JPH03255625A - Semiconductor manufacturing device - Google Patents
Semiconductor manufacturing deviceInfo
- Publication number
- JPH03255625A JPH03255625A JP5422290A JP5422290A JPH03255625A JP H03255625 A JPH03255625 A JP H03255625A JP 5422290 A JP5422290 A JP 5422290A JP 5422290 A JP5422290 A JP 5422290A JP H03255625 A JPH03255625 A JP H03255625A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- electrode
- lower electrode
- buried
- electrostatic chuck
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 238000000034 method Methods 0.000 abstract description 16
- 238000005530 etching Methods 0.000 abstract description 15
- 239000012212 insulator Substances 0.000 abstract description 11
- 239000000919 ceramic Substances 0.000 abstract description 7
- 230000002159 abnormal effect Effects 0.000 abstract description 3
- 235000012431 wafers Nutrition 0.000 description 39
- 238000001020 plasma etching Methods 0.000 description 14
- 239000007789 gas Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010849 ion bombardment Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 210000000078 claw Anatomy 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔概 要〕
半導体製造装置、例えば、プラズマエツチング装置にお
ける静電チャックを含む電極の構造に関し、
低い周波数の電源を用いて、しかも、ウェハーを静電チ
ャッキングして良好に処理することを目的とし、
ウェハーを載置する下部電極を備え、該下部電極がウェ
ハーに近接して位置した静電チャック電極板と、ウェハ
ーに対して静電チャック電極板より遠くに位置した高周
波用電極板とを、絶縁体内にウェハーに平行して埋没さ
せた構造を有することを特徴とする。[Detailed Description of the Invention] [Summary] Regarding the structure of an electrode including an electrostatic chuck in a semiconductor manufacturing device, for example, a plasma etching device, the present invention relates to a structure of an electrode including an electrostatic chuck in a semiconductor manufacturing device, for example, a plasma etching device, which uses a low frequency power source, and moreover, can perform good electrostatic chucking of a wafer. The electrostatic chuck electrode plate has a lower electrode on which the wafer is placed, and the lower electrode is located close to the wafer, and the electrostatic chuck electrode plate is located further away from the wafer than the electrostatic chuck electrode plate. It is characterized by having a structure in which a high frequency electrode plate is buried in an insulator parallel to the wafer.
本発明は半導体製造装置、例えば、プラズマエツチング
装置における静電チャックを含む電極の構造に関する。The present invention relates to the structure of an electrode including an electrostatic chuck in semiconductor manufacturing equipment, such as plasma etching equipment.
ウェハープロセスにおいては、プラズマエツチング装置
やプラズマ化学気相成長（プラズマＣｖＤ）装置が用い
られており、そのような装置は電極間に高周波を印加し
て、一方の電極にはウェハーを載置しているが、そのウ
ェハーのチャッキングを含む電極の構造は製造装置の性
能に大きく影響するためにその構造は重要であり、本発
明はその電極の改善に関している。In wafer processing, plasma etching equipment and plasma chemical vapor deposition (plasma CVD) equipment are used. Such equipment applies high frequency waves between electrodes, and places the wafer on one electrode. However, the structure of the electrode including chucking of the wafer is important because it greatly affects the performance of the manufacturing equipment, and the present invention relates to improvement of the electrode.
例えば、プラズマエツチング装置はりアクティブイオン
エツチング（ＲＴＥ）方法が適用されて、対向配置した
２枚の平行平板電極のうちの一方の電極にウェハー（被
エツチング基板）を載置する平行平板型の電極構造が採
られている。For example, in a plasma etching device, an active ion etching (RTE) method is applied, and a wafer (substrate to be etched) is placed on one of two parallel plate electrodes arranged facing each other, which has a parallel plate type electrode structure. is taken.
第３図はプラズマエツチング装置の要部断面図を示して
おり、図中の記号１は真空チャンバ、２は上部電極、３
は下部電極、４はウェハー、５はガス導入０．６は排気
口、７は高周波電源（周波数５ Ｋ）ＩＺ〜１３．５６
ＭＨ２）である。図示のように、高周波を印加した下部
電極３と上部電極２とを対向配置し、下部電極３上に載
置したウェハー４に対して上部電極２の下面から反応ガ
スを垂直に噴射して反応ガスをプラズマ化し、ウェハー
４にそのプラズマガスを衝突させてエツチングする装置
である。Figure 3 shows a cross-sectional view of the main parts of the plasma etching apparatus, in which symbol 1 is a vacuum chamber, 2 is an upper electrode, and 3 is a vacuum chamber.
is the lower electrode, 4 is the wafer, 5 is the gas introduction port, 0.6 is the exhaust port, 7 is the high frequency power supply (frequency 5 K) IZ ~ 13.56
MH2). As shown in the figure, a lower electrode 3 to which a high frequency has been applied and an upper electrode 2 are arranged facing each other, and a reaction gas is vertically injected from the lower surface of the upper electrode 2 to a wafer 4 placed on the lower electrode 3 to cause a reaction. This device converts gas into plasma and causes the plasma gas to collide with the wafer 4 for etching.
このようなプラズマエツチング装置には接地電極側にウ
ェハーを載置するアノードカップル型と上記第３図のよ
うな高周波電源側にウエノ＼−を載置するカソードカッ
プル型との二種類があるが、その性能には差異はない。There are two types of plasma etching equipment: an anode couple type in which the wafer is placed on the ground electrode side, and a cathode couple type in which the wafer is placed on the high frequency power source side as shown in Figure 3 above. There is no difference in performance.
しかし、−船釣には１３゜５６ＭＨ２程度の高い周波数
の電源を用いる場合はカソードカップル型にして多結晶
シリコン膜や窒化シリコン膜のエツチングに用い、４０
０ＫＨ２程度の低い周波数の電源を用いる場合はアノー
ドカップル型にして酸化シリコン膜をエツチングするこ
とが多い。However, when using a power source with a high frequency of about 13°56 MH2 for boat fishing, a cathode couple type power source is used for etching polycrystalline silicon films or silicon nitride films.
When using a power source with a low frequency of about 0KH2, an anode couple type is often used to etch the silicon oxide film.
ところで、上記のようなドライエツチング装置において
、ウェハー４を＠置する下部電極３にエツチング特性に
かかわる問題があり、それを第４図に示す従来の下部電
極の構造断面図によって説明する。即ち、ウェハーをた
だ自由に載せるだけではエツチング処理中に動き、また
、密着させて冷却を良くするために、ウェハーを下部電
極に固定させる必要がある。その方法として、従来から
第４図（ａ）に示す機械的に押さえる方法と第４図（ｂ
）に示すクーロン力によって静電チャッキングする方法
との二種類が知られている。図中の記号４はウェハー、
３０．３１は高周波用電極、３２は押さえ爪。By the way, in the dry etching apparatus as described above, there is a problem related to the etching characteristics of the lower electrode 3 on which the wafer 4 is placed, and this will be explained with reference to the structural cross-sectional view of the conventional lower electrode shown in FIG. That is, if the wafer is simply placed freely, it will move during the etching process, and it is necessary to fix the wafer to the lower electrode in order to bring it into close contact and improve cooling. Conventionally, there is a mechanical pressing method shown in FIG. 4(a) and a method of mechanically pressing as shown in FIG.
) There are two known methods: electrostatic chucking using Coulomb force. Symbol 4 in the figure is a wafer,
30.31 is a high frequency electrode, and 32 is a presser claw.
３３は静電チャック体、３４は直流電源である。33 is an electrostatic chuck body, and 34 is a DC power source.
そのうち、第４図（ａ）に示す機械的な押着法は幾多の
機械部品を真空チャンバｌ内に持ち込むことになるため
にゴミが発生し易く、ウェハーの品質を低下させる心配
があって好ましくない。また、この方法はドライエツチ
ング装置の作成や装置の取扱も面倒になる。Among these, the mechanical pressing method shown in FIG. 4(a) is preferable because it involves bringing many mechanical parts into the vacuum chamber, which tends to generate dust, which may reduce the quality of the wafer. do not have. Furthermore, this method also makes it difficult to create and handle the dry etching device.
従って、第４図（ｂ）に示す静電チャッキング法を用い
ることが望ましい。しかし、例えば、ＲＴＥ法で弗素系
ガスを用いてシリコン化合物をエツチングする場合、多
結晶シリコン膜や窒化シリコン膜のような化学反応が主
体となってエツチングが進行する被エツチング膜では、
１３．５６ＭＨ２程度の高い周波数の電源によってエツ
チングしてもエツチング速度が早くて問題はない。しか
し、Ｓｉｎ。Therefore, it is desirable to use the electrostatic chucking method shown in FIG. 4(b). However, when etching a silicon compound using a fluorine-based gas using the RTE method, for example, a film to be etched, such as a polycrystalline silicon film or a silicon nitride film, in which etching progresses mainly through a chemical reaction,
Even if etching is performed using a power source with a high frequency of about 13.56 MH2, the etching speed is fast and there is no problem. However, Sin.
（酸化シリコン）膜のようなイオン衝撃による物理的食
刻が主体になってエツチングされる被エツチング膜では
、３８０〜４００Ｋ）ＩＺ程度の低い周波数の電源を用
いた方がイオン衝撃が太き（てエツチング速度が早くな
る。For a film to be etched, such as a (silicon oxide) film, which is mainly etched by physical etching by ion bombardment, it is better to use a power source with a low frequency of about 380 to 400 K) IZ, as the ion bombardment will be stronger ( This increases the etching speed.
そのため、３８０〜４００ＫＨ２程度の低い周波数の電
源を用いてエツチングすることが要望されるが、その低
い周波数の電源を用いた場合、静電チャック体３３は厚
い絶縁体であるから低い周波数の電力の通過が妨害され
て、露出した高周波用電極の側部（第４図（ｂ）に矢印
で示す）で異常放電が起こり、満足に精度良くエツチン
グできないという問題が起こる。この静電チャック体３
３は導体を埋めたセラミック絶縁板からなり、口径８イ
ンチφのウェハーをチャンキングするためには板厚を６
ｍｍ程度より薄く作成することは歪みが発生するから、
ある程度の厚みが必要になり、それが高周波電力の通過
を妨げることになっている。Therefore, it is desired to perform etching using a power source with a low frequency of about 380 to 400KH2. However, if such a low frequency power source is used, the electrostatic chuck body 33 is a thick insulator, so the low frequency power is The passage is obstructed, and abnormal discharge occurs at the exposed side of the high-frequency electrode (indicated by the arrow in FIG. 4(b)), resulting in a problem that etching cannot be carried out with satisfactory accuracy. This electrostatic chuck body 3
3 is made of a ceramic insulating plate with a conductor buried in it, and in order to chunk a wafer with a diameter of 8 inches, the plate thickness must be 6.
Making it thinner than about mm will cause distortion, so
A certain degree of thickness is required, which obstructs the passage of high-frequency power.
本発明はこのような問題点を解消させて、低い周波数の
電源を用いて、しかも、ウェハーを静電チャッキングし
て良好に処理することを目的とした半導体製造装置を提
案するものである。The present invention solves these problems and proposes a semiconductor manufacturing apparatus that uses a low-frequency power source and also performs electrostatic chucking of wafers to efficiently process the wafers.
その課題は、ウェハーを載置する下部電極を備え、該下
部電極が、第１図に示すように、ウェハーに近接して位
置した静電チャック電極板１２と、ウェハーに対して静
電チャック電極板より遠くに位置した高周波用電極板１
３とを、絶縁体１１内にウェハーに平行して埋没させた
構造を有する半導体製造装置によって解決される。The problem is that the lower electrode is provided with a lower electrode on which the wafer is placed, and the lower electrode is connected to an electrostatic chuck electrode plate 12 located close to the wafer, as shown in FIG. High frequency electrode plate 1 located further away from the plate
3 is solved by a semiconductor manufacturing apparatus having a structure in which the wafer is buried in the insulator 11 in parallel with the wafer.
即ち、本発明は、ウェハーに対して静電チャック電極板
と高周波用電極板とをほぼ同程度の大きさで平行に近接
して絶縁体内に配置した下部電極を設ける。即ち、従来
の静電チャック体の中に高周波用電極を取り込んだ構造
にする。そうすると、ウェハーを静電チャッキングし、
低い周波数の電源を用いて、早い速度で均一に処理する
ことが可能になる。That is, in the present invention, a lower electrode is provided in which an electrostatic chuck electrode plate and a high-frequency electrode plate are arranged in parallel and close to each other in an insulator and have approximately the same size with respect to a wafer. That is, the structure is such that a high frequency electrode is incorporated into a conventional electrostatic chuck body. Then, the wafer is electrostatically chucked,
By using a low frequency power source, it becomes possible to process uniformly at a high speed.
以下に図面を参照して実施例によって詳細に説明する。 Examples will be described in detail below with reference to the drawings.
第１図（ａ）、 （ｂ）は本発明に関わりある下部電極
の構造図を示しており、同図（ａ）は同図（ｂ）のＡＡ
断面図、同図（ｂ）は平面図である。図中の記号１１は
セラミック絶縁体、１２はタングステンからなる静電チ
ャック電極板、１３は同しくタングステンからなる高周
波用電極板で、１２Ｔは静電チャック電極板の取出し端
子、１３Ｔは高周波用電極板の取出し端子りは高周波用
電極板における周辺凹部（静電チャック電極板１２から
取出し端子１２Ｔに接続する導線のための凹部）である
。例えば、直径＝ ２００ｍｍφ。FIGS. 1(a) and 1(b) show structural diagrams of the lower electrode related to the present invention, and FIG. 1(a) shows the structure of the lower electrode in FIG.
The cross-sectional view is a plan view. In the figure, symbol 11 is a ceramic insulator, 12 is an electrostatic chuck electrode plate made of tungsten, 13 is a high frequency electrode plate also made of tungsten, 12T is an extraction terminal of the electrostatic chuck electrode plate, and 13T is a high frequency electrode. The take-out terminal of the plate is a peripheral recess in the high-frequency electrode plate (a recess for a conducting wire connected from the electrostatic chuck electrode plate 12 to the take-out terminal 12T). For example, diameter = 200mmφ.
厚さｆ＝１０＋ｎｍのセラミック絶縁体の中にウェハー
を載置する表面からの間隔ｍ＝２００μｍをとって静電
チャック電極板１２を埋没させ、それより間隔ｎ＝５０
０ｕｍをとって高周波用電極板が埋没させた構成とする
。且つ、このような構成の下部電極はセラミック絶縁体
全体の厚みを十分に厚くしても良く、高い寸法精度で作
成できる。The electrostatic chuck electrode plate 12 is buried in a ceramic insulator having a thickness of f=10+nm with a distance m=200 μm from the surface on which the wafer is placed, and then a distance n=50 μm is taken from the surface on which the wafer is placed.
0 um is taken, and the high frequency electrode plate is buried. In addition, the lower electrode having such a configuration may have a sufficiently thick ceramic insulator as a whole, and can be manufactured with high dimensional accuracy.
かくして、このような下部電極を配置すれば、３８０〜
４００ＫＨｚ程度の低い周波数の電源を用い、早いエツ
チング速度で、異常プラズマ放電を起こすことなく、ウ
ェハー面を精度良くエツチングできる。Thus, if such a lower electrode is arranged, 380~
Using a power source with a low frequency of about 400 KHz, the wafer surface can be etched with high precision at a high etching speed without causing abnormal plasma discharge.
次の第２図は本発明にかかるプラズマエツチング装置に
おける電気的接続の要部図を示している。The following FIG. 2 shows a diagram of essential parts of electrical connections in the plasma etching apparatus according to the present invention.
記号は第１図および第３図と同一部位に同一記号が付け
であるが、その他の記号３５はＲＦカットフィルタ、３
６はウェハー搬送ピンである。本発明に関わる下部電極
をプラズマエツチング装置に配置しても静電チャック電
極板１２および高周波用電極板１３は円板のまま無加工
で取り付けることは困難で、例えば、自動インライン方
式中の一装置として配設されたプラズマエツチング装置
では、その下部電極中の電極板１２．１３を透過させて
ウェハー搬送ビン３６を取り付ける必要がある。また、
熱伝導を良くするために下部電極とウェハーとの間にヘ
リウム（Ｈｅ）ガスを僅かに送入しているが、そのガス
送入孔を下部電極に設ける必要があり、そのために電極
板１２．１３に孔をあけている。しかし、電極板１２．
１３に設ける孔はウェハー面でのプラズマ分布を乱さな
いためには、３ＩＩｌｆｆｌφ以下の孔径にすることが
重要である。The same symbols are attached to the same parts as in FIGS. 1 and 3, but the other symbols 35 are RF cut filters, 3
6 is a wafer transfer pin. Even if the lower electrode according to the present invention is placed in a plasma etching device, it is difficult to attach the electrostatic chuck electrode plate 12 and the high frequency electrode plate 13 as disks without machining. In a plasma etching apparatus configured as a plasma etching apparatus, it is necessary to attach the wafer transport bin 36 through the electrode plate 12, 13 in the lower electrode. Also,
A small amount of helium (He) gas is injected between the lower electrode and the wafer in order to improve heat conduction, but it is necessary to provide a gas inlet hole in the lower electrode, so the electrode plate 12. A hole is drilled at 13. However, the electrode plate 12.
In order not to disturb the plasma distribution on the wafer surface, it is important that the hole provided in the hole 13 has a diameter of 3IIlfflφ or less.
上記に説明した下部電極を設けると、ウェハープロセス
の効率化、高品質化に寄与するプラズマエツチング装置
が得られ、且つ、装置自身も小型化することができる。By providing the above-described lower electrode, a plasma etching apparatus that contributes to increased efficiency and higher quality of the wafer process can be obtained, and the apparatus itself can also be made smaller.
更に、そのような下部電極は１３．５６ＭＨ２程度の高
い周波数の電源を用いる平行平板型のプラズマＣＶＤ装
置に配置しても良く、且つ、エツチング装置のみならず
、プラズマＣＶＤ装置に配置しても同様の効果が得られ
るものである。Furthermore, such a lower electrode may be placed in a parallel plate type plasma CVD apparatus that uses a power source with a high frequency of about 13.56 MH2, and can be placed not only in an etching apparatus but also in a plasma CVD apparatus. The following effects can be obtained.
以上の説明から明らかなように、本発明にかかる半導体
製造装置によれば、コンパクトな下部電極が設けられて
装置の小型化に役立ち、且つ、ウェハープロセスの効率
化、半導体デバイスの高品質化に大きく寄与するもので
ある。As is clear from the above description, according to the semiconductor manufacturing apparatus according to the present invention, a compact lower electrode is provided, which contributes to miniaturization of the apparatus, and improves the efficiency of the wafer process and the quality of semiconductor devices. This will make a major contribution.
第１図（ａ）、 （ｂ）は本発明に関わりある下部電極
の構造図、
第２図は本発明にかかるプラズマエツチング装置におけ
る電気的接続の要部図、
第３図はプラズマエツチング装置の要部断面図、第４図
（ａ）、 （ｂ）は従来の下部電極の構造断面図である
。
図において、
１は真空チャンバ、
２は上部電極、 ３は下部電極、４はウェハー
５はガス導入口、６は排気口、
７は高周波電源、１１はセラミック絶縁体、
１２は静電チャック電極板、
１３は高周波用電極板、
１２Ｔ 、 １３Ｔは端子、
３４は直流電源、
３５はＲＦカットフィルタ、
３６はウェハー搬送ビン
を示している。
１２静電チｖ・７７電赦志
？１発θ昂；関イっソＡシ下音戸哨定〉なしのｉ造１１
Ｚｒ第１図Figures 1 (a) and (b) are structural diagrams of the lower electrode related to the present invention, Figure 2 is a diagram of the main electrical connections in the plasma etching apparatus according to the present invention, and Figure 3 is a diagram of the plasma etching apparatus. FIGS. 4(a) and 4(b) are cross-sectional views of the structure of a conventional lower electrode. In the figure, 1 is a vacuum chamber, 2 is an upper electrode, 3 is a lower electrode, 4 is a wafer, 5 is a gas inlet, 6 is an exhaust port,
7 is a high frequency power supply, 11 is a ceramic insulator, 12 is an electrostatic chuck electrode plate, 13 is a high frequency electrode plate, 12T and 13T are terminals, 34 is a DC power supply, 35 is an RF cut filter, and 36 is a wafer transfer bin. ing. 12 Electrostatic Chi v. 77 Denkyoshi? 1 shot θ; I-Zou 11 without Seki Iso A Shimoondo patrol
Zr Figure 1
Claims (1)
ェハーに近接して位置した静電チャック電極板と、ウェ
ハーに対して静電チャック電極板より遠くに位置した高
周波用電極板とを、絶縁体内にウェハーに平行して埋没
させた構造を有することを特徴とする半導体製造装置。An electrostatic chuck electrode plate is provided with a lower electrode on which a wafer is placed, and the lower electrode is located close to the wafer, and a high frequency electrode plate is located farther from the electrostatic chuck electrode plate with respect to the wafer. A semiconductor manufacturing device characterized by having a structure buried in a body parallel to a wafer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5422290A JPH03255625A (en) | 1990-03-05 | 1990-03-05 | Semiconductor manufacturing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5422290A JPH03255625A (en) | 1990-03-05 | 1990-03-05 | Semiconductor manufacturing device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03255625A true JPH03255625A (en) | 1991-11-14 |
Family
ID=12964510
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5422290A Pending JPH03255625A (en) | 1990-03-05 | 1990-03-05 | Semiconductor manufacturing device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03255625A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1995014308A1 (en) * | 1993-11-18 | 1995-05-26 | Ngk Insulators, Ltd. | Electrode for generating plasma, element for burying electrode, and method for manufacturing the electrode and the element |
| US5633073A (en) * | 1995-07-14 | 1997-05-27 | Applied Materials, Inc. | Ceramic susceptor with embedded metal electrode and eutectic connection |
| US5800618A (en) * | 1992-11-12 | 1998-09-01 | Ngk Insulators, Ltd. | Plasma-generating electrode device, an electrode-embedded article, and a method of manufacturing thereof |
| US5817406A (en) * | 1995-07-14 | 1998-10-06 | Applied Materials, Inc. | Ceramic susceptor with embedded metal electrode and brazing material connection |
| WO2001058828A1 (en) * | 2000-02-07 | 2001-08-16 | Ibiden Co., Ltd. | Ceramic substrate for semiconductor production/inspection device |
| US7011874B2 (en) | 2000-02-08 | 2006-03-14 | Ibiden Co., Ltd. | Ceramic substrate for semiconductor production and inspection devices |
-
1990
- 1990-03-05 JP JP5422290A patent/JPH03255625A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5800618A (en) * | 1992-11-12 | 1998-09-01 | Ngk Insulators, Ltd. | Plasma-generating electrode device, an electrode-embedded article, and a method of manufacturing thereof |
| US6101969A (en) * | 1992-11-12 | 2000-08-15 | Ngk Insulators, Ltd. | Plasma-generating electrode device, an electrode-embedded article, and a method of manufacturing thereof |
| US6197246B1 (en) | 1992-11-12 | 2001-03-06 | Ngk Insulators, Ltd. | Plasma-generating electrode device, an electrode-embedded article, and a method of manufacturing thereof |
| WO1995014308A1 (en) * | 1993-11-18 | 1995-05-26 | Ngk Insulators, Ltd. | Electrode for generating plasma, element for burying electrode, and method for manufacturing the electrode and the element |
| US5633073A (en) * | 1995-07-14 | 1997-05-27 | Applied Materials, Inc. | Ceramic susceptor with embedded metal electrode and eutectic connection |
| US5817406A (en) * | 1995-07-14 | 1998-10-06 | Applied Materials, Inc. | Ceramic susceptor with embedded metal electrode and brazing material connection |
| WO2001058828A1 (en) * | 2000-02-07 | 2001-08-16 | Ibiden Co., Ltd. | Ceramic substrate for semiconductor production/inspection device |
| US6891263B2 (en) | 2000-02-07 | 2005-05-10 | Ibiden Co., Ltd. | Ceramic substrate for a semiconductor production/inspection device |
| US7011874B2 (en) | 2000-02-08 | 2006-03-14 | Ibiden Co., Ltd. | Ceramic substrate for semiconductor production and inspection devices |
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