JPH03241176A - Layout structure of building for semiconductor manufacturing factory - Google Patents
Layout structure of building for semiconductor manufacturing factoryInfo
- Publication number
- JPH03241176A JPH03241176A JP3467290A JP3467290A JPH03241176A JP H03241176 A JPH03241176 A JP H03241176A JP 3467290 A JP3467290 A JP 3467290A JP 3467290 A JP3467290 A JP 3467290A JP H03241176 A JPH03241176 A JP H03241176A
- Authority
- JP
- Japan
- Prior art keywords
- section
- building
- semiconductor
- semiconductor manufacturing
- manufacturing factory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 235000012431 wafers Nutrition 0.000 claims abstract description 12
- 238000012545 processing Methods 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 34
- 239000000126 substance Substances 0.000 abstract description 2
- 238000011282 treatment Methods 0.000 abstract description 2
- 238000000206 photolithography Methods 0.000 description 9
- 238000009792 diffusion process Methods 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000004378 air conditioning Methods 0.000 description 2
- 238000012993 chemical processing Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 241000257465 Echinoidea Species 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000011144 upstream manufacturing Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野］
この発明ａ半導体製造工場の！ａ屋クレイアウト構造関
し、特に被処理半導体ウェハに対するＦＡ機能構造を提
供するものである。[Detailed Description of the Invention] [Industrial Field of Application] This invention a semiconductor manufacturing factory! Regarding the A-ya layout structure, in particular, it provides an FA functional structure for semiconductor wafers to be processed.
第３図は従来の半導体製造工場の建屋レイアウト構造の
平面図で１図にかいて、Ｃ１１）は写真製版プロセス部
、０．１は化学処理プロセス部、（Ｌｌｌ’を拡散プロ
セス部、圓は成膜プロセス部、＠はイオン注入プロセス
部、ａａは被処理半導体ウェハの各物流方向を示す。Figure 3 is a plan view of the building layout structure of a conventional semiconductor manufacturing factory. The film forming process section, @ indicates the ion implantation process section, and aa indicates each flow direction of the semiconductor wafer to be processed.
第４図は第３図の側面工υ見た建屋レイアウト構造を示
す。図にかいて、（ロ）は半１体つエノ・プロセス部、
明はユーテイリイテイ部、ＣＬ嶋ｒｉ空ｔ１１部を示す
。次に、被処理半透体ウェハの物流について第３図を用
いて説明する。被処理半導体ウェハは半導体製造工場に
投入された後、拡散プロセス部αＱから写真製版プロセ
ス部（ロ）を経て、イオン注入プロセス部＠から化学処
理プロセス部（至）又は、成膜プロセス部ａ４から写真
製版プロセス部０又は。Figure 4 shows the building layout structure seen from the side view of Figure 3. In the figure, (b) is a half-body Eno process part,
Light indicates the utility section and CL Shima ri empty t11 section. Next, the distribution of semitransparent wafers to be processed will be explained using FIG. 3. After the semiconductor wafer to be processed is introduced into the semiconductor manufacturing factory, it passes from the diffusion process section αQ to the photolithography process section (B), from the ion implantation process section @ to the chemical processing section (to), or from the film formation process section A4. Photolithography process department 0 or.
拡散プロセスｓ叫から写真製版プロセス部Ｑｌ）を経て
成膜プロセス部α４から写真製版プロセス部（ロ）とい
う処理工Ｓを順次進んで行く。The process sequentially proceeds from the diffusion process S to the photolithography process section Ql), and then to the film forming process section α4 and then to the photolithography process section (B).
従来の半導体製造工場にシいて、ウェハプロセス工程が
進むにつれて化学処理、写真製版、拡散。In traditional semiconductor manufacturing plants, chemical treatments, photolithography, and diffusion are used as the wafer process progresses.
敗膜、イオン注入などの各プロセス部は建屋横方向へ繰
υ返し設置されてかや、被処理半這体ウエハは後戻りを
しないようにｌｌ或される。Process sections such as membrane removal and ion implantation are repeatedly installed in the lateral direction of the building, and half-sized wafers to be processed are moved back so as not to move back.
［発明が解決しようとするｆｆ１９１
従来の半導体製造工場の建屋レイアウト構造は以上の様
に１１１１或されていたので、建屋が横方向に大きく拡
がシ、写真製版など何回も使用されるプロセス部にＤい
ては設置場所の装置の処理負荷が少なく、他の場所の装
置が負荷オーバーになってもＦＡＫ工っての半導体ウェ
ハの物流が困雌でその部分ヘウエハを送ることが不可で
あるなど半導体製造に柔軟性が無いなどの問題点があっ
た。[ff191 to be solved by the invention Since the building layout structure of the conventional semiconductor manufacturing factory was 1111 as described above, the building had to be expanded horizontally, and process parts such as photolithography were used many times. In D, the processing load on the equipment at the installation location is low, and even if the equipment at other locations becomes overloaded, the distribution of semiconductor wafers at the FAK facility is difficult and it is impossible to send wafers to that location. There were problems such as lack of flexibility in semiconductor manufacturing.
この発明は上記の様な問題点を解消するためになされた
もので、製造工場を小さくでさるとともに各プロセス部
を集合させ半導体製造に柔軟性を持たせることのできる
半導体製造工場の建屋レイアウトｔ！ｌ得ることを目的
とする。This invention was made in order to solve the above-mentioned problems.The building layout of the semiconductor manufacturing factory allows the manufacturing factory to be made smaller, and each process section is grouped together to provide flexibility in semiconductor manufacturing. ! The purpose is to obtain.
この発明に係る半導体製造工場の建屋レイアウト構造は
、建ｍを上面から見た場合円形もしくは５角以上の多角
形にするとともに、各半導体プロセスをパイチャートの
ごとく配置するＬうにしたものである。The building layout structure of a semiconductor manufacturing factory according to the present invention is such that the building m is circular or polygonal with five or more sides when viewed from above, and each semiconductor process is arranged like a pie chart.
この発明にかける半導体製造工場の建屋レイアウト構造
は、被処理半導体ウエノ・の物Ｒ，を単純化して建屋ス
ペースを小さく出来るＯ
〔実施例〕
以下、この発明の一実施例を図について説明する。第１
図はこの発明の一実施例である半導体製造工場のＩ屋の
平面図で、図にかいて、（１）は化学処理プロセス部、
（２）は写真製版プロセス部、（３）は拡散プロセス部
、（４）は成膜プロセス部、（５）はイオン注入プロセ
ス部、（６）は被処理半導体ウニ／・を各プロセス部へ
配分するＦＡ機能部である。The building layout structure of a semiconductor manufacturing factory according to the present invention can simplify the semiconductor material R to be processed and reduce the building space. [Example] Hereinafter, an example of the present invention will be described with reference to the drawings. 1st
The figure is a plan view of an I room in a semiconductor manufacturing factory which is an embodiment of the present invention.
(2) is the photolithography process section, (3) is the diffusion process section, (4) is the film formation process section, (5) is the ion implantation process section, and (6) is the semiconductor urchin to be processed to each process section. This is the FA functional department that allocates.
第２図は第１図の半導・体製造工場の側面図で、図にか
いて、（８）は半導体ウニ／％プロセス部、（９）はユ
ーテイリイテイ部、（７）は空調部である。Figure 2 is a side view of the semiconductor/device manufacturing factory shown in Figure 1. In the figure, (8) is the semiconductor processing section, (9) is the utility section, and (7) is the air conditioning section. .
被処理半導体ウニノ・が製造工場に投入され、被処理半
導体ウニノ・は化学処理プロセス部ｆｌ）から写真製版
プロセス５（２）を経て、拡散プロセス部（３）から成
膜プロセス部（４）からイオン注入プロセス５（５）で
順次処理されていくが、各プロセス部がパイチャートの
ごとく配置されている為、中央に設置されたＦＡ機能部
（６）を被処理半導体ウニノ）ｒｉ経由するのみで済み
、又、各プロセス部に設置された装置はプロセス上流用
出来ないものを除いてどのプロセス工程のものも処理出
来稼動率は向上する０なか、上記実施例にかいては半導
体プロセスをＳ屋の１階分だけについて示したが、中央
のＦＡ機能を複数階に延長させても良い。The semiconductor to be processed is put into the manufacturing factory, and the semiconductor to be processed is transferred from the chemical processing section (fl) to the photolithography process 5 (2), from the diffusion processing section (3) to the film formation processing section (4). It is sequentially processed in the ion implantation process 5 (5), but since each process section is arranged like a pie chart, it only passes through the FA function section (6) installed in the center of the semiconductor to be processed. In addition, the equipment installed in each process section can process any process step except those that cannot be used upstream, improving the operating rate.In the above embodiment, however, the semiconductor process is Although only one floor of the building is shown, the central FA function may be extended to multiple floors.
また、上記実施例では建屋の構造を円形構造とした場合
を示したが、円形に限定するものではなく例えば５角形
以上の多角形状としても同等の効果がある。Further, in the above embodiment, the structure of the building is circular, but it is not limited to a circular shape, and the same effect can be obtained by using a polygonal shape, for example, a pentagon or more.
以上の様にこの発明によれば、半導体製造工場を円形も
しくは５角形以上の多角形状にし、各クエハプロセスヲ
ハイチャートのごとく配置したので、プロセス装置の有
効活用及び稼動″４を向上させて、建屋敷地面積を小さ
くすることが出来るという効果が得られる。As described above, according to the present invention, the semiconductor manufacturing factory is made into a circular or polygonal shape of more than a pentagon, and each wafer process is arranged like a high chart, thereby improving the effective utilization and operation of process equipment. This has the effect of reducing the building site area.
第１図はこの発明一実施例による半導体製造工場の建屋
レイアウト構造を示す平面図、第２図は第１図側面図、
第３図は従来の半導体製造工場の建屋レイアウト構造を
示す平面図、第４図は第３図の＠面図を示す０
図にかいて、（１）は化学処理プロセス部、（２）は写
真製版プロセス部、（３）は拡散プロセス部、（４）ｉ
成膜プロセス部、（５）はイオン注入プロセス部、（６
）はＦＡ機能部、（７）は空調部、（８）は半導体クエ
７％プロセス部、（９）ｒ！ユーテイリイテイ部を示す
。FIG. 1 is a plan view showing the building layout structure of a semiconductor manufacturing factory according to an embodiment of the present invention, FIG. 2 is a side view of the building shown in FIG.
Fig. 3 is a plan view showing the building layout structure of a conventional semiconductor manufacturing factory, and Fig. 4 is an @ side view of Fig. 3. Photolithography process section, (3) diffusion process section, (4) i
Film formation process section, (5) is ion implantation process section, (6
) is the FA function department, (7) is the air conditioning department, (8) is the semiconductor query 7% process department, (9) r! Shows the utility section.
Claims (1)
屋の構造が上面から見た場合円形もしくは５角形以上の
多角形状とし、その中央部分には被処理半導体ウェハを
各半導体プロセス部へ配送するＦＡ機能部とし、その周
辺の半導体製造プロセス部分は各工程毎にパイチャート
のごとく分離され配置されていることを特徴とする半導
体製造工場の建屋レイアウト構造。In the building layout structure of a semiconductor manufacturing factory, the structure of the building is circular or a polygon of pentagon or more when viewed from the top, and the central part thereof has an FA function unit that delivers semiconductor wafers to be processed to each semiconductor processing department. A building layout structure of a semiconductor manufacturing factory, characterized in that the surrounding semiconductor manufacturing process parts are separated and arranged like a pie chart for each process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3467290A JP2692325B2 (en) | 1990-02-15 | 1990-02-15 | Semiconductor manufacturing factory building layout structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3467290A JP2692325B2 (en) | 1990-02-15 | 1990-02-15 | Semiconductor manufacturing factory building layout structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03241176A true JPH03241176A (en) | 1991-10-28 |
| JP2692325B2 JP2692325B2 (en) | 1997-12-17 |
Family
ID=12420919
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3467290A Expired - Fee Related JP2692325B2 (en) | 1990-02-15 | 1990-02-15 | Semiconductor manufacturing factory building layout structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2692325B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6099599A (en) * | 1996-05-08 | 2000-08-08 | Industrial Technology Research Institute | Semiconductor device fabrication system |
| US6748704B2 (en) | 2000-10-19 | 2004-06-15 | Renesas Technology Corp. | Factory layout |
| CN105735686A (en) * | 2014-11-20 | 2016-07-06 | 中国中元国际工程有限公司 | Super large combined workshop and plane arrangement method |
-
1990
- 1990-02-15 JP JP3467290A patent/JP2692325B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6099599A (en) * | 1996-05-08 | 2000-08-08 | Industrial Technology Research Institute | Semiconductor device fabrication system |
| US6748704B2 (en) | 2000-10-19 | 2004-06-15 | Renesas Technology Corp. | Factory layout |
| CN105735686A (en) * | 2014-11-20 | 2016-07-06 | 中国中元国际工程有限公司 | Super large combined workshop and plane arrangement method |
| CN105735686B (en) * | 2014-11-20 | 2018-05-15 | 中国中元国际工程有限公司 | Ultra-large type complex factories and its horizontal layout method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2692325B2 (en) | 1997-12-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5795356A (en) | Microelectronic component fabrication facility, and process for making and using the facility | |
| US6748704B2 (en) | Factory layout | |
| US5350336A (en) | Building and method for manufacture of integrated semiconductor circuit devices | |
| US6099599A (en) | Semiconductor device fabrication system | |
| EP2613340A1 (en) | Device manufacturing apparatus and method therefor | |
| JP2004055823A (en) | Semiconductor integrated circuit | |
| US6264550B1 (en) | Clean room and method of remodeling clean room | |
| JPH03241176A (en) | Layout structure of building for semiconductor manufacturing factory | |
| JP2853677B2 (en) | Semiconductor device manufacturing line | |
| JPS63184330A (en) | Baking device for photoresist | |
| US6190424B1 (en) | Process for fabricating two different types of wafers in a semiconductor wafer production line | |
| JPH05251337A (en) | Formation method of resist pattern | |
| JPH0917703A (en) | Production instruction system | |
| JPH06302667A (en) | Chamber system | |
| JP3787599B2 (en) | Clean room building | |
| JPH0282032U (en) | ||
| Campbell et al. | A model of a 300mm wafer fabrication line | |
| JP3275700B2 (en) | Structure with clean room | |
| US20020165633A1 (en) | System and method for managing work-in-process (WIP) workload within a fabrication facility | |
| JP2634795B2 (en) | Wafer processing equipment | |
| KR100269570B1 (en) | Wafer fab | |
| EP1062681A1 (en) | Production facility for integrated circuits | |
| TW468203B (en) | Improved semiconductor manufacturing system | |
| JPH0286167A (en) | Master slice system integrated circuit device | |
| JPH07180871A (en) | Multi-storied clean room |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |