JPH03231508A - Glitch elimination circuit - Google Patents
Glitch elimination circuitInfo
- Publication number
- JPH03231508A JPH03231508A JP2026597A JP2659790A JPH03231508A JP H03231508 A JPH03231508 A JP H03231508A JP 2026597 A JP2026597 A JP 2026597A JP 2659790 A JP2659790 A JP 2659790A JP H03231508 A JPH03231508 A JP H03231508A
- Authority
- JP
- Japan
- Prior art keywords
- point
- output
- resistor
- input
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000008030 elimination Effects 0.000 title 1
- 238000003379 elimination reaction Methods 0.000 title 1
- 239000003990 capacitor Substances 0.000 abstract description 10
- 238000010586 diagram Methods 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明はグリッジ除去回路に関するものでわるＯ
〔従来の技術〕
第３図は従来のグリッジ除去回路の回路図で、図におい
て、（１）は入力の切換端子、（２） 、 （３）は入
力端子、（５） 、 （６） 、 （７）は入力信号Ａ
、Ｂを切換端子（１）Ｋ加えられた信号により切換える
論理回路、四〜α力は論理回路（７）の出力で発生した
グリッジを除去するグリッジ除去回路である。[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to a glitch removal circuit. [Prior Art] Fig. 3 is a circuit diagram of a conventional glitch removal circuit. In the figure, (1) are input switching terminals, (2), (3) are input terminals, (5), (6), (7) are input signal A
, B are switching terminals (1) and K are switched by a signal applied to the logic circuit, and the terminals 4 to .alpha. are glitch removal circuits that remove glitches generated at the output of the logic circuit (7).
第４図は第３図の回路の各信号のタイミングチャートで
ある。FIG. 4 is a timing chart of each signal in the circuit of FIG. 3.
次に動作について説明する。入力信号として２つのクロ
ックＡ、Ｂがあすこれを切換橋子（１）に加えられた切
換信号により切換えた時に、その出力Ｑにはグリッジ（
ひげバルスー−−−−クロック周期よりも短いパルス）
が出る。このグリッジをなくす為に、切換信号が入った
時に出力されているクロックによシ切換信号を遅らせる
。これによシ、グリッジが出るタイミング時に出力をマ
スクしてグリッジを出力しないようにする。この最初の
マスクタイミングはＤタイプフリップフロップ（以下Ｄ
−ＦＦ’と呼ぶ）口、（２）で作っており０点の波形が
切換った後にＤ −Ｆ Ｆ ０４１によシマスフを解除
している。Next, the operation will be explained. When the two clocks A and B are switched as input signals by the switching signal applied to the switching bridge (1), a glitch (
Whisker pulse---pulse shorter than clock period)
coming out. In order to eliminate this glitch, the switching signal is delayed by the clock that is being output when the switching signal is input. With this, the output is masked at the timing when a glitch occurs, so that the glitch is not output. This first mask timing is for a D type flip-flop (hereinafter referred to as D
-FF') is created in step (2), and after the waveform at the 0 point is switched, the stripe shift is canceled by D-FF 041.
従来のグリッジ除去回路は以とのように構成されていた
ので、回路規模が大きくなり、高集積の半導体集積回路
を設計する場合には多くの労力を必要とするという問題
点があった。Since the conventional glitch removal circuit is constructed as described below, there is a problem that the circuit scale becomes large and a lot of labor is required when designing a highly integrated semiconductor integrated circuit.
この発明は上記のような問題点を解決する為になされた
もので、非常に小さな回路規模で構成されるグリッジ除
去回路を得る事を目的とする。The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a glitch removal circuit configured with a very small circuit scale.
この発明に係るグリッジ除去回路は、Ｄ−ＦＦ１個とコ
ンデｙ ｆ Ｃ及び抵抗Ｒのみで構成するとともに、出
力をマスクするのではなく時定数にょシ巾の短いパルス
は出力させないようにしたものである。The glitch removal circuit according to the present invention is composed of only one D-FF, a capacitor fC, and a resistor R, and instead of masking the output, a short pulse with a time constant width is not output. be.
この発明におけるグリッジ除去回路は、出力をマスクし
ないで、入力のパルスの巾に応じてコンデンサＣおよび
抵抗Ｒによる時定数で充放電する事により、ある−足の
パルス巾より小さくても大きくても出力に出さないよう
にする。The glitch removal circuit of the present invention does not mask the output, but charges and discharges with the time constant of the capacitor C and the resistor R according to the width of the input pulse. Prevent it from being output.
以下、この発明の一実施例を図について説明する。第１
図において、（１）〜（７）は入力Ａ、Ｂを切換信号に
よって切換える論理回路で、前記従来のものと同一であ
る。（８）はグリッジのある入力ＣがＴに入力されそれ
に応じて変化するＱ、向をコンデンサ０と抵抗Ｒによる
時定数でなまらせて互に入力するＤ−ＦＦ、Ｑυはその
出力端子である。An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (1) to (7) are logic circuits that switch inputs A and B using a switching signal, and are the same as the conventional circuits described above. (8) is a D-FF in which glitchy input C is input to T and Q changes accordingly, and the direction is blunted by the time constant of capacitor 0 and resistor R and input to each other, and Qυ is its output terminal. .
第２図は第１図の回路の各信号のタイミングチャートで
ある。FIG. 2 is a timing chart of each signal in the circuit of FIG. 1.
次に動作について説明する。０点にクロックが入って来
た場合、０点の立ｈｂエツジによりＤの信号がＤ −Ｆ
Ｆ ＜８）の端子Ｑに出力されＱは１Ｈ“となる。こ
の時０点はＤ−ＦＦＯＲ側が高電位に充電されている為
、０点がゝＨ“に上がる。この後コンデンサＣ１抵抗Ｒ
の時定数により０点の電位は放電され、只の入力の閾値
まで下がるとＤ−ＦＦ（８）はリセットされる。リセッ
トされればＱはゝ′Ｌ″ζは知“に変化する為、Ｒ側が
高い電位に充電されていたコンデンサＣは０点がゝゝＬ
“に押し下げられＣ，Ｈの時定数により徐々に高い電位
に上ってゆく。この繰返しである。Next, the operation will be explained. When the clock enters the 0 point, the D signal changes to D - F due to the rising hb edge of the 0 point.
F < 8), and Q becomes 1H. At this time, the 0 point rises to 1H because the D-FFOR side is charged to a high potential. After this capacitor C1 resistance R
The potential at the 0 point is discharged according to the time constant, and when it drops to the threshold value of the single input, the D-FF (8) is reset. When reset, Q changes to ``L'', so the 0 point of capacitor C, whose R side was charged to a high potential, becomes ``L''.
The potential is pushed down by ", and gradually rises to a higher potential due to the time constants of C and H. This process is repeated.
入力に１′Ｌ“で間隔の短いパルスが入力された場合、
０点はリセットが解除される。Ｒの閾値に違しない為Ｑ
、Ｑの変化はなく、出力には出ない。When a pulse with a short interval of 1'L" is input to the input,
If the score is 0, the reset is canceled. Since it does not violate the threshold of R, Q
, there is no change in Q, and there is no output.
また、入力にＶ″Ｈ＃で間隔の短いパルスが入力された
場合、Ｑが“Ｌ＃になるタイミングはコンデンサＣ抵抗
Ｒの時定数で決っている為、出力Ｑは一定の時間後に１
１Ｌ″となる。In addition, when a short interval pulse is input to the input at V''H#, the timing at which Q becomes ``L#'' is determined by the time constant of capacitor C and resistor R, so the output Q becomes 1 after a certain period of time.
It becomes 1L''.
なお、Ｃ，Ｈの選び方は互の閾値がＶｏ／２の揚足する
。Note that C and H are selected so that their respective threshold values are Vo/2.
なお、１記実施例では抵抗Ｒを固定とした場合を示した
が可変抵抗であってもよく、この場合出力Ｑのデユーテ
ィ調整としても動作する０〔発明の効果〕
以りのようにこの発明によれば、マスクする為のゲート
を用いず、Ｏ，Ｈによる時定数でグリッジを除去するよ
うにしたので、非常に小さな回路規模でグリッジを除去
出来る効果がある０In addition, in the first embodiment, the case where the resistor R is fixed is shown, but it may be a variable resistor, and in this case, it also operates as a duty adjustment of the output Q. According to 0.0, glitches are removed using a time constant of O and H without using a gate for masking, which is effective in removing glitches with a very small circuit scale.
第１図はこの発明の一実施例によるグリッジ除去回路の
回路図、第２図は第１図の回路の各信号のタイミングチ
ャート、第３図は従来のグリッジ除去回路の回路図、第
４図は第３図の回路の各信号のタイミングチャートであ
る０
（１）は切換端子、（２） 、 （３）は入力端子、（
４） 、 （５） 、 （６） 。
（７）は入力を切換える論理回路、（８） 、 （９）
、α１はグリッジ除去回路で、（８）はＤ−ＦＦ 、
（９）は抵抗Ｒ１αＱはコンデンサ０、αυは出力端子
を示す０なお、図中、同一符号は同一、又は相当部分を
示す。FIG. 1 is a circuit diagram of a glitch removal circuit according to an embodiment of the present invention, FIG. 2 is a timing chart of each signal in the circuit of FIG. 1, FIG. 3 is a circuit diagram of a conventional glitch removal circuit, and FIG. 4 is a timing chart of each signal of the circuit in Figure 3. (1) is the switching terminal, (2) and (3) are the input terminals, (
4), (5), (6). (7) is a logic circuit that switches inputs, (8), (9)
, α1 is a glitch removal circuit, (8) is D-FF,
(9) is a resistor R1, αQ is a capacitor 0, and αυ is an output terminal 0. In the figure, the same reference numerals indicate the same or corresponding parts.
Claims (1)
が閾値よりも高い電位に接続されたＤ−タイプフリップ
フロップにおいて、Ｑ出力にＣが接続されＣの反対側に
＠Ｑ＠からＲを通して接続されＲとＣの接続点が＠Ｒ＠
に接続されＱが出力として構成されたことを特徴とする
グリツジ除去回路。In a D-type flip-flop, in which a logic signal with glitches is input to the T input and the D input is connected to a potential higher than the threshold, C is connected to the Q output, and the other side of C is connected from @Q to R through R. The connection point between R and C is @R@
What is claimed is: 1. A glitch removal circuit characterized in that the circuit is connected to Q and Q is configured as an output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2026597A JPH03231508A (en) | 1990-02-06 | 1990-02-06 | Glitch elimination circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2026597A JPH03231508A (en) | 1990-02-06 | 1990-02-06 | Glitch elimination circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03231508A true JPH03231508A (en) | 1991-10-15 |
Family
ID=12197940
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2026597A Pending JPH03231508A (en) | 1990-02-06 | 1990-02-06 | Glitch elimination circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03231508A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100503053B1 (en) * | 1997-11-14 | 2005-09-30 | 삼성전자주식회사 | Clock adjustment circuit |
| JP2010068270A (en) * | 2008-09-11 | 2010-03-25 | Nec Commun Syst Ltd | Noise elimination circuit and method |
-
1990
- 1990-02-06 JP JP2026597A patent/JPH03231508A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100503053B1 (en) * | 1997-11-14 | 2005-09-30 | 삼성전자주식회사 | Clock adjustment circuit |
| JP2010068270A (en) * | 2008-09-11 | 2010-03-25 | Nec Commun Syst Ltd | Noise elimination circuit and method |
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