JPH03231437A - Forming method for protruding electrode - Google Patents
Forming method for protruding electrodeInfo
- Publication number
- JPH03231437A JPH03231437A JP2748690A JP2748690A JPH03231437A JP H03231437 A JPH03231437 A JP H03231437A JP 2748690 A JP2748690 A JP 2748690A JP 2748690 A JP2748690 A JP 2748690A JP H03231437 A JPH03231437 A JP H03231437A
- Authority
- JP
- Japan
- Prior art keywords
- wirings
- electrode
- protrusion
- substrate
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 39
- 239000011347 resin Substances 0.000 claims abstract description 8
- 229920005989 resin Polymers 0.000 claims abstract description 8
- 239000004020 conductor Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims description 28
- 239000011521 glass Substances 0.000 abstract description 9
- 229910052737 gold Inorganic materials 0.000 abstract description 7
- 239000000463 material Substances 0.000 abstract description 6
- 229910052802 copper Inorganic materials 0.000 abstract description 5
- 229920000642 polymer Polymers 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 229910052709 silver Inorganic materials 0.000 abstract description 4
- 229910052763 palladium Inorganic materials 0.000 abstract description 3
- 239000000919 ceramic Substances 0.000 abstract description 2
- 229910052804 chromium Inorganic materials 0.000 abstract description 2
- 229910052697 platinum Inorganic materials 0.000 abstract 1
- 239000010408 film Substances 0.000 description 9
- 239000010931 gold Substances 0.000 description 8
- 239000010409 thin film Substances 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 238000007650 screen-printing Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 238000013007 heat curing Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、突起電極形成方法に係り、詳しくは、半導体
の製造等に用いられる突起電極形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention relates to a method for forming a protruding electrode, and more particularly, to a method for forming a protruding electrode used in semiconductor manufacturing and the like.
（従来の技術）
半導体の製造等に用いられる従来の突起電極形成方法と
しては、例えば、スクリーンマスクを用いてペーストを
スキージで転写するスクリーン印刷法、フォトリソでレ
ジスト上に突きあて後、メツキで金ハンプを形成する薄
膜法、予めガラス板上にメツキで金ハンプを形成して基
板に熱で転写する転写ハンプ法および放電によりＡｕあ
るいはＣｕからなるワイヤの先端にポールを形成し基板
に熱圧着して、ワイヤを途中でカット後成形するボール
形成法等が知られている。(Prior Art) Conventional methods for forming protruding electrodes used in the manufacture of semiconductors include, for example, the screen printing method in which paste is transferred using a squeegee using a screen mask, and the method in which the paste is transferred onto the resist using photolithography and then gold is plated. A thin film method for forming humps, a transfer hump method in which a gold hump is formed in advance by plating on a glass plate and transferred to the substrate using heat, and a pole is formed at the tip of a wire made of Au or Cu by electric discharge and bonded to the substrate by thermocompression. A ball forming method is known in which a wire is cut in the middle and then formed.
（発明が解決しようとする課題）
しかしながら、従来の突起電極形成方法にあっては、下
達の理由により、異形の基板に適用できなかったり、コ
ストが増大したりするといった問題点があった。(Problems to be Solved by the Invention) However, the conventional method for forming protruding electrodes has problems such as being unable to be applied to irregularly shaped substrates and increasing costs due to poor quality.
すなわち、スクリーン印刷法および薄膜法は、パターニ
ングの手法であり、前者は、パターン精度（ｉｌ常±５
μｍ）や形状精度が低く、後者は、プロセスが複雑でコ
ストが高い。また両者ともに異形（凹凸）基板に通用す
ることができない。That is, the screen printing method and the thin film method are patterning methods, and the former has pattern accuracy (il normal ±5
μm) and shape accuracy are low, and the latter requires a complicated process and high cost. Further, neither of them can be applied to irregularly shaped (irregular) substrates.
一方、転写バンプ法およびボール形成法は、異形の基板
に適用することができるが、前者は、薄膜のプロセスを
必要とするためコストが高く、材料が薄膜法で形成する
ことおよび熱圧着することができるものという二つの制
約を受ける。後者は、形状精度のばらつきが大きく、さ
らにワイヤの材料がボールを形成することができるもの
（Ａｕ、 Ｃｕ）という制約を受ける。したがって、両
者ともコストが増大する。On the other hand, the transfer bump method and the ball formation method can be applied to irregularly shaped substrates, but the former requires a thin film process and is therefore expensive, and the material is formed using a thin film method and is bonded by thermocompression. There are two constraints: what can be done. The latter has large variations in shape accuracy and is further constrained by the wire material being able to form a ball (Au, Cu). Therefore, both increase costs.
（発明の目的）
そこで本発明は、突起を樹脂あるいはゴムにより形成し
、基板の配線に当接するとともに突起の先端を覆う電極
部材を形成して突起電極を形成することにより、異形基
板にも適用することができ、コストを低減することがで
きる突起電極形成方法を提供することを目的としている
。(Purpose of the Invention) Therefore, the present invention can be applied to irregularly shaped substrates by forming protrusions from resin or rubber and forming a protruding electrode by forming an electrode member that contacts the wiring of the substrate and covers the tips of the protrusions. It is an object of the present invention to provide a method for forming protruding electrodes that can reduce costs.
（発明の構成）
本発明は、上記目的を達成するため、基板上の配線に接
続された突起電極を基板に形成する突起電極形成方法で
あって、前記基板上の所定位置に絶縁性を有する樹脂あ
るいはゴムからなる突起を形成し、次いで、導電性材料
からなり、突起の先端を覆うとともに配線に当接する電
極部材を形成することを特徴とするものである。(Structure of the Invention) In order to achieve the above-mentioned object, the present invention provides a method for forming a protruding electrode on a substrate, the protruding electrode being connected to a wiring on the substrate, the protruding electrode having an insulating property at a predetermined position on the substrate. The method is characterized in that a protrusion made of resin or rubber is formed, and then an electrode member made of a conductive material that covers the tip of the protrusion and comes into contact with the wiring is formed.
以下、本発明を図面に基づいて具体的に説明する。Hereinafter, the present invention will be specifically explained based on the drawings.
第１〜５図は本発明に係る突起電極形成方法により形成
される突起電極の一実施例およびその成形手順を説明す
るための図である。1 to 5 are diagrams for explaining one embodiment of a protruding electrode formed by the protruding electrode forming method according to the present invention and its forming procedure.
まず、第１〜５図の示す内容およびその構成を説明する
。First, the contents shown in FIGS. 1 to 5 and their configurations will be explained.
第１図は、突起電極が形成される基板を示しており、■
は基板、２は基板１上の配線、３は後述する工程におい
て隣接パターン間のショートの発生を防止するための絶
縁膜である。基板ｌはガラスまたはセラミックまたは樹
脂からなり、配’に’Ａ ２は、厚膜導体の場合、Ａｕ
、 Ａｇ／Ｐｄ、 Ｃｕあるいはｐｔからなり、薄膜導
体の場合、Ａｕ／ＣｒあるいはＡｌらなる。また配線２
の接続端子は千鳥状に配設されている。Figure 1 shows a substrate on which protruding electrodes are formed;
2 is a substrate, 2 is a wiring on the substrate 1, and 3 is an insulating film for preventing occurrence of short circuit between adjacent patterns in a process to be described later. The substrate 1 is made of glass, ceramic, or resin, and the wiring board 1 is made of Au.
, Ag/Pd, Cu or PT, and in the case of a thin film conductor, Au/Cr or Al. Also wiring 2
The connection terminals are arranged in a staggered manner.
第２図は、基板１上に絶縁性部材を塗布する装置を示し
ており、４はノズルであり、５は絶縁性部材である。ノ
ズル４は絶縁性部材５を収納しており、ノズル４の先端
には微細な吐出穴４ａが形成されている。ノズル４には
図外の装置から圧搾空気が供給されるようになっており
、圧搾空気の供給により、吐出穴４ａから絶縁性部材５
が吐出して基板１上に塗布されるようになっている。ま
たこのとき、ノズル４および基板ｌの相対位置を変化さ
せることにより、絶縁性部材５を所定パターン形状に塗
布することができる。絶縁性部材５は厚膜ガラス系ペー
ストまたは厚膜ポリマー系ペーストまたはゴム系ペース
トからなる。厚膜ガラス系ペーストは低融点ガラスにフ
ィラー（Ｓｉｇｈ、Ａ ｌ ２０３）を混入しており、
熱硬化温度が５００〜９００°Ｃである。厚膜ポリマー
系ペーストおよびゴム系ペーストの熱硬化温度が１００
〜３００℃である。FIG. 2 shows an apparatus for applying an insulating member onto a substrate 1, where 4 is a nozzle and 5 is an insulating member. The nozzle 4 houses an insulating member 5, and a fine discharge hole 4a is formed at the tip of the nozzle 4. Compressed air is supplied to the nozzle 4 from a device not shown, and the supply of compressed air causes the insulating member 5 to flow from the discharge hole 4a.
is discharged and applied onto the substrate 1. Further, at this time, by changing the relative positions of the nozzle 4 and the substrate 1, the insulating member 5 can be applied in a predetermined pattern. The insulating member 5 is made of thick glass paste, thick polymer paste, or rubber paste. Thick film glass paste is made by mixing low melting point glass with filler (Sigh, Al 203).
The thermosetting temperature is 500 to 900°C. The heat curing temperature of thick film polymer paste and rubber paste is 100
~300°C.
第３図は、絶縁性部材５が基板１に塗布された状態を示
しており、絶縁性部材５により突起６が構成される。突
起６は、各配線２の端部近傍を跨くように直線上に形成
され、所定の高さを有している。FIG. 3 shows a state in which the insulating member 5 is applied to the substrate 1, and the insulating member 5 forms the protrusion 6. The protrusion 6 is formed on a straight line so as to straddle the vicinity of the end of each wiring 2, and has a predetermined height.
第４図は、突起６および配ｖＡ２上に導電性部材を塗布
する装置を示しており、７はノズルであり、ノズル４と
同様の構造を有し、導電性材料からなる導電性部材８を
収納している。導電性部材８は厚膜ガラス系ペースト（
Ａｕ、 Ａｇ／Ｐｄ、 Ａｇ、、Ｃｕ＝）あるいは厚膜
ポリマー系ペースト（Ａｇ、 Ａｕ・・）からなり、厚
膜ガラス系ペーストの熱硬化温度は５００〜９００°Ｃ
であり、厚膜ポリマー系ペーストの熱硬化温度は１００
〜３００℃である。また、導電性部材８は、突起６の先
端を覆った後に配線２に当接するように、塗布される。FIG. 4 shows an apparatus for applying a conductive member onto the protrusion 6 and the distribution plate A2, where 7 is a nozzle, which has the same structure as the nozzle 4, and which coats the conductive member 8 made of a conductive material. It is stored. The conductive member 8 is made of thick film glass paste (
It consists of Au, Ag/Pd, Ag, Cu=) or thick film polymer paste (Ag, Au...), and the thermosetting temperature of the thick film glass paste is 500 to 900°C.
, and the heat curing temperature of the thick film polymer paste is 100
~300°C. Further, the conductive member 8 is applied so as to cover the tip of the protrusion 6 and then come into contact with the wiring 2 .
第５図は、導電性部材８が塗布された状態を示しており
、導電性部材８により、配線２に接続された電極部材９
が構成され、突起６および導電性部材８により、突起電
極１０が形成される。FIG. 5 shows a state where the conductive member 8 is applied, and the electrode member 9 is connected to the wiring 2 by the conductive member 8.
The protrusion 6 and the conductive member 8 form a protrusion electrode 10.
なお、上述のノズル４．７により突起６、電極部材９を
形成する方法は、いわゆる厚膜直接描画法であり、ライ
ト法と呼ばれることもある。Note that the method of forming the protrusion 6 and the electrode member 9 using the nozzle 4.7 described above is a so-called thick film direct writing method, which is sometimes called a write method.
次に、突起電極１０の形成手順を説明する。Next, a procedure for forming the protruding electrode 10 will be explained.
まず、第２．３図に示すように、ノズル４に圧搾空気を
送り絶縁性部材５を基板ｌ上の所定位置に吐出させた後
、硬化させて、突起６を形成する。First, as shown in FIG. 2.3, compressed air is sent to the nozzle 4 to discharge the insulating member 5 to a predetermined position on the substrate l, and then it is hardened to form the protrusion 6.
次いで、第４．５図に示すように、ノズル７に圧搾空気
を送り導電性部材８を吐出させた後、硬化させて、導電
性部材８により突起６の先端を覆うとともに配線２に当
接する電極部材９を形成する。Next, as shown in FIG. 4.5, compressed air is sent to the nozzle 7 to discharge the conductive member 8, which is then hardened to cover the tip of the protrusion 6 with the conductive member 8 and come into contact with the wiring 2. Electrode member 9 is formed.
このとき、突起６および電極部材９により、突起電極１
０が形成される。 ′
上述のような形成方法によれば、基板１の形状がどのよ
うなものであっても適用することができ、薄膜法のプロ
セス（フォトリソ二メッキ）を用いていないので、従来
の薄膜法に比較すると大幅にコストを低減することがで
きる。At this time, the protrusion 6 and the electrode member 9 cause the protrusion electrode 1
0 is formed. ' According to the above-mentioned formation method, it can be applied to any shape of the substrate 1, and since it does not use a thin film process (photolithographic plating), it can be applied to the conventional thin film method. By comparison, costs can be significantly reduced.
また、絶縁性部材５として安価な絶縁性の材料を用いる
ことができるので、コストを低減することができる。Furthermore, since an inexpensive insulating material can be used as the insulating member 5, costs can be reduced.
さらに、ペースト状にすれば、どんな材料のものでも絶
縁性部材５および導電性部材８として、用いることがで
きるので、メツキを用いた方法やボール形成法に比較す
ると、使用材料の対象範囲を非常に広くすることができ
る。Furthermore, if it is made into a paste, any material can be used as the insulating member 5 and the conductive member 8, so compared to methods using plating or ball forming methods, the range of materials used can be greatly reduced. can be widened to
またさらに、従来の方法により形成されたハンプの場合
、半導体チップを基板上にボンディングするとき、ＵＶ
や熱により硬化する接着剤を用いたり、両者を加圧保持
したりする方法を用いると、ハンプの高さのばらつきが
問題になるが、本実施例の場合、突起６が樹脂あるいは
ゴムからなり、弾力性を有しているので、ハンプ高さに
ばらつきがあっても、接続の歩留りや信頼性を高めるこ
とができる。Furthermore, in the case of humps formed by conventional methods, when bonding a semiconductor chip onto a substrate, UV
If an adhesive that hardens with heat or heat is used, or if both are held under pressure, variations in the height of the hump will be a problem, but in the case of this embodiment, the protrusions 6 are made of resin or rubber. Since it has elasticity, it is possible to improve the yield and reliability of connections even if there are variations in hump height.
さらにまた、突起６は、半導体チップと基板ｌとの膨張
係数の差による熱歪を吸収することができるので、上述
同様に接続の歩留りや信頼性を高めることができる。Furthermore, since the protrusions 6 can absorb thermal strain due to the difference in expansion coefficients between the semiconductor chip and the substrate 1, the yield and reliability of the connection can be improved as described above.
また、配線２の接続端子が千鳥配設になっており、また
絶縁膜３により導電性部材８が多少だれても隣接パター
ン間のショートを防止することができ、さらにライン長
が短いので、１００μｍピ。In addition, the connection terminals of the wiring 2 are arranged in a staggered manner, and the insulating film 3 prevents short-circuits between adjacent patterns even if the conductive member 8 sag to some extent.Furthermore, the line length is short, so the line length is 100 μm. Pi.
チ以下のファインピッチを実現することができる。It is possible to achieve a fine pitch of less than 1.
さミに、半田付はタイプのフリップチップ用の突起電極
の形成に適用した場合、高さをかせくことができるので
、非常に有用である。Additionally, soldering is very useful when applied to the formation of protruding electrodes for flip-chip type flip-chip devices, since the height can be increased.
なお、本実施例では、直接描画法により突起６等を形成
したが、これに限られるものではなく、例えばスクリー
ン印刷等を用いて突起６をゴムにより形成するようにし
てもよい。In this embodiment, the protrusions 6 and the like are formed by a direct drawing method, but the present invention is not limited to this, and the protrusions 6 may be formed of rubber using screen printing or the like, for example.
（効果）
本発明によれば、突起を樹脂あるいはゴムにより形成し
、基板の配線に当接するとともに突起の先端を覆う電極
部材を形成して突起電極を形成しているので、材料を選
ばずに容易に突起電極を形成することができ、異形基板
にも適用することができ、またコストを低減することが
できる。(Effects) According to the present invention, the protrusion is made of resin or rubber, and the protrusion electrode is formed by forming an electrode member that contacts the wiring on the board and covers the tip of the protrusion, so there is no need to select a material. Protruding electrodes can be easily formed, it can be applied to irregularly shaped substrates, and costs can be reduced.
第１図は本発明に係る突起電極形成方法により突起電極
が形成される基板の一実施例を示す斜視図、第２図は本
発明に係る突起電極形成方法を適用した形成装置の一実
施例を示す要部断面図、第３図は本発明に係る突起電極
形成方法により形成された突起の一実施例を示す斜視図
、第４図は第２図に示す形成装置の他の要部断面図、第
５図二よ本発明に係る突起電極形成方法により形成され
た突起電極の一実施例を示す斜視図である。
１・・・・・・基板、
２〜・−・−・配線、
６・・−・−・突起、
９・・−・電極部材、
１０・−・・・・突起電極。FIG. 1 is a perspective view showing an embodiment of a substrate on which a protruding electrode is formed by the protruding electrode forming method according to the present invention, and FIG. 2 is an example of a forming apparatus to which the protruding electrode forming method according to the present invention is applied. FIG. 3 is a perspective view showing an example of a protrusion formed by the protrusion electrode forming method according to the present invention, and FIG. 4 is a cross-sectional view of another essential part of the forming apparatus shown in FIG. 2. FIG. 5 is a perspective view showing an embodiment of a protruding electrode formed by the protruding electrode forming method according to the present invention. DESCRIPTION OF SYMBOLS 1... Substrate, 2... Wiring, 6... Protrusion, 9... Electrode member, 10... Protrusion electrode.
Claims (1)
起電極形成方法であって、前記基板上の所定位置に絶縁
性を有する樹脂あるいはゴムからなる突起を形成し、次
いで、導電性材料からなり、突起の先端を覆うとともに
配線に当接する電極部材を形成することを特徴とする突
起電極形成方法。A protruding electrode forming method in which a protruding electrode connected to wiring on a substrate is formed on a substrate, the protrusion being made of an insulating resin or rubber is formed at a predetermined position on the substrate, and then a protrusion made of an electrically conductive material is formed. A method for forming a protruding electrode, the method comprising: forming an electrode member that covers the tip of the protrusion and comes into contact with the wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2748690A JPH03231437A (en) | 1990-02-06 | 1990-02-06 | Forming method for protruding electrode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2748690A JPH03231437A (en) | 1990-02-06 | 1990-02-06 | Forming method for protruding electrode |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03231437A true JPH03231437A (en) | 1991-10-15 |
Family
ID=12222460
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2748690A Pending JPH03231437A (en) | 1990-02-06 | 1990-02-06 | Forming method for protruding electrode |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03231437A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5336547A (en) * | 1991-11-18 | 1994-08-09 | Matsushita Electric Industrial Co. Ltd. | Electronic components mounting/connecting package and its fabrication method |
| WO2001075969A1 (en) * | 2000-03-31 | 2001-10-11 | Infineon Technologies Ag | Electronic component with flexible contact points and method for the production thereof |
| KR20030043748A (en) * | 2001-11-28 | 2003-06-02 | 가부시키가이샤 신가와 | Method of manufacturing a semiconductor device |
| JP2006098637A (en) * | 2004-09-29 | 2006-04-13 | Seiko Epson Corp | Semiconductor device, mounting structure, electro-optical device, method of manufacturing eectro-optical device, and electronic apparatus |
| JP2007042770A (en) * | 2005-08-02 | 2007-02-15 | Seiko Epson Corp | Semiconductor device and its manufacturing process |
| US7482541B2 (en) * | 2004-03-17 | 2009-01-27 | Seiko Epson Corporation | Panel for electro-optical apparatus, method of manufacture thereof, electro-optical apparatus and electronic apparatus |
-
1990
- 1990-02-06 JP JP2748690A patent/JPH03231437A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5336547A (en) * | 1991-11-18 | 1994-08-09 | Matsushita Electric Industrial Co. Ltd. | Electronic components mounting/connecting package and its fabrication method |
| WO2001075969A1 (en) * | 2000-03-31 | 2001-10-11 | Infineon Technologies Ag | Electronic component with flexible contact points and method for the production thereof |
| US6897568B2 (en) | 2000-03-31 | 2005-05-24 | Infineon Technologies Ag | Electronic component with flexible contacting pads and method for producing the electronic component |
| US7312533B2 (en) | 2000-03-31 | 2007-12-25 | Infineon Technologies Ag | Electronic component with flexible contacting pads and method for producing the electronic component |
| KR20030043748A (en) * | 2001-11-28 | 2003-06-02 | 가부시키가이샤 신가와 | Method of manufacturing a semiconductor device |
| US7482541B2 (en) * | 2004-03-17 | 2009-01-27 | Seiko Epson Corporation | Panel for electro-optical apparatus, method of manufacture thereof, electro-optical apparatus and electronic apparatus |
| JP2006098637A (en) * | 2004-09-29 | 2006-04-13 | Seiko Epson Corp | Semiconductor device, mounting structure, electro-optical device, method of manufacturing eectro-optical device, and electronic apparatus |
| JP4539268B2 (en) * | 2004-09-29 | 2010-09-08 | セイコーエプソン株式会社 | Mounting structure |
| JP2007042770A (en) * | 2005-08-02 | 2007-02-15 | Seiko Epson Corp | Semiconductor device and its manufacturing process |
| JP4645832B2 (en) * | 2005-08-02 | 2011-03-09 | セイコーエプソン株式会社 | Semiconductor device and manufacturing method thereof |
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