JPH03226042A - Transmission frequency monitor system - Google Patents
Transmission frequency monitor systemInfo
- Publication number
- JPH03226042A JPH03226042A JP2020316A JP2031690A JPH03226042A JP H03226042 A JPH03226042 A JP H03226042A JP 2020316 A JP2020316 A JP 2020316A JP 2031690 A JP2031690 A JP 2031690A JP H03226042 A JPH03226042 A JP H03226042A
- Authority
- JP
- Japan
- Prior art keywords
- clock
- phase difference
- phase
- pulse signal
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 title claims abstract description 43
- 238000012544 monitoring process Methods 0.000 claims abstract description 16
- 238000000605 extraction Methods 0.000 claims abstract description 13
- 238000006243 chemical reaction Methods 0.000 claims abstract description 7
- 230000010355 oscillation Effects 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 13
- 230000001360 synchronised effect Effects 0.000 claims description 10
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 6
- 230000002159 abnormal effect Effects 0.000 claims description 3
- 239000000284 extract Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 244000205754 Colocasia esculenta Species 0.000 description 1
- 235000006481 Colocasia esculenta Nutrition 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
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- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、伝送路から抽出される伝送りロックの正常性
を識別監視する方式に関し、特に、伝送りロック信号を
情報信号に含めて伝送するＡＭＩ、ＣＭｌ等の復号バイ
ポーラ信号を使用した伝送路上のクロックの有無、及び
クロック周波数の正常性を高精度に識別監視する伝送周
波数監視方式に関する。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for identifying and monitoring the normality of a transmission lock extracted from a transmission path, and particularly to an AMI that transmits a transmission lock signal by including it in an information signal. The present invention relates to a transmission frequency monitoring method for highly accurately identifying and monitoring the presence or absence of a clock on a transmission path and the normality of a clock frequency using a decoded bipolar signal such as CMl or the like.
従来の技術
従来、ディジタル情報を伝送路を介して伝送する方式と
して情報信号、同期信号、クロック信号の各信号を個別
線により伝送する方式と、Ａ旧、ＣＭＩ信号等の様に前
記の各個別信号をある符号変換則に基ずき情報信号、ク
ロック信号、同期信号を符号変換することにより一対の
伝送路で伝送する方式が知られている。Conventional technology Conventionally, as a method for transmitting digital information via a transmission path, there are two methods: one method is to transmit each signal, such as an information signal, a synchronization signal, and a clock signal, through individual lines; A method is known in which signals are transmitted over a pair of transmission paths by converting the codes of information signals, clock signals, and synchronization signals based on a certain code conversion rule.
ここで、伝送りロックの正常性（クロックの有無、周波
数の適正）を識別する場合には、従来から実用化されて
いる簡易な方法としてモノマルチ回路によりクロックの
エツジの間隔をコンデンサ、抵抗器を使用した時定数回
路で可変調整して特定の周波数の監視に使用する方法が
一般的であっな。Here, when identifying the normality of the transmission lock (the presence or absence of a clock, the appropriateness of the frequency), a simple method that has been in practical use is to use a monomulticircuit to adjust the interval between clock edges using capacitors and resistors. A common method is to use a time constant circuit to make variable adjustments and monitor a specific frequency.
発明が解決しようとする課題
上述した従来のモノマルチ回路を使用したクロック周波
数の監視方式でクロックの有無を検出する場合、前者に
於いてはクロック信号を個別に伝送している為に伝送路
が切断された場合には完全に受信クロックが無くなる為
に識別することが可能であるが、後者に於いてはＡＮＴ
またはＣ旧符号の復調回路に於いて受信クロック再生回
路の使用素子としてセラミックフィルタ及び能動素子等
で回路を構成している為に、伝送路が切断された場合実
際に信号が受信されないにもがかわらず受信回路内部で
発振し、復調回路から周波数が不定のクロックが出力さ
れる場合がある為に、通常のモノマルチ回路等のクロッ
ク検出回路では誤動作する。またクロックの周波数監視
をする場合には、前記の様に時定数回路に抵抗、コンデ
ンサを使用している為に部品の精度等に依存し、監視精
度にばらつきが生じるという欠点があった。Problems to be Solved by the Invention When detecting the presence or absence of a clock using the conventional clock frequency monitoring method using a mono multi-circuit as described above, in the former case, the clock signal is transmitted individually, so the transmission path is In the case of disconnection, it is possible to identify it because the reception clock is completely lost, but in the latter case, the ANT
Or, in the demodulation circuit of the old C code, since the circuit is composed of ceramic filters and active elements as elements used in the reception clock recovery circuit, if the transmission line is cut off, the signal may not actually be received. However, since the receiving circuit oscillates internally and the demodulating circuit may output a clock with an undefined frequency, a clock detection circuit such as a normal monomulti circuit will malfunction. Furthermore, when monitoring the frequency of the clock, since a resistor and a capacitor are used in the time constant circuit as described above, there is a drawback that the monitoring accuracy depends on the accuracy of the components and the like, resulting in variations in monitoring accuracy.
本発明は従来の上記実情に鑑みてなされたちのであり、
従って本発明の目的は、従来の技術に内在する上記欠点
を解消し、伝送路等から抽出される伝送りロック周波数
の正常性を高精度に識別することを可能とした新規な伝
送周波数監視方式を提供することにある。The present invention has been made in view of the above-mentioned conventional circumstances,
Therefore, an object of the present invention is to provide a new transmission frequency monitoring method that eliminates the above-mentioned drawbacks inherent in the conventional technology and that makes it possible to identify with high precision the normality of the transmission lock frequency extracted from the transmission path, etc. Our goal is to provide the following.
課題を解決するための手段
上記目的を達成する為に、本発明に係る伝送周波数の高
精度監視方式は、伝送路から受信される信号を復調しク
ロック成分を抽出する伝送路クロック抽出部と、該クロ
ック抽出部からのクロックに正常時には従属同期し異常
時には自走する位相同期発振部と、前記クロック抽出部
及び該位相同期発信部から出力される各々のクロックを
使用して一定間隔のパルス信号を作成するパルス信号発
生部と、該パルス信号発生部から出力される各々のパル
ス信号の位相差を検出しその位相差をもとに位相差を直
線的な出力特性をもつ電圧に変換する位相差電圧変換部
とを具備して構成され、入力されるタロツク及び基準と
なるクロックとの位相差を常時識別監視することを特徴
としている。Means for Solving the Problems In order to achieve the above object, the high-precision transmission frequency monitoring method according to the present invention includes a transmission line clock extraction unit that demodulates a signal received from a transmission line and extracts a clock component; A phase-synchronized oscillation section that slave-synchronizes with the clock from the clock extraction section when normal and runs free when abnormal; and a pulse signal at constant intervals using each clock output from the clock extraction section and the phase-synchronized oscillation section. A pulse signal generation section that generates a pulse signal, and a section that detects the phase difference between each pulse signal output from the pulse signal generation section and converts the phase difference into a voltage having linear output characteristics based on the phase difference. The clock is configured to include a phase difference voltage converter, and is characterized in that it constantly identifies and monitors the phase difference between the input taro clock and the reference clock.
実施例
次に本発明をその好ましい一実施例について図面を参照
して具体的に説明する。Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.
第１図は、本発明に係る伝送路から入力されるクロック
周波数を高精度に監視する為に必要な構成要素を含んだ
本発明の一実施例を示すブロック構成図である。FIG. 1 is a block diagram showing an embodiment of the present invention including components necessary for highly accurate monitoring of a clock frequency input from a transmission line according to the present invention.
まず本図を使用して本方式の動作原理を説明する。第１
図を参照するに、伝送路から受信されるバイポーラ信号
は信号入力端子１から伝送りロック抽出部２に入力され
る。伝送りロック抽出部２はバイポーラ信号を復調し、
クロック成分を分離抽出する。ここで抽出されたクロッ
クは位相同期発振部３及びパルス信号発生部４に入力さ
れる。First, the operating principle of this system will be explained using this figure. 1st
Referring to the figure, a bipolar signal received from a transmission path is input from a signal input terminal 1 to a transmission lock extraction section 2. The transmission lock extraction unit 2 demodulates the bipolar signal,
Separate and extract clock components. The clock extracted here is input to the phase synchronized oscillation section 3 and the pulse signal generation section 4.
位相同期発振部３では、伝送路から受信されたクロック
が正常な場合には、該クロック周波数に従属同期した動
作を行う、また、パルス信号発生部４では伝送路クロッ
ク抽出部２から出力される受信クロックからある一定の
フレームパルス（本実施例では８ＫＨｚ）を作成し位相
差電圧変換部６に出力する。一方位相同期発振部３から
出力される受信クロックに従属同期したクロックは、パ
ルス信号発生部５に入力され、パルス信号発生部４と同
様にある一定のフレームパルス（本実施例では８ＫＨｚ
）を作成し、位相差電圧変換部６に出力する。When the clock received from the transmission line is normal, the phase synchronized oscillator 3 performs an operation in slave synchronization with the clock frequency, and the pulse signal generator 4 outputs the clock from the transmission line clock extractor 2. A certain frame pulse (8 KHz in this embodiment) is created from the received clock and output to the phase difference voltage converter 6. On the other hand, a clock slave-synchronized with the received clock output from the phase synchronized oscillator 3 is input to the pulse signal generator 5, and similarly to the pulse signal generator 4, a certain frame pulse (in this example, 8 KHz) is input to the pulse signal generator 5.
) is generated and output to the phase difference voltage converter 6.
ここで１位相差電圧変換部６の動作原理について説明す
る０位相差電圧変換部６は、位相比較を行う際に、基準
位相信号にパルス信号発生部５から出力されるフレーム
パルス信号を使用し、パルス信号発生部４から出力され
るフレームパルス信号との位相差を検出し、その位相差
に対応した電圧を出力する。The operating principle of the 1-phase difference voltage converter 6 will now be explained. The 0-phase difference voltage converter 6 uses the frame pulse signal output from the pulse signal generator 5 as the reference phase signal when performing phase comparison. , detects the phase difference with the frame pulse signal output from the pulse signal generator 4, and outputs a voltage corresponding to the phase difference.
上記フレームパルス信号の位相関係とその位相差に対す
る電圧変化動作を説明する為に、パルス信号発生部５と
パルス信号発生部４の出力位相差を第２図に、また位相
差とその位相差に対応する差分電圧との関係を示す特性
グラフを第３図に示す。In order to explain the phase relationship of the frame pulse signals and the voltage change operation with respect to the phase difference, the output phase difference between the pulse signal generator 5 and the pulse signal generator 4 is shown in FIG. 2, and the phase difference and the phase difference are shown in FIG. A characteristic graph showing the relationship with the corresponding differential voltage is shown in FIG.
第２図において、パルス信号発生部４の出力として実線
で示したパルスは基準となるパルスよりΔφだけ位相が
遅れていることを示し、また破線は逆にΔφだけ位相が
進んでいることを示している。In FIG. 2, the pulse shown by the solid line as the output of the pulse signal generator 4 shows that the phase is delayed by Δφ from the reference pulse, and conversely, the broken line shows that the phase is advanced by Δφ. ing.
また第３図は上記位相差が同相のときに出力電圧がｖｃ
で、位相差が一２πのときに出力電圧がＶＬ、位相差が
＋２ｆのときに出力電圧がＶ）！で、位相差とそれに対
する差分電圧は直線的に変化する特性を示している。従
って前記フレームパルスに位相差が進んでいる場合には
差分電圧としては出力電圧ＶＣより高い電圧Ｖ（＋Δφ
）を出力し、逆に遅れている場合には出力電圧■。より
低い電圧Ｖ（−Δφ）を出力する。In addition, FIG. 3 shows that when the above phase differences are in phase, the output voltage is vc
So, when the phase difference is 12π, the output voltage is VL, and when the phase difference is +2f, the output voltage is V)! The phase difference and the differential voltage corresponding to the phase difference exhibit characteristics that change linearly. Therefore, if the phase difference is advanced in the frame pulse, the differential voltage will be a voltage V (+Δφ
), and conversely, if there is a delay, the output voltage ■. Outputs a lower voltage V (-Δφ).
以上に示した動作特性をもつ位相差電圧変換部６の出力
は位相同期発振部３に帰還され、該出力信号が常時伝送
路クロック抽出部２から出力されるクロックに周波数が
一致する様に制御信号として使用される。従って、位相
同期発振部３と伝送路クロック抽出部２の周波数が正常
時には常に位相差電圧変換部６の出力がｖｃに保たれる
。The output of the phase difference voltage converter 6 having the operating characteristics described above is fed back to the phase synchronized oscillator 3, and the output signal is controlled so that the frequency always matches the clock output from the transmission line clock extractor 2. used as a signal. Therefore, when the frequencies of the phase synchronized oscillation section 3 and the transmission line clock extraction section 2 are normal, the output of the phase difference voltage conversion section 6 is always maintained at vc.
次に信号入力端子１に接続される伝送路が切断された場
合には伝送路クロック抽出部２からのクロック周波数が
不定となり、位相差電圧変換部６に入力される前記フレ
ームパルスの位相差が同相でなくなり、位相差電圧変換
部６の出力は入力される位相差の差分として出力電圧Ｖ
Ｃから電圧がある一定以上変化すると位相同期発振部３
に入力されている前記制御信号から位相同期発振部３は
、従属動作から外部から入力されるクロックの影響を受
けないような自走動作となる０位相同期発振部３が自走
で動作する様になると、この自走周波数が基準フレーム
パルス位相となり、該基準位相フレームパルスとパルス
信号発生部４から出力されるフレームパルスとの位相を
位相差電圧変換部６が比較し、その結果を差分電圧とし
て出力する様になる。従って、伝送路が切断された場合
には当然伝送路クロック抽出部２からの出力周波数は不
定となるために、位相差電圧変換部６からの該出力信号
を監視することにより伝送路から受信されるクロック周
波数の正常性を識別することができる。Next, when the transmission line connected to the signal input terminal 1 is disconnected, the clock frequency from the transmission line clock extraction section 2 becomes unstable, and the phase difference of the frame pulses input to the phase difference voltage conversion section 6 changes. They are no longer in phase, and the output of the phase difference voltage converter 6 is the output voltage V as the difference between the input phase differences.
When the voltage changes from C to more than a certain level, the phase synchronized oscillator 3
The phase synchronized oscillator 3 operates from the control signal input to the 0-phase synchronized oscillator 3, which becomes a free-running operation that is not affected by the clock input from the outside from the dependent operation. Then, this free-running frequency becomes the reference frame pulse phase, and the phase difference voltage converter 6 compares the phase of the reference phase frame pulse and the frame pulse output from the pulse signal generator 4, and converts the result into a difference voltage. It will be output as . Therefore, if the transmission line is disconnected, the output frequency from the transmission line clock extraction section 2 will naturally become unstable, so by monitoring the output signal from the phase difference voltage conversion section 6, the frequency that is received from the transmission line can be determined. The normality of the clock frequency can be identified.
発明の詳細
な説明したように、本発明によれば、基準クロックと外
部から受信されるクロックの位相周波数を比較すること
により、ＡＭＩ／Ｃ旧符号の様な伝送情報にクロック成
分を重畳させた伝送方式に於いて受信装置側の受信クロ
ック復調回路等でクロックの有無、及び周波数変動の監
視を行う場合に伝送路が切断され該復調回路で正常でな
い周波数の疑似クロックが出力されても基準クロックと
の位相周波数を比較監視する方式のため高精度に監視可
能である。As described in detail, according to the present invention, a clock component is superimposed on transmission information such as an AMI/C old code by comparing the phase frequencies of a reference clock and a clock received from the outside. In a transmission system, when monitoring the presence or absence of a clock and frequency fluctuations using a reception clock demodulation circuit, etc. on the receiving device side, even if the transmission line is disconnected and the demodulation circuit outputs a pseudo clock with an abnormal frequency, the reference clock remains unchanged. This method allows for highly accurate monitoring because the phase frequency is compared and monitored.
【図面の簡単な説明】
第１図は本発明に係る伝送路から入力されるクロック周
波数を高精度に監視するためのに必要な構成要素の本発
明の一実施例を示すブロック構成図、第２図は基準タロ
ツクから作成した基準フレームパルス信号と外部から受
信したクロックから作成したフレームパルス信号の位相
比較図、第３図は第２図に示したフレームパルス信号の
位相差とその位相差に比例して変化する出力電圧の特性
グラフを示す図である。[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a block diagram showing an embodiment of the present invention of components necessary for highly accurate monitoring of the clock frequency input from the transmission path according to the present invention. Figure 2 is a phase comparison diagram of the reference frame pulse signal created from the reference clock and the frame pulse signal created from the externally received clock, and Figure 3 shows the phase difference between the frame pulse signal shown in Figure 2 and its phase difference. FIG. 3 is a diagram showing a characteristic graph of an output voltage that changes proportionally.
Claims (1)
する伝送路クロック抽出部と、該クロック抽出部からの
クロックに正常時には従属同期し異常時には自走する位
相同期発振部と、前記クロック抽出部及び該位相同期発
信部から出力される各々のクロックを使用して一定間隔
のパルス信号を作成するパルス信号発生部と、該パルス
信号発生部から出力される各々のパルス信号の位相差を
検出しその位相差をもとに位相差を直線的な出力特性を
もつ電圧に変換する位相差電圧変換部とを有し、入力さ
れるクロック及び基準となるクロックとの位相差を常時
識別監視することを特徴とする伝送周波数監視方式。a transmission line clock extraction unit that demodulates a signal received from a transmission line and extracts a clock component; a phase synchronized oscillation unit that is dependently synchronized to the clock from the clock extraction unit in normal times and runs free in abnormal situations; and the clock extraction unit. and a pulse signal generation section that generates pulse signals at regular intervals using each of the clocks output from the phase synchronization transmission section, and a pulse signal generation section that detects a phase difference between each of the pulse signals output from the pulse signal generation section. and a phase difference voltage conversion unit that converts the phase difference into a voltage with linear output characteristics based on the phase difference, and constantly identifies and monitors the phase difference between the input clock and the reference clock. A transmission frequency monitoring method featuring:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2020316A JPH03226042A (en) | 1990-01-30 | 1990-01-30 | Transmission frequency monitor system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2020316A JPH03226042A (en) | 1990-01-30 | 1990-01-30 | Transmission frequency monitor system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03226042A true JPH03226042A (en) | 1991-10-07 |
Family
ID=12023728
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2020316A Pending JPH03226042A (en) | 1990-01-30 | 1990-01-30 | Transmission frequency monitor system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03226042A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7701268B2 (en) | 2006-02-20 | 2010-04-20 | Nec Corporation | Clock generation circuit |
-
1990
- 1990-01-30 JP JP2020316A patent/JPH03226042A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7701268B2 (en) | 2006-02-20 | 2010-04-20 | Nec Corporation | Clock generation circuit |
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