JPH03209731A - Semiconductor-device mounting method - Google Patents

Semiconductor-device mounting method

Info

Publication number
JPH03209731A
JPH03209731A JP428590A JP428590A JPH03209731A JP H03209731 A JPH03209731 A JP H03209731A JP 428590 A JP428590 A JP 428590A JP 428590 A JP428590 A JP 428590A JP H03209731 A JPH03209731 A JP H03209731A
Authority
JP
Japan
Prior art keywords
die pad
semiconductor
hole
adhesive
bonding agent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP428590A
Other languages
Japanese (ja)
Inventor
Takeshi Nagamura
猛 永村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Radio Co Ltd
Original Assignee
Japan Radio Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Japan Radio Co Ltd filed Critical Japan Radio Co Ltd
Priority to JP428590A priority Critical patent/JPH03209731A/en
Publication of JPH03209731A publication Critical patent/JPH03209731A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To enhance the connecting reliability between a large semiconductor device and a die pad by forming one or a plurality of holes in a semiconductor- device mounting die pad, and removing air and bubbles of solvent and the like generated in an bonding agent in curing which are causes of the remaining of voids and unhardened part. CONSTITUTION:A bonding agent 3 is generally hardened from the outer surface part. Therefore, the larger a semiconductor device 4, the harder the removal of the air and solvent components remaining in the inside. When a hole 7 penetrating a board 1 and a die pad 2 is formed, air stagnating in the bonding agent and bubbles generated from the solvent can be discharged and removed. As the bonding agent, the conductive agent wherein silver powder is mixed as a filler is used. At this time, the die pad itself is made to be the ground so as to made the rear side of the semiconductor to be the electric ground. Therefore, when the inner wall of the hole 7 is metallized and the rear surface of the substrate is made to be the ground, it is effective to achieve the grounding directly by way of the through hole.

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は、基板上のダイパッドに大型半導体素子を接着
剤を用いて装着する方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for mounting a large semiconductor element onto a die pad on a substrate using an adhesive.

（従来の技術） 従来の基板上に設けられたダイパッドと半導体素子の接
続構造の断面図を第２図、第３図に示す。(Prior Art) Cross-sectional views of a conventional connection structure between a die pad and a semiconductor element provided on a substrate are shown in FIGS. 2 and 3.

図において、１は基板、２はダイパッド、３は接着剤、
４は半導体素子、５は接着剤内に残存したボイド、６は
接着剤の未硬化部を示す。In the figure, 1 is a substrate, 2 is a die pad, 3 is an adhesive,
4 is a semiconductor element, 5 is a void remaining in the adhesive, and 6 is an uncured portion of the adhesive.

（発明が解決しようとする課題） 同図からも明らかなように接着剤の硬化後において、接
着剤３内にはボイド５や未硬化部６が残存するため、後
工程で負荷される熱的及び機械的な応力により半導体素
子の脱落が発生し易くなり、接続に対する信頼性を低下
させる原因になっていた。なお、一般的に使用される接
着剤は無溶剤タイプのものが使用され、加熱により硬化
する機構になっているにもかかわらず、粘度等の調整の
ため、溶剤分が５〜１５％程度混合されており、これが
硬化中に、前記の未硬化部を発生させる原因になってい
る。また、従来では接着剤内に残存するのを防ぐ目的で
、ダイボンドを行う前に脱泡やプレキュア−等の処理を
行うことがあるが、逆に接着剤の特性を劣化させたり、
接着剤が硬くなり、半導体素子をダイパッド上に平滑に
接続することが不可能であった。(Problem to be Solved by the Invention) As is clear from the figure, voids 5 and uncured portions 6 remain in the adhesive 3 after the adhesive is cured, so the thermal stress applied in the subsequent process is Also, the semiconductor element is likely to fall off due to mechanical stress, which causes a decrease in the reliability of the connection. Although the commonly used adhesives are solvent-free and have a mechanism of curing by heating, in order to adjust the viscosity etc., the solvent content is about 5 to 15% mixed. This causes the above-mentioned uncured portion to occur during curing. In addition, in the past, treatments such as defoaming and precure were sometimes performed before die bonding in order to prevent the adhesive from remaining in the adhesive, but this could actually deteriorate the properties of the adhesive.
The adhesive became hard and it was impossible to smoothly connect the semiconductor element onto the die pad.

（課題を解決するための手段） 本発明はこのような欠点を解決するため、半導体素子実
装用ダイパッド部に、１個又は複数個の孔を穿つことに
より、ボイドや未硬化部の残存の原因となるエアー及び
接着剤から硬化時に発生する溶剤等の気泡を除去し、大
型半導体素子とダイパッドの接続信頼性を高めることを
目的とする。(Means for Solving the Problems) In order to solve the above-mentioned drawbacks, the present invention creates one or more holes in the die pad portion for mounting semiconductor elements, thereby eliminating the causes of voids and remaining uncured portions. The purpose of this method is to remove bubbles from the air and solvent generated during curing from the adhesive and to improve the reliability of the connection between large semiconductor elements and die pads.

以下に本発明を図面により詳細に説明する。The present invention will be explained in detail below with reference to the drawings.

（実施例） 第１図は本発明の実施例で１は基板、２はダイパッド、
３は接着剤、４は半導体素子、７は孔を示す。(Example) Fig. 1 shows an example of the present invention, where 1 is a substrate, 2 is a die pad,
3 represents an adhesive, 4 represents a semiconductor element, and 7 represents a hole.

接着剤は一般的に外周部から硬化するため、内部に残存
したエアーや溶剤分は、半導体素子４が大型になればな
るほど抜けにくくなるが、基板１とダイパッド２を貫通
する孔７を穿つことで接着剤に滞留するエアーや溶剤か
ら発生する気泡を排気、除去できる。また接着剤はフィ
ラーとして録粉を混入した導電性のものを使用するが、
この場合半導体の裏側を電気的なグランドにするためダ
イパッド自体もグランドとなる。Since the adhesive generally hardens from the outer periphery, it becomes more difficult for the air and solvent remaining inside to escape as the semiconductor element 4 becomes larger. can be used to exhaust and remove air bubbles generated from the air and solvent that remain in the adhesive. In addition, the adhesive used is a conductive one that contains recording powder as a filler.
In this case, since the back side of the semiconductor is electrically grounded, the die pad itself is also grounded.

したかって、第１図に示す孔７の内壁をメタライズして
、基板裏面をグランドとしたときに、スルーホールとし
て、直接グランドに落とすことにも有効である。Therefore, when the inner wall of the hole 7 shown in FIG. 1 is metallized and the back surface of the substrate is grounded, it is also effective to connect it directly to the ground as a through hole.

穿つ孔の径は０．８ｍｍＸ０．８ｍｍ角のチップサイズ
の半導体素子であれば、ダイパッドの中心に直径０．３
ｍｍの孔を一つ設ければ十分である。For a semiconductor element with a chip size of 0.8 mm x 0.8 mm square, the diameter of the hole to be drilled is 0.3 mm at the center of the die pad.
It is sufficient to provide one mm hole.

（発明の効果） 以上説明したように、本発明によれば、基板とダイパッ
ドを貫・通ずる孔を設けることで、大型半導体素子とダ
イパッドの接続に使用する接着剤中のボイドや、接着剤
の未硬化部を無くすことができ、信頼性の高い接続を行
うことができる。(Effects of the Invention) As explained above, according to the present invention, by providing a hole that penetrates a substrate and a die pad, voids in the adhesive used to connect a large semiconductor element and a die pad, and Uncured parts can be eliminated, and highly reliable connections can be made.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明による実施例の断面図、第２図及び第３
図は従来の基板上に半導体素子を接続する構造を示す断
面図である。 １・・・基板、２・・・ダイパッド、３・・・接着剤、 ・半導体素子、 ボイド、 ・未硬化部、 ・孔。FIG. 1 is a sectional view of an embodiment according to the present invention, FIGS.
The figure is a cross-sectional view showing a conventional structure for connecting semiconductor elements on a substrate. DESCRIPTION OF SYMBOLS 1... Substrate, 2... Die pad, 3... Adhesive, - Semiconductor element, Void, - Uncured part, - Hole.

Claims (1)

【特許請求の範囲】[Claims] 　基板に設けたダイパッド上に接着剤を用いて半導体素
子を装着する方法において、前記基板とダイパッドを貫
通する１つ又は複数個の孔を穿つことにより、前記接着
剤に形成されるボイドあるいは接着剤の未硬化部に含ま
れる気泡を除去して、前記半導体素子を前記基板に装着
したことを特徴とする半導体素子の装着方法。In a method of mounting a semiconductor element using an adhesive on a die pad provided on a substrate, a void formed in the adhesive or the adhesive by drilling one or more holes penetrating the substrate and the die pad. A method for mounting a semiconductor device, comprising removing air bubbles contained in an uncured portion of the semiconductor device and mounting the semiconductor device on the substrate.
JP428590A 1990-01-11 1990-01-11 Semiconductor-device mounting method Pending JPH03209731A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP428590A JPH03209731A (en) 1990-01-11 1990-01-11 Semiconductor-device mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP428590A JPH03209731A (en) 1990-01-11 1990-01-11 Semiconductor-device mounting method

Publications (1)

Publication Number Publication Date
JPH03209731A true JPH03209731A (en) 1991-09-12

Family

ID=11580260

Family Applications (1)

Application Number Title Priority Date Filing Date
JP428590A Pending JPH03209731A (en) 1990-01-11 1990-01-11 Semiconductor-device mounting method

Country Status (1)

Country Link
JP (1) JPH03209731A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004228167A (en) * 2003-01-20 2004-08-12 Sanyo Electric Co Ltd Lead frame and semiconductor device using it
EP2688095A3 (en) * 2012-07-18 2016-08-10 Nichia Corporation Semiconductor component support and semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63169033A (en) * 1987-01-06 1988-07-13 Nec Corp Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63169033A (en) * 1987-01-06 1988-07-13 Nec Corp Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004228167A (en) * 2003-01-20 2004-08-12 Sanyo Electric Co Ltd Lead frame and semiconductor device using it
EP2688095A3 (en) * 2012-07-18 2016-08-10 Nichia Corporation Semiconductor component support and semiconductor device
US10068821B2 (en) 2012-07-18 2018-09-04 Nichia Corporation Semiconductor component support and semiconductor device

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