JPH03194921A - Semiconductor epitaxial wafer and its manufacture - Google Patents
Semiconductor epitaxial wafer and its manufactureInfo
- Publication number
- JPH03194921A JPH03194921A JP33342189A JP33342189A JPH03194921A JP H03194921 A JPH03194921 A JP H03194921A JP 33342189 A JP33342189 A JP 33342189A JP 33342189 A JP33342189 A JP 33342189A JP H03194921 A JPH03194921 A JP H03194921A
- Authority
- JP
- Japan
- Prior art keywords
- plane
- single crystal
- epitaxial
- epitaxial wafer
- unevenness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000013078 crystal Substances 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims description 16
- 239000007791 liquid phase Substances 0.000 claims description 6
- 238000005520 cutting process Methods 0.000 claims description 4
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 claims 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052757 nitrogen Inorganic materials 0.000 abstract description 2
- 239000000758 substrate Substances 0.000 description 14
- 238000005204 segregation Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 238000009826 distribution Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000295 emission spectrum Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000002441 X-ray diffraction Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000003909 pattern recognition Methods 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Landscapes
- Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はエピタキシャルウェハー及びその製造方法に関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an epitaxial wafer and a method for manufacturing the same.
■−Ｖ族化合物半導体のエピタキシャル成長層は発光ダ
イオード、レーザーダイオードなどの光デバイスや、Ｆ
ＥＴなどの高速デバイスなどに広く応用されている。■-Epitaxially grown layers of group V compound semiconductors are used in optical devices such as light-emitting diodes and laser diodes,
It is widely applied to high-speed devices such as ET.
これらの薄膜エピタキシャル成長法としては大別して液
相エピタキシャル成長法と気相エピタキシャル成長法が
ある。These thin film epitaxial growth methods can be broadly classified into liquid phase epitaxial growth methods and vapor phase epitaxial growth methods.
従来の液相エピタキシャル成長法に於ては、（１１１）
面、あるいは（１００）面のような面方位を持つ単結晶
ウェハーが基板として使用されている。In the conventional liquid phase epitaxial growth method, (111)
A single crystal wafer having a plane orientation such as a plane or a (100) plane is used as a substrate.
この面方位は、エピタキシャル層の成長速度、ドーパン
トの偏析係数の面方位依存性から最適な面方位として選
択されている。エピタキシャル成長は単結晶表面の原子
ステップ（キンク）に原子が結合することによって進行
するが、この速度は成長する方位によって異なる。This plane orientation is selected as the optimum plane orientation based on the growth rate of the epitaxial layer and the dependence of the dopant segregation coefficient on the plane orientation. Epitaxial growth proceeds by atoms bonding to atomic steps (kinks) on the surface of a single crystal, and the rate of this growth varies depending on the direction of growth.
たとえば、（１１１）面のごとく原子ステップが明瞭に
現われる面上では成長は遅く、一方、（２１１）面のご
とく大きな面指数をもった面上では結晶成長速度は早く
なる傾向にある。このため、液相エピタキシャル成長に
於て（ｌ １１）面に＜ｉｌｌ＞方向に結晶を成長させ
る場合、−度、＜ｉｌｌ＞とは異なる方位への結晶成長
が始まってしまうと、エピタキシャル成長に伴って成長
速度差が強調され、エピタキシャル成長後の表面に縞模
様状の深さ１０〜２０μｓの凹凸が発生する場合がある
。結晶の成長速度が異なると、その近傍の実効偏析係数
も異なる。このために、結晶成長の際に添加する微量不
純物（ドーパント）ａ度がエピタキシャル層の凹凸に対
応して異なっていることが明らかになっている（西永、
Ｊｏｕｒｎａｌｏｒ Ｊａｐａｎｅｓｅ Ａｐｐｌｉ
ｅｄ Ｐｈｙｓｉｃｓ 、 ｖｏｌ、２４． ｐ、２２
９゜１９８５参照）。たとえば、偏析係数が１より小さ
い場合には凸部に多く偏析し、逆に偏析係数が１より大
きい場合には凹部に多く偏析する。For example, crystal growth tends to be slow on a plane where atomic steps clearly appear, such as the (111) plane, while crystal growth tends to be fast on a plane with a large plane index, such as the (211) plane. For this reason, when growing a crystal in the <ill> direction on the (l 11) plane in liquid phase epitaxial growth, if the crystal growth starts in a direction different from the <ill> direction by − degrees, the epitaxial growth The difference in growth rate is accentuated, and a striped pattern of irregularities with a depth of 10 to 20 μs may occur on the surface after epitaxial growth. When the crystal growth rate differs, the effective segregation coefficient in the vicinity also differs. For this reason, it has become clear that the concentration of trace impurities (dopants) added during crystal growth differs depending on the unevenness of the epitaxial layer (Nishinaga,
Journal Japanese Appli
ed Physics, vol, 24. p, 22
9゜1985). For example, when the segregation coefficient is less than 1, a large amount of the material segregates in convex portions, and conversely, when the segregation coefficient is greater than 1, a large amount of material segregates in concave portions.
前項で述べたように、（ｉｌｌ）面にエピタキシャル成
長を行なうと成長表面に縞模様の凹凸が生じる場合があ
る。この凹凸は例えば、デバイスを作製するために、こ
の表面に作成された電極パターンを自動的に検査しよう
とする場合、凹凸によってパターンが歪み、パターン認
識装置が正しくパターンを識別できないという問題が生
じる。As described in the previous section, when epitaxial growth is performed on the (ill) plane, striped irregularities may occur on the growth surface. For example, when attempting to automatically inspect an electrode pattern created on this surface in order to fabricate a device, the unevenness causes a problem in that the pattern is distorted and the pattern recognition device cannot correctly identify the pattern.
また、前述のように凸部と凹部では、ドーパント濃度が
２〜ＩＯ倍程度異なるので、凹凸のウェハー面内分布状
態によっては、１枚のエピタキシャル基板から２００〜
３００μｓ角の多数のデバイスを作成すると、その電子
特性のバラツキが大きくなることがある。従って、例え
ばＬＥＤの場合には１枚のウェハーから得られるチエツ
ブ間で、色調、明るさ等の光学特性のバラツキが多くな
る問題点がある。Furthermore, as mentioned above, the dopant concentration in the convex portions and the concave portions differs by a factor of 2 to IO, so depending on the distribution state of the concavities and convexities within the wafer surface, it is possible to
When a large number of devices of 300 μs square are manufactured, variations in their electronic characteristics may become large. Therefore, for example, in the case of LEDs, there is a problem that optical characteristics such as color tone and brightness vary widely between chips obtained from one wafer.
本発明は極めて平易な方法でこの成長表面の凹凸を制御
し、実質的に均一な成長表面を持つエピタキシャルウェ
ハーを提供することを目的とする。An object of the present invention is to control the unevenness of the growth surface using an extremely simple method and to provide an epitaxial wafer having a substantially uniform growth surface.
成長表面の凹凸に伴う問題点を解決する手段としては、
表面の凹凸を完全になくしてしまう方法と、この凹凸の
分布のピッチをデバイスのサイズより細かくする方法の
２つが考えられる。前者の方法は、エピタキシャル層成
長がキンクの存在によって起こるので、原理的にかなり
困難である。As a means to solve the problems associated with the unevenness of the growth surface,
There are two possible methods: completely eliminating the unevenness on the surface, and making the pitch of the unevenness distribution smaller than the size of the device. The former method is quite difficult in principle since epitaxial layer growth occurs due to the presence of kinks.
本発明は後者の手段を実現させるものである。The present invention realizes the latter means.
本発明は（１１１）面から０．５〜２度の範囲でずらし
た単結晶基板（以下、これをオフアングル基板と呼ぶ）
を用いてエピタキシャルを実施するものである。基板の
面方位が従来と異なる点を除き、エピタキシャル成長条
件は従来と同一条件で支障がなく、また、エピタキシャ
ル層の電気的、光学的特性もバラツキの程度を除けば従
来法で作製されたものと比較して有意差はない。基板の
面方位をずらす範囲を上記のように設定した理由は、以
下のとおりである。The present invention uses a single crystal substrate that is shifted from the (111) plane by 0.5 to 2 degrees (hereinafter referred to as an off-angle substrate).
The epitaxial process is carried out using the following method. Except for the difference in the plane orientation of the substrate, the epitaxial growth conditions were the same as before, and there were no problems, and the electrical and optical properties of the epitaxial layer were the same as those produced by the conventional method, except for the degree of variation. There is no significant difference in comparison. The reason why the range in which the plane orientation of the substrate is shifted is set as described above is as follows.
（ｌ ｌ ｌ）面からのずれが０，５度未満の場合、エ
ピタキシャル成長表面のモホロジーは（ｌ ｌ １）而
を使用した場合と差がない。また、このずれが２度以上
になると、格子定数の不整合などの原因で正常なエピタ
キシャル成長が実現されない。When the deviation from the (l l l) plane is less than 0.5 degrees, the morphology of the epitaxially grown surface is no different from that when using the (l l 1) plane. Furthermore, if this deviation exceeds 2 degrees, normal epitaxial growth will not be achieved due to lattice constant mismatch.
エピタキシャル成長に使用する単結晶基板の面方位を（
ｌ ｌ ｌ）面からずらすと、基板表面に、エピタキシ
ャル成長の核となるステップが多数露出する。（Ｌ ｌ
ｌ）面とは異なり、基板表面に予め、多数の成長点が
用意されていることになるので、エピタキシャル表面の
凹凸の周期を、従来の数關のオーダーから５０−程度ま
で細かくすることが実現できる。この結果、例えば発光
ダイオードなどのように、２５０〜３０〇−角の素子を
、このエピタキシャルウェハーから製作する場合、全て
の素子に凸部と凹部を同時に含ませることが可能になる
。The plane orientation of the single crystal substrate used for epitaxial growth is (
When shifted from the l l l) plane, a large number of steps that become the core of epitaxial growth are exposed on the substrate surface. (L l
l) Unlike the surface, many growth points are prepared in advance on the substrate surface, so it is possible to reduce the periodicity of the irregularities on the epitaxial surface from the conventional order of several orders of magnitude to about 50. can. As a result, when a 250 to 300 square element, such as a light emitting diode, is manufactured from this epitaxial wafer, it becomes possible to simultaneously include convex portions and concave portions in all the elements.
これによって１枚のウェハーから多数個のデバイスを取
る場合にエピタキシャルウェハー面内の成長表面の凹凸
に起因するデバイス間の諸特性のバラツキが実質的に低
減されたことになる。As a result, when a large number of devices are produced from one wafer, variations in characteristics between devices due to unevenness of the growth surface within the plane of the epitaxial wafer are substantially reduced.
基板方位を０．５〜２度傾ける方法としては、単結晶イ
ンゴットから基板を切出す際に、Ｘ線回折により方位を
検出し、それに基づき切削治具の角度調整機構を利用し
て（ｌ ｌ ｌ）面から０６５〜２度の範囲で方位をず
らして切断すれば良い。A method for tilting the substrate orientation by 0.5 to 2 degrees is to detect the orientation by X-ray diffraction when cutting the substrate from a single crystal ingot, and then use the angle adjustment mechanism of the cutting jig based on the orientation (l l l) The cutting may be performed by shifting the direction within a range of 065 to 2 degrees from the plane.
方向を若干ずらすことにより、エピタキシャル成長の核
となるステップを多数露出させ、エピタキシャル成長の
同時進行をはかるものである。By slightly shifting the direction, a large number of steps that are the core of epitaxial growth are exposed, and epitaxial growth can proceed simultaneously.
ＧａＰ単結晶基板を用い（ｌ ｌ ｌ）面（従来例）、
及び、これから、０．７．０．１１１． ２度ずらした
面方位のオフアングル基板を用いて、窒素ドープＧａＰ
層を液相エピタキシャル成長させた場合の表面状態を表
面粗さ計で測定した。結果を第１図ないし第４図に示す
。第１図は従来の＜１１１＞方向の場合、第２図ないし
第４図は、それぞれ＜ｉｌｌ＞方向から０．７度、０．
８度、２度ずらしたオフアングル基板の場合を示す。測
定はウェハーの直径方向に沿って行なった。これらの結
果から、従来品では数＋ｍｍの周期で存在する深さ１０
〜２０即の表面の凹凸が、本発明によるオフアングル基
板を用いた場合には、はとんど解消されていることがわ
かる。このエピタキシャルウェハーに電極を加工し３５
０μｓ角の発光ダイオードを作成した。Using a GaP single crystal substrate (l l l) plane (conventional example),
And from now on, 0.7.0.111. Nitrogen-doped GaP was produced using an off-angle substrate with a plane orientation shifted by 2 degrees.
The surface condition when the layer was grown by liquid phase epitaxial growth was measured using a surface roughness meter. The results are shown in Figures 1 to 4. FIG. 1 shows the conventional <111> direction, and FIGS. 2 to 4 show 0.7 degrees and 0.7 degrees from the <ill> direction, respectively.
The cases of off-angle boards shifted by 8 degrees and 2 degrees are shown. Measurements were taken along the diameter of the wafer. From these results, it can be seen that the conventional product has a depth of 10 mm, which exists at a period of several + mm.
It can be seen that the unevenness on the surface of ~20 mm is almost eliminated when the off-angle substrate according to the present invention is used. Electrodes are processed on this epitaxial wafer and 35
A 0 μs square light emitting diode was created.
発光ダイオードの発光波長の市内バラツキを測定した結
果を第５図及び第６図に示す。測定は第７図に示すよう
にウェハーの２方向の直径方向に沿って行ない、０．５
ｍ脂層ハーフダイス後ライン当り３２点をとり、３点毎
に測った。ＧａＰ黄緑色発光ダイオードに於ては、窒素
ドープ量が発光波長に大きな影響を与えるが、第５図、
第６図から明らかなように、従来品よりもオフアングル
品の方が発光波長の面内バラツキがσ″：０．２：０．
２程度＝０．１と小さくなっており、前述の目的が達成
されていることがわかる。The results of measuring the variation in the emission wavelength of the light emitting diodes within the city are shown in FIGS. 5 and 6. Measurements were made along the diameter of the wafer in two directions as shown in Figure 7.
After half-dicing the fat layer, 32 points were taken per line, and measurements were taken every three points. In GaP yellow-green light emitting diodes, the amount of nitrogen doping has a large effect on the emission wavelength;
As is clear from FIG. 6, the off-angle product has a greater in-plane variation in emission wavelength than the conventional product, σ″: 0.2:0.
It can be seen that the above-mentioned objective has been achieved.
本発明のウェハーを使用すれば、成長表面の凹凸の周期
がデバイスのサイズより充分に小さく、この凹凸によっ
て生じるデバイス間の特性のバラツキが低減された半導
体デバイスを提供することができる。By using the wafer of the present invention, it is possible to provide a semiconductor device in which the period of the unevenness on the growth surface is sufficiently smaller than the size of the device, and the variation in characteristics between devices caused by the unevenness is reduced.
この方法が従来法と異なっている点は、オフアングル基
板を使用する点のみであるので、本方法は特に経費を増
加させることなく、従来技術の延長として直ちに製造す
ることが可能である。Since this method differs from the conventional method only in that an off-angle substrate is used, the present method can be manufactured immediately as an extension of the conventional technique without increasing costs.
第１図〜第４図は、液相エピタキシャルウェハーの表面
の凹凸を示す図、第５図及び第６図は発光ダイオードの
発光スペクトルのウェハー面内のバラツキを示す図であ
る。第７図はエピタキシャルウェハー内の発光スペクト
ル１ｌｉＪ定方向を示す図である。
第１図
第２図1 to 4 are diagrams showing irregularities on the surface of a liquid phase epitaxial wafer, and FIGS. 5 and 6 are diagrams showing variations in the emission spectrum of light emitting diodes within the wafer surface. FIG. 7 is a diagram showing the emission spectrum 1liJ constant direction within the epitaxial wafer. Figure 1 Figure 2
Claims (1)
度ずれた面方位を有するエピタキシャル成長層を具備し
てなることを特徴とする半導体エピタキシャルウェハー
。 ２）単結晶がガリウムリン（ＧａＰ）であることを特徴
とする第１項記載の半導体エピタキシャルウェハー。 ３）単結晶を（＠１＠＠１＠＠１＠）面から０．５〜２
度ずらした面で切断し、該切断面の上に半導体結晶層を
エピタキシャル成長させることを特徴とする半導体エピ
タキシャルウェハーの製造方法。 ４）エピタキシャル成長が液相法であることを特徴とす
る第３項記載の半導体エピタキシャルウェハーの製造方
法。[Claims] 1) 0.5 to 2 from the (@1@1@1@1@) plane of the single crystal
A semiconductor epitaxial wafer comprising an epitaxial growth layer having a misaligned plane orientation. 2) The semiconductor epitaxial wafer according to item 1, wherein the single crystal is gallium phosphide (GaP). 3) 0.5 to 2 points from the (@1@1@1@1) plane of the single crystal
1. A method for manufacturing a semiconductor epitaxial wafer, which comprises cutting a semiconductor epitaxial wafer on a plane that is shifted by a certain degree, and epitaxially growing a semiconductor crystal layer on the cut plane. 4) The method for manufacturing a semiconductor epitaxial wafer according to item 3, wherein the epitaxial growth is a liquid phase method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33342189A JPH03194921A (en) | 1989-12-22 | 1989-12-22 | Semiconductor epitaxial wafer and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33342189A JPH03194921A (en) | 1989-12-22 | 1989-12-22 | Semiconductor epitaxial wafer and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03194921A true JPH03194921A (en) | 1991-08-26 |
Family
ID=18265925
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33342189A Pending JPH03194921A (en) | 1989-12-22 | 1989-12-22 | Semiconductor epitaxial wafer and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03194921A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011216780A (en) * | 2010-04-01 | 2011-10-27 | Shin Etsu Handotai Co Ltd | Silicon epitaxial wafer, method for producing the same, method for producing bonded soi wafer, and bonded soi wafer |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5438599A (en) * | 1977-09-01 | 1979-03-23 | Matsushita Electric Ind Co Ltd | Preparing piezo-electric sheet |
-
1989
- 1989-12-22 JP JP33342189A patent/JPH03194921A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5438599A (en) * | 1977-09-01 | 1979-03-23 | Matsushita Electric Ind Co Ltd | Preparing piezo-electric sheet |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011216780A (en) * | 2010-04-01 | 2011-10-27 | Shin Etsu Handotai Co Ltd | Silicon epitaxial wafer, method for producing the same, method for producing bonded soi wafer, and bonded soi wafer |
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