JPH03192706A - Formation of electrode for laminated lc chip - Google Patents
Formation of electrode for laminated lc chipInfo
- Publication number
- JPH03192706A JPH03192706A JP33127289A JP33127289A JPH03192706A JP H03192706 A JPH03192706 A JP H03192706A JP 33127289 A JP33127289 A JP 33127289A JP 33127289 A JP33127289 A JP 33127289A JP H03192706 A JPH03192706 A JP H03192706A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- laminated
- plating
- external electrode
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015572 biosynthetic process Effects 0.000 title 1
- 238000007747 plating Methods 0.000 claims abstract description 37
- 229910000679 solder Inorganic materials 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 9
- 229910052751 metal Inorganic materials 0.000 claims abstract description 9
- 239000003990 capacitor Substances 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 7
- 239000004020 conductor Substances 0.000 claims description 4
- 238000007772 electroless plating Methods 0.000 claims description 4
- 238000009713 electroplating Methods 0.000 abstract description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 26
- 239000011248 coating agent Substances 0.000 description 14
- 238000000576 coating method Methods 0.000 description 14
- 229910052759 nickel Inorganic materials 0.000 description 13
- 229910000859 α-Fe Inorganic materials 0.000 description 7
- 239000011230 binding agent Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000001354 calcination Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010304 firing Methods 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 210000004899 c-terminal region Anatomy 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000003756 stirring Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、積層ＬＣＣチップ品の外部電極形成方法に係
わり、ＬＣ回路の外部電極のメッキによる形成方法を改
善したものに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming external electrodes of a laminated LCC chip product, and relates to an improved method for forming external electrodes of an LC circuit by plating.
Ｃ従来の技術〕
電子機器にはＬＣ回路が多く用いられているが、コンパ
クトな部品として積層ＬＣチップ部品が広く用いられて
いる。この積層ＬＣＣチップ品の構成は、例えば第３図
（ロ）に示すＬｌ、Ｌ２、のインダクタと、Ｃのコンデ
ンサをＴ型に接続したＴ型ＬＣ回路の場合、第３図（イ
）に示すように、インダクタ部１、コンデンサ部２を積
層する。インダクタ部１は左右一対のコイル３．４を接
続して形成され、コンデンサ部は誘電体を上下一対の内
部電極５．６により挟持して形成される。これらのコイ
ル３．４は導体による配線を形成したフェライト材料か
らなる基板を積層し、それぞれの基板をスルボールによ
り接続して形成され、内部電極５．６は電極層を形成し
た誘電体材料からなる基板を積層して形成される。C. Prior Art] LC circuits are often used in electronic devices, and laminated LC chip components are widely used as compact components. The configuration of this multilayer LCC chip product is, for example, in the case of a T-type LC circuit in which inductors Ll and L2 shown in Fig. 3 (b) and capacitor C are connected in a T-shape, as shown in Fig. 3 (a). The inductor section 1 and capacitor section 2 are stacked in this manner. The inductor section 1 is formed by connecting a pair of left and right coils 3.4, and the capacitor section is formed by sandwiching a dielectric between a pair of upper and lower internal electrodes 5.6. These coils 3.4 are formed by laminating substrates made of ferrite material on which conductor wiring is formed, and connecting the substrates with through balls, and the internal electrodes 5.6 are made of dielectric material on which electrode layers are formed. It is formed by laminating substrates.
そして第３図（イ）に示す積層体の外壁には第３図（ロ
）に示すＬＣ回路のＬＣ接続部分の■に対応するＬＣ回
路接続外部電極７、同様にＬｌ、Ｌ２の端子■、■に対
応するコイル３．４のそれぞれの端子の外部電極８．９
、同様にＣの端子■に対応するコンデンサの内部電極の
端子に外部電極１０がそれぞれ形成される。Then, on the outer wall of the laminate shown in FIG. 3(a), there is an LC circuit connecting external electrode 7 corresponding to the LC connection part of the LC circuit shown in FIG. External electrode 8.9 of each terminal of coil 3.4 corresponding to ■
, similarly, external electrodes 10 are respectively formed at the terminals of the internal electrodes of the capacitor corresponding to the terminals (2) of C.
ところで、第３図（イ）に示す積層体の外壁に形成され
る外部電極は、上記コイルの配線用、コンデンサの内部
電極用塗膜を形成したグリーンシートを積層した未焼成
積層体を焼成した後の積層体に、第１層の導体ペースト
塗膜を形成して焼き付け、その焼き付は導電塗膜の上に
第２層のニッケルのバレル電解メッキを施し、最後に第
３層のはんだのバレルメッキを施す。By the way, the external electrodes formed on the outer wall of the laminate shown in FIG. The first layer of conductive paste coating is formed and baked on the subsequent laminate, and the baking process is accomplished by applying barrel electroplating of nickel as the second layer on top of the conductive coating, and finally applying the third layer of solder. Apply barrel plating.
この外部電極を形成する工程において、第２層のニッケ
ルメッキ、第３層のはんだメッキを施す際に用いるバレ
ル電解メッキは、メンシュのバレル（籠）の中に陰極を
設け、これに対応してバレルの外部に設けた陽極との間
にメッキ浴を介在させ、上記バレルに上記第１層の焼き
付は導電塗膜を形成した積層体と粒状の導体のダミーを
入れ、これらを−緒に攪拌しながらメッキを行うもので
ある。この場合、陰極と直接又はダミーを通して通電さ
れることによりメッキが施されるので、上記積層体は静
止してメッキされるよりも各導電塗膜に平等にメッキさ
れる機会が与えられる。In the process of forming this external electrode, barrel electrolytic plating is used to apply the second layer of nickel plating and the third layer of solder plating. A plating bath is interposed between the anode provided on the outside of the barrel, and a laminate with a conductive coating and a dummy of a granular conductor are placed in the barrel to bake the first layer, and these are placed together. Plating is performed while stirring. In this case, since plating is performed by applying electricity directly to the cathode or through a dummy, each conductive coating film is given an equal opportunity to be plated, compared to when the laminate is plated statically.
゛〔発明が解決しようとする課題〕
しかしながら、第３図（ロ）の等価回路からも知られる
ように、インダクタンスＬｌ、Ｌ２の端子■、■及びそ
の接続部■のいずれか１つが陰極と電気的に導通される
と他の端子も電気的に導通されるが、コンデンサＣの端
子■はこれらとは電気的に絶縁される。この結果、■の
部分が通電される確率は、Φ〜■の場合の１７３となり
、メンキされる確率も低くなる。[Problem to be Solved by the Invention] However, as is known from the equivalent circuit in FIG. When the capacitor C is electrically connected, the other terminals are also electrically electrically connected, but the terminal (2) of the capacitor C is electrically insulated from these terminals. As a result, the probability that the part (■) will be energized is 173 in the case of Φ to (■), and the probability that it will be damaged is also low.
この結果、第３図（ロ）の■〜■に対応する第３図（イ
）の外部電極７〜９はメッキ膜が厚くり、■に対応るす
外部電極１０はメッキ膜が薄くなり、メッキ膜の厚さに
バラツキが生じる。第２層のニッケルメッキ層が薄いか
、あるいは不均一になると、これに第３層のはんだメッ
キを施しても、はんだ食われを起こす。これを防ぐため
に■に対応する外部電極のニッケルメッキ層を厚くする
と、今度は■〜■に対応する外部電極のニッケルメッキ
層が厚過ぎることになり、この上にはんがメッキ層を形
成した外部電極はストレスが大きくなり、外部電極その
ものの素地に対する接着強度が低下したり、素地にクラ
ンクを起こすことがあるゆ本発明の目的は、特に電解ニ
ッケルメッキによるメッキ層の厚さのバラツキあるいは
メッキ層が不均一になることを少なくし、ＬＣ回路の各
端子の外部電極に−様な厚さのニッケルメッキ層を形成
できる積層ＬＣチップ部品の外部電極形成方法を提供す
ることにある。As a result, the plating film of the external electrodes 7 to 9 in FIG. 3(a) corresponding to the numbers ■ to ■ in FIG. 3(b) becomes thicker, and the plating film of the external electrode 10 corresponding to Variations occur in the thickness of the plating film. If the second nickel plating layer is thin or uneven, even if a third layer of solder plating is applied thereto, solder erosion will occur. To prevent this, if the nickel plating layer of the external electrode corresponding to ■ is made thicker, the nickel plating layer of the external electrode corresponding to ■ to ■ becomes too thick, and a solder plating layer is formed on top of this. The stress on the external electrode becomes large, which may reduce the adhesion strength of the external electrode itself to the base material or cause cranking of the base material. It is an object of the present invention to provide a method for forming an external electrode of a laminated LC chip component, which can reduce non-uniformity of the layers and form a nickel plating layer of varying thickness on the external electrode of each terminal of an LC circuit.
本発明は、上記課題を解決するために、導体の配線を有
する複数の絶縁体基板を積層しそれぞれの絶縁体基板の
配線を接続してコイルを形成したインダクタ部と、誘電
体の両側に電極を形成した少なくとも１組のコンデンサ
部とを積層した積層体の外壁にＬＣ回路の外部電極を形
成する積層ＬＣチンプ部品の電極形成方法において、そ
れぞれの外部電極が形成される外壁に導電膜を形成する
工程と、この導１！膜に金属無電解メッキを施す工程と
、この金属無電解メッキ層にはんだの電解メッキを施す
工程を有することを特徴とする積層ＬＣチップ部品の電
極形成方法を提供するものである。In order to solve the above problems, the present invention provides an inductor section in which a plurality of insulating substrates having conductor wiring are stacked and connecting the wiring of each insulating substrate to form a coil, and electrodes on both sides of the dielectric. In a method for forming an electrode for a laminated LC chimp component, in which an external electrode of an LC circuit is formed on an outer wall of a laminate in which at least one set of capacitor parts is laminated, a conductive film is formed on the outer wall on which each external electrode is formed. The process and this guide 1! The present invention provides a method for forming electrodes of a laminated LC chip component, which comprises the steps of applying electroless metal plating to a film and electrolytically plating solder to the electroless metal plating layer.
第１層の導電膜上に第２層、この第２層に第３層のメッ
キ層を順次形成する際に、第２層を無電解メッキにより
形成したので、この第２層のメキ層が均一厚さに形成さ
れる。When forming the second layer on the first conductive film and the third plating layer on the second layer, the second layer was formed by electroless plating, so the second plating layer was Formed to a uniform thickness.
次に本発明の一実施例を第１図ないし第３図に基づいて
説明する。Next, one embodiment of the present invention will be described based on FIGS. 1 to 3.
第１図（イ）に示すように、フェライト粉末とバインダ
ーからなるフェライトグリーンシート１１に導体ペース
トによる配線塗膜１２を形成したコイル用グリーンシー
）１３と、同様にフェライトグリーンシート１１’ に
別の配線量Ｍ＊ １２ ’を形成したコイル用グリーン
シート１３° と、同様にフェライトグリーンシート１
１°°に別の配線量１１ｉ１２”を形成したコイル用グ
リーンシート１３１とを積層し、それぞれのシートをス
ルーホールで接続し、第３図（イ）に示すコイル３．４
に対応する左右一対のコイル用塗膜を形成し、その積層
体の両側から上記フェライトグリーンシート１１と同様
の組成で厚さの厚いフェライトグリーンシート１４．１
４゛ を圧着積層してグリーンシート積層体の第２図に
示すインダクタンス未焼成部１５を形成する。As shown in FIG. 1(a), a coil green sheet 13 in which a wiring coating film 12 made of conductive paste is formed on a ferrite green sheet 11 made of ferrite powder and a binder, and another coated ferrite green sheet 11' in the same manner as shown in FIG. A coil green sheet 13° with a wiring amount M* 12' and a ferrite green sheet 1
A coil green sheet 131 with a different wiring amount 11i12" formed at 1°° is laminated, and each sheet is connected with a through hole to form a coil 3.4 shown in FIG. 3(A).
A pair of left and right coil coating films corresponding to the above are formed, and a thick ferrite green sheet 14.1 having the same composition as the above ferrite green sheet 11 is applied from both sides of the laminate.
4'' are laminated under pressure to form an inductance unfired portion 15 shown in FIG. 2 of the green sheet laminate.
一方、第１図（ロ）に示すように、誘電体原料とバイン
ダーからなる誘電体グリーンシート１６に導電ペースト
により内部電極塗膜１７を形成したコンデンサ用グリー
ンシート１８と、同様に誘電体グリーンシート１６’
に内部電極１７”を形成したコンデンサ用グリーンシー
ト１８″ とを積層し、その両側から同様の組成で厚さ
の厚い誘電体グリーンシート１９．１９″を圧着積層し
て第２図にグリーンシート積層体のコンデンサ未焼成部
２０を形成する。On the other hand, as shown in FIG. 1(B), there is a capacitor green sheet 18 in which an internal electrode coating film 17 is formed using a conductive paste on a dielectric green sheet 16 made of a dielectric raw material and a binder, and a dielectric green sheet 18 in which an internal electrode coating film 17 is formed using a conductive paste. 16'
A capacitor green sheet 18'' with an internal electrode 17'' formed on the capacitor green sheet 18'' is laminated on the top, and thick dielectric green sheets 19.19'' with the same composition are laminated from both sides by pressure bonding, and the green sheet lamination is shown in Figure 2. A capacitor green portion 20 of the body is formed.
この際、第３図く口）に示す等価回路のインダクタし及
びＬｌの接続部■及びこれらＬｌ、Ｌｌの端子■、■に
対応して、第１図、第２図に示すように、インダクタ未
焼成部１５の配線塗膜１２”°、１２をその積層体の３
つのそれぞれの外壁に導出して導出部１２ａ 、 １２
ｂ 、 １２ｃとするとともに、コンデンサ未焼成部２
０の一万の内部電極塗膜１７’ を上記導出部１２ａと
同一平面をなす外壁に導出して導出部１７’ａとし、そ
の残りの内部電極塗膜１７を上記いずれの内部電極塗膜
、配線塗膜も導出されていない外壁に導出し導出部１７
ａとする。At this time, as shown in Fig. 1 and Fig. 2, the inductor is The wiring coating film 12” of the unfired part 15, 12 is 3 of the laminate.
The lead-out portions 12a, 12 are led out to each of the outer walls.
b, 12c, and the capacitor unfired part 2
010,000 internal electrode coating film 17' is led out to the outer wall forming the same plane as the above-mentioned leading-out part 12a to form the leading-out part 17'a, and the remaining internal electrode coating film 17 is any of the above-mentioned internal electrode coating films, The lead-out portion 17 is led out to the outer wall where the wiring coating film is also not led out.
Let it be a.
そして第２図に示すように、上記インダクタンス未焼成
部１５とコンデンサ未焼成部２０を圧着して積層する。Then, as shown in FIG. 2, the inductance unfired part 15 and the capacitor unfired part 20 are pressed together and laminated.
この後、仮焼してバインダーを焼失させ、本焼成するか
、あるいは・仮焼と本焼成を一連の工程で行ない、第３
図（イ）に示すように、焼成した積層体であって、コイ
ル３．４を形成するインダクタ部１と、内部電極５１．
６に誘電体を挟持したコンデンサ部２を有する積層ＬＣ
回路体を作製する。After this, either calcination is performed to burn out the binder and main firing is performed, or ・Calcination and main firing are performed in a series of steps, and then the third
As shown in Figure (a), the fired laminate includes an inductor portion 1 forming a coil 3.4, an internal electrode 51.
A multilayer LC having a capacitor part 2 with a dielectric material sandwiched between 6 and 6.
Create a circuit body.
次に、第３図（イ）に示すように、この積層ＬＣ回路体
の外壁であって、第２図に示す上記導出部１２ａと導出
部１７゛ａが導出されている面に対応する面、同様に他
の導出部１２ｂ 、１２ｃがそれぞれ導出さている面及
び上記導出部１７ａが導出されている面のそれぞれに対
応する面に、これらの導出部と接続する導電膜を、Ａｇ
８５重量部、ガラス１５重量部を含有する導電ペース
トを塗布して焼き付けることにより形成する。Next, as shown in FIG. 3(a), a surface of the outer wall of this laminated LC circuit body corresponding to the surface from which the leading portion 12a and the leading portion 17'a shown in FIG. 2 are led out. , Similarly, a conductive film connected to these lead-out parts is formed on a surface corresponding to the face where the other lead-out parts 12b and 12c are led out, and the face where the lead-out part 17a is led out, respectively.
It is formed by applying and baking a conductive paste containing 85 parts by weight and 15 parts by weight of glass.
次いで、これをベルニッケル液に４５℃で、２５分浸漬
することにより無電解ニッケルメッキを施す。Next, electroless nickel plating is applied by immersing this in a Bell nickel solution at 45° C. for 25 minutes.
そして、さらにははんだ電解メッキをバレルメッキ法に
より、１０Ａ、４０分の条件で行なう、このようにして
第３図（ロ）のＬＣ接続部■に対応する第３図（イ）に
示す外部電極７、同様にＬｌ、Ｌｌの端子■、■に対応
する外部電極８．９及び同様にＣの端子に対応する外部
電極ｌＯを有する積層ＬＣＣチップ品が完成される。Furthermore, solder electrolytic plating is carried out by the barrel plating method at 10A for 40 minutes.In this way, the external electrodes shown in Figure 3 (A) corresponding to the LC connection part (■) in Figure 3 (B) are 7. Similarly, a laminated LCC chip product is completed having external electrodes 8.9 corresponding to Ll, Ll terminals (2) and (2), and external electrode 10 similarly corresponding to C terminal.
このようにして得られた積層ＬＣチップ部品について、
ニッケルメッキ層の厚さ、はんだメッキ層の厚さを測定
した結果を下記表に示す。表中、括弧内は第３図（イ）
の外部電極に対応する第３図（ロ）の端子番号である。Regarding the laminated LC chip parts obtained in this way,
The results of measuring the thickness of the nickel plating layer and the solder plating layer are shown in the table below. Figure 3 (a) is in parentheses in the table.
These are the terminal numbers in FIG. 3 (b) corresponding to the external electrodes.
なお、メッキ層の厚さの測定はメッキ面を研磨して光学
顕微鏡で測定した。The thickness of the plated layer was measured using an optical microscope after polishing the plated surface.
比較例
上記実施例において、無電解ニッケルメッキを行なう代
わりに、２０Ａ 、４５分バレル電解メッキを行った以
外は同様にして第３図（イ）に対応する積層ＬＣチップ
部品を作製した。これについても、上記実施例と同様に
測定した結果を下記表に示す。Comparative Example A laminated LC chip component corresponding to FIG. 3(a) was prepared in the same manner as in the above example except that instead of electroless nickel plating, barrel electrolytic plating was performed at 20 A for 45 minutes. This was also measured in the same manner as in the above example, and the results are shown in the table below.
本発明によれば、積層ＬＣＣチップ品の外部電極を導電
塗膜、第２層金属メッキ層及び第３層金属メッキ層の３
層により構成するうち、第２層の例えばニッケルメッキ
を無電解メッキにより行ったので、従来のバレル電解ニ
ッケルメッキに比べて、ＬＣ回路のインダクタ（Ｌ）
と絶縁されているコンデンサ（Ｃ）の端子にもＬｍ子
と同様の厚さのメッキ層を形成することができる。これ
により、ニッケルメッキ層の厚さをどの外部電極に対し
ても一様にしてその厚さを例えば２〜３μｍに調整する
ことができる。このようにしてその薄過ぎることにより
後続のはんだメッキの際のはんだ食われを防止するとと
もに、厚過ぎることによるその上にはんだメッキ層を形
成した外部電極のストレスの発生、接着強度の低下及び
素地のクラックの発生を防止することができる。According to the present invention, the external electrodes of a laminated LCC chip product are formed by three layers: a conductive coating, a second metal plating layer, and a third metal plating layer.
Among the layers, the second layer, for example, nickel plating, is done by electroless plating, so compared to conventional barrel electrolytic nickel plating, the inductor (L) of the LC circuit is
A plating layer having the same thickness as the Lm element can also be formed on the terminal of the capacitor (C) which is insulated from the Lm element. Thereby, the thickness of the nickel plating layer can be made uniform for all external electrodes, and the thickness can be adjusted to, for example, 2 to 3 μm. In this way, if the solder is too thin, the solder is not eaten away during subsequent solder plating, and if the solder is too thick, stress is generated on the external electrode on which the solder plating layer is formed. It is possible to prevent the occurrence of cracks.
第１図（イ）（ロ）は本発明の積層ＬＣチップ部品の製
造工程の一部の説明図、第２図はその積層ＬＣチップ部
品の組立てた状態の斜視図、第３図（イ）はその完成図
、同（ロ）はその等価回路図である。
図中、１はインダクタ部、２はコンデンサ部、７．８．
９．１０は外部電極、■、■、■、■はこれら外部電極
にそれぞれ対応する回路の端子である。
平成１年１２月２Ｚ日
第１図
（イ）
（ｃｒ）
第２図
３１−Figures 1 (a) and (b) are explanatory diagrams of a part of the manufacturing process of the laminated LC chip component of the present invention, Figure 2 is a perspective view of the assembled laminated LC chip component, and Figure 3 (a) is its completed diagram, and (b) is its equivalent circuit diagram. In the figure, 1 is an inductor part, 2 is a capacitor part, 7.8.
9. 10 are external electrodes, and 2, 2, 2, and 2 are circuit terminals corresponding to these external electrodes, respectively. December 2Z, 1999 Figure 1 (a) (cr) Figure 2 31-
Claims (1)
れぞれの絶縁体基板の配線を接続してコイルを形成した
インダクタ部と、誘電体の両側に電極を形成した少なく
とも１組のコンデンサ部とを積層した積層体の外壁にＬ
Ｃ回路の外部電極を形成する積層ＬＣチップ部品の電極
形成方法において、それぞれの外部電極が形成される外
壁に導電膜を形成する工程と、この導電膜に金属無電解
メッキを施す工程と、この金属無電解メッキ層にはんだ
の電解メッキを施す工程を有することを特徴とする積層
ＬＣチップ部品の電極形成方法。(1) An inductor section in which a plurality of insulating substrates having conductor wiring are laminated and the wiring of each insulating substrate is connected to form a coil, and at least one set of capacitor sections in which electrodes are formed on both sides of the dielectric. L on the outer wall of the laminate made of
A method for forming an electrode of a laminated LC chip component that forms an external electrode of a C circuit includes a step of forming a conductive film on the outer wall on which each external electrode is formed, a step of applying metal electroless plating to the conductive film, and A method for forming electrodes of a laminated LC chip component, comprising the step of electrolytically plating a metal electroless plating layer with solder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33127289A JPH03192706A (en) | 1989-12-22 | 1989-12-22 | Formation of electrode for laminated lc chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33127289A JPH03192706A (en) | 1989-12-22 | 1989-12-22 | Formation of electrode for laminated lc chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03192706A true JPH03192706A (en) | 1991-08-22 |
Family
ID=18241838
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33127289A Pending JPH03192706A (en) | 1989-12-22 | 1989-12-22 | Formation of electrode for laminated lc chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03192706A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013084875A (en) * | 2011-10-06 | 2013-05-09 | Samsung Electro-Mechanics Co Ltd | Multilayer ceramic capacitor and method for manufacturing the same |
| US9666366B2 (en) | 2002-04-15 | 2017-05-30 | Avx Corporation | Method of making multi-layer electronic components with plated terminations |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51114672A (en) * | 1975-04-01 | 1976-10-08 | Nippon Electric Co | Small planeetype coil |
-
1989
- 1989-12-22 JP JP33127289A patent/JPH03192706A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS51114672A (en) * | 1975-04-01 | 1976-10-08 | Nippon Electric Co | Small planeetype coil |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9666366B2 (en) | 2002-04-15 | 2017-05-30 | Avx Corporation | Method of making multi-layer electronic components with plated terminations |
| US10020116B2 (en) | 2002-04-15 | 2018-07-10 | Avx Corporation | Plated terminations |
| US10366835B2 (en) | 2002-04-15 | 2019-07-30 | Avx Corporation | Plated terminations |
| US11195659B2 (en) | 2002-04-15 | 2021-12-07 | Avx Corporation | Plated terminations |
| JP2013084875A (en) * | 2011-10-06 | 2013-05-09 | Samsung Electro-Mechanics Co Ltd | Multilayer ceramic capacitor and method for manufacturing the same |
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