JPH03191572A - Optical semiconductor device - Google Patents
Optical semiconductor deviceInfo
- Publication number
- JPH03191572A JPH03191572A JP33158089A JP33158089A JPH03191572A JP H03191572 A JPH03191572 A JP H03191572A JP 33158089 A JP33158089 A JP 33158089A JP 33158089 A JP33158089 A JP 33158089A JP H03191572 A JPH03191572 A JP H03191572A
- Authority
- JP
- Japan
- Prior art keywords
- light
- emitting element
- refractive index
- index layer
- emitting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003287 optical effect Effects 0.000 title claims description 31
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 230000008054 signal transmission Effects 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 4
- 239000000463 material Substances 0.000 description 23
- 230000001681 protective effect Effects 0.000 description 10
- 229920001721 polyimide Polymers 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 239000009719 polyimide resin Substances 0.000 description 6
- 238000005304 joining Methods 0.000 description 5
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 229910015365 Au—Si Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000012777 electrically insulating material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 230000011514 reflex Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Photo Coupler, Interrupter, Optical-To-Optical Conversion Devices (AREA)
- Semiconductor Lasers (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、素子間の信号伝送に光結合を導入した光半導
体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an optical semiconductor device in which optical coupling is introduced for signal transmission between elements.
従来、電気回路間の電磁的ノイズの除去手段として、電
気信号を光信号に変換して伝送する光結合アイソレータ
（ホトカブラ）が知られている。Conventionally, as a means for removing electromagnetic noise between electric circuits, an optical coupling isolator (photocoupler) that converts an electric signal into an optical signal and transmits the optical signal is known.
これは、第８図（ａ）、 （ｂ）に示すように、発光素
子（例えばＬＥＤ）と受光素子（例えばホトダイオード
）と絶縁物を介して対面固定してパッケージ内に密封す
るものであり、プリント基板上あるいはハイブリッド基
板上に実装される。As shown in FIGS. 8(a) and 8(b), this is a device in which a light-emitting element (e.g., an LED) and a light-receiving element (e.g., a photodiode) are fixed facing each other via an insulator and sealed in a package. Mounted on a printed circuit board or hybrid board.
しかしながら、このものを高速性を要求される通信シス
テムやコンピュータ内のＩＣに適用する場合、このホト
カプラとＩ１０ボート用ＩＣ間の配線部がモノリシック
ＩＣ内の配線より長くなってしまうことから、耐ノイズ
性の確保が却って困難となってしまうという問題がある
。However, when this product is applied to a communication system that requires high speed or an IC in a computer, the wiring between this photocoupler and the I10 board IC is longer than the wiring inside the monolithic IC, so noise resistance is required. There is a problem in that securing sex becomes even more difficult.
また、例えば特開昭６３−２７１９７５号公報等には、
端面型発光素子と端面型受光素子とを光結合するように
した光電子集積回路（所謂０ＥＩＣ）が開示されている
が、このものは発光素子１つに対して受光素子を１：ｌ
に対面させる必要があり、それにより光結合構造が限定
されてしまう。Also, for example, in Japanese Patent Application Laid-Open No. 63-271975,
An optoelectronic integrated circuit (so-called 0EIC) has been disclosed in which an edge-type light emitting element and an edge-type light receiving element are optically coupled;
This limits the optical coupling structure.
すなわち、平面型発光素子・平面型受光素子からなるホ
トカブラのように出力増幅を図って受光素子アレイを構
成することができず、出力増幅をはかるためには発光素
子の電力を大きくする必要が生し、発光素子の寿命が短
縮されるなど、経済的損失が発生する。In other words, it is not possible to construct a light-receiving element array by amplifying the output like in a photocoupler consisting of a flat light-emitting element and a flat light-receiving element, and in order to amplify the output, it is necessary to increase the power of the light-emitting elements. However, economic losses occur, such as the life of the light emitting element being shortened.
本発明は、上記問題に鑑みてなされたものであり、発光
・受光素子間の電気絶縁化により耐ノイズ性を向上させ
るとともに、信号伝送の高速性が確保できるコンパクト
な光半導体装置を提供することを目的とする。The present invention has been made in view of the above problems, and an object of the present invention is to provide a compact optical semiconductor device that improves noise resistance by electrically insulating between light-emitting and light-receiving elements, and can ensure high-speed signal transmission. With the goal.
（課題を解決するための手段）
上記目的を達成するために、本発明による光半導体装置
は、
同一基板に、面発光型の平面型発光素子と、面受光型の
平面型受光素子とが、それぞれ発光面。(Means for Solving the Problems) In order to achieve the above object, an optical semiconductor device according to the present invention includes a surface-emitting planar light-emitting element and a surface-receiving planar light-receiving element on the same substrate. Each light emitting surface.
受光面を同一方向に面するようにして構成され、前記平
面型発光素子の発光面から出力する光を前記発光面と前
記受光面とが為す面に沿って前記平面型受光素子の受光
面へと導く光導波路が、前記基板上において少なくとも
前記平面型発光素子の発光面と前記平面型受光素子の受
光面とを覆着するようにして形成されていることを特徴
とする。The light receiving surface is configured to face the same direction, and the light output from the light emitting surface of the planar light emitting element is directed to the light receiving surface of the planar light receiving element along a plane formed by the light emitting surface and the light receiving surface. An optical waveguide is formed on the substrate so as to cover at least the light emitting surface of the planar light emitting element and the light receiving surface of the planar light receiving element.
以下、本発明を図に示す実施例について説明する。 DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention shown in the drawings will be described.
第１図（ａ）、 （ｂ）に本発明第１実施例の構成を示
す。FIGS. 1(a) and 1(b) show the configuration of a first embodiment of the present invention.
第１図（ａ）は本発明第１実施例の構成を示す断面図、
第１図（ｂ）はその平面図である。FIG. 1(a) is a sectional view showing the configuration of the first embodiment of the present invention,
FIG. 1(b) is a plan view thereof.
第１図（ａ）、（ハ）において、８は平面型発光素子チ
ップ１ （例えば発光ダイオードＬＥＤ）および平面型
受光素子チップ２（例えばホトダイオード）を埋め込ん
で複合集積化するためのＳｉ基板である。なお、このＳ
ｉ基板８は異方性エツチングが可能な面方位（１００）
、（１１０）等の基板を用いることが望ましい。また、
このＳｉ基板８には発光素子１の駆動回路や信号処理回
路等の電子回路が作り込まれていてもよい。In FIGS. 1(a) and 1(c), 8 is a Si substrate for embedding a flat light emitting element chip 1 (e.g. a light emitting diode LED) and a flat light receiving element chip 2 (e.g. a photodiode) for composite integration. . Furthermore, this S
The i-substrate 8 has a surface orientation (100) that allows anisotropic etching.
, (110), etc. are preferably used. Also,
Electronic circuits such as a drive circuit for the light emitting element 1 and a signal processing circuit may be built into the Si substrate 8.
さらに、このＳｉ基板８には、アルカリ溶液を用いた異
方性エツチングによりチップ１および２を埋め込むため
のテーバ状の凹部１３が形成されている。この凹部Ｉ３
の深さはチップ１．２の厚み程度とされており、該凹部
１３の底部の形状はチップ１および２の底部と同形状、
あるいは数μｍ程度大きめの形状に形成されている。チ
ップ１および２は、テーパ穴１３内に接合部材１０によ
り固定される。なお、接合部材１０は必要に応じて導電
性のものを用いてもよい。Furthermore, a tapered recess 13 for embedding the chips 1 and 2 is formed in the Si substrate 8 by anisotropic etching using an alkaline solution. This recess I3
The depth of the recess 13 is approximately the thickness of the chip 1.2, and the bottom of the recess 13 has the same shape as the bottom of the chips 1 and 2.
Alternatively, it is formed in a larger shape by several μm. Chips 1 and 2 are fixed in tapered hole 13 by joining member 10 . Note that the joining member 10 may be electrically conductive if necessary.
Ｓｉ基板８とチップ１および２の間に生じた溝１１は、
平坦化材料７により溝環めされ、それにより基板８表面
を平坦化している。The groove 11 created between the Si substrate 8 and the chips 1 and 2 is
The groove is surrounded by a flattening material 7, thereby flattening the surface of the substrate 8.
発光素子チップ１および受光素子チップ２０表面には、
例えば窒化ケイ素による保護膜１２が形成されている。On the surfaces of the light emitting element chip 1 and the light receiving element chip 20,
For example, a protective film 12 made of silicon nitride is formed.
発光素子チップ１と受光素子チップ２を光結合する光導
波路は、第１低屈折率層３と高屈折率層４およびこの３
，４を覆着する第２低屈折率層５との積層構造により形
成されている。なお、前述の保護膜１２の屈折率は光導
波層を形成する高屈折率層４の屈折率より大きいもの、
あるいは等しいものとされている。また、第１．第２低
屈折率層３，５の屈折率は中間層である高屈折率Ｎ４の
屈折率より小さいものであり、これら第１．第２低屈折
率層３，５を同材質により構成するようにしてもよい。The optical waveguide that optically couples the light emitting element chip 1 and the light receiving element chip 2 includes a first low refractive index layer 3, a high refractive index layer 4, and
, 4 and a second low refractive index layer 5 covering them. Note that the refractive index of the above-mentioned protective film 12 is greater than the refractive index of the high refractive index layer 4 forming the optical waveguide layer;
Or they are considered to be equal. Also, 1st. The refractive index of the second low refractive index layers 3 and 5 is smaller than the refractive index of the high refractive index N4 which is the intermediate layer. The second low refractive index layers 3 and 5 may be made of the same material.
表１に保護膜１２．光導波路の各層の組み合わせ例を示
す。Table 1 shows the protective film 12. Examples of combinations of each layer of an optical waveguide are shown.
（以下余白）
表
１
なお、前述の接合部材１ｏはチップ１，２とＳ基板８を
接着できるものであれば何でもよいが、配線６の材１！
４（例えばアルミニウム）に対する加熱限界温度（５０
０°Ｃ）等を考慮した素子の耐熱温度以下で処理可能で
、さらに第１．第２低屈折率Ｎ３，５、高屈折率層４、
保護膜１２等の形成温度（３５０〜４００°Ｃ）等を考
慮して、耐熱温度の高い材料、例えばポリイミド樹脂、
Ａｕ−３共晶、ハンダ等が望ましい。また、配Ｌ？ｉ
６の材質は、千ツブ１および２と基板間の電気的結合が
できるものであれば何でもよく、例えばＡｕ、Ｍ。(Margin below) Table 1 The above-mentioned bonding member 1o may be any material as long as it can bond the chips 1, 2 and the S-board 8, but the material 1 for the wiring 6!
Heating limit temperature (50
It can be processed at temperatures below the heat-resistant temperature of the element, taking into consideration factors such as 0°C), and the first. second low refractive index N3,5, high refractive index layer 4,
Considering the formation temperature (350 to 400°C) of the protective film 12, etc., materials with high heat resistance, such as polyimide resin,
Au-3 eutectic, solder, etc. are preferable. Also, distribution L? i
The material 6 may be any material as long as it allows electrical connection between the tubes 1 and 2 and the substrate, such as Au or M.
！
！
Ｗ、Ａｌ、Ｃｕ等が用いられる。また、平坦化材料７は
容易に溝１１に充填でき、電気的に絶縁性のものであれ
ばよく、例えばポリイミド樹脂のように接合部材１０と
同様の熱特性を持つものが望ましい。! ! W, Al, Cu, etc. are used. Further, the flattening material 7 may be any material as long as it can be easily filled into the groove 11 and is electrically insulating. For example, a material having the same thermal properties as the bonding member 10, such as polyimide resin, is preferable.
次に、第１図（ａ）、 （ｂ）に示す光半導体装置をそ
の製造工程に従って説明する。第２図（ａ）〜（ｅ）は
製造工程を説明するための断面図である。Next, the optical semiconductor device shown in FIGS. 1(a) and 1(b) will be explained according to its manufacturing process. FIGS. 2(a) to 2(e) are cross-sectional views for explaining the manufacturing process.
まず、第２図（ａ）に示すように必要な電子回路を作り
込んだ面方位（１００）のＳｉ基板８の主表面上の所定
領域に酸化シリコン膜（Ｓｉｎｇ）あるいは窒化シリコ
ン膜（ＳｉＮｘ）１２を形成し、所望のバターニングを
行う。これをマスクとして水酸化カリウム（ＫＯＨ）等
による異方性エツチングにより、第２図（ｂ）に示すテ
ーパ状の凹部１３を形成する。なお、ここで用いるＳｉ
基板は前述の如＜（１１０）面のものであってもよい。First, as shown in FIG. 2(a), a silicon oxide film (Sing) or a silicon nitride film (SiNx) is deposited on a predetermined area on the main surface of a Si substrate 8 with a plane orientation (100) on which necessary electronic circuits have been fabricated. 12 and perform desired patterning. Using this as a mask, anisotropic etching is performed using potassium hydroxide (KOH) or the like to form a tapered recess 13 as shown in FIG. 2(b). Note that Si used here
The substrate may have the (110) plane as described above.
また、基板８裏面から電極をとり出す場合には、不純物
を高濃度に拡散したＰ″層等を予め基板裏面に設けてお
く。Further, when an electrode is taken out from the back surface of the substrate 8, a P'' layer or the like in which impurities are diffused at a high concentration is provided on the back surface of the substrate in advance.
次に、第２図（Ｃ）にしめずように、テーパ状凹部１３
の底面に発光素子チップ１および受光素子チップ２を接
合部材１０により接着する。このときチップ１．２表面
には保護膜１２（例えばプラズマ窒化ケイ素膜）が形成
されている。なお、発光素子チップ１側の接合部材１０
′は、発光素子の電極を取り出すため、本例では導電性
のもの（例えばＡｕ−Ｓｉ共品ハンダ、導電性ポリイミ
ド等）を使用している。一方、受光素子チップ２側の接
合部材１０は、電気絶縁性のもの（ポリイミド樹脂等）
を用い、発光素子側回路と受光素子側回路とは電気的に
分離（なお、基板作り込み素子はｐｎ接合による素子分
離）されている。Next, as shown in FIG. 2(C), the tapered recess 13
A light-emitting element chip 1 and a light-receiving element chip 2 are bonded to the bottom surface of the substrate using a bonding member 10. At this time, a protective film 12 (for example, a plasma silicon nitride film) is formed on the surface of the chip 1.2. Note that the joining member 10 on the light emitting element chip 1 side
In this example, a conductive material (for example, Au-Si solder, conductive polyimide, etc.) is used in order to take out the electrode of the light emitting element. On the other hand, the bonding member 10 on the light receiving element chip 2 side is made of electrically insulating material (polyimide resin, etc.)
The circuit on the light emitting element side and the circuit on the light receiving element side are electrically separated (the elements built into the substrate are separated by a pn junction).
この後、第２図（ｄ）に示すように、埋め込んだチップ
１゜２と基板の凹部１３との間に残された溝１１を絶縁
性の平坦化材料７（例えばポリイミド樹脂等）で埋め込
み、チップ上電極９および基板上電極９′を配線６で接
続する。なお、配線６は例えばＡ！蒸着膜等のフォトリ
ソグラフィで形成するか、メツキ処理にて形成すればよ
い。After this, as shown in FIG. 2(d), the groove 11 left between the embedded chip 1゜2 and the recess 13 of the substrate is filled with an insulating flattening material 7 (for example, polyimide resin, etc.). , the electrode 9 on the chip and the electrode 9' on the substrate are connected by a wiring 6. Note that the wiring 6 is, for example, A! It may be formed by photolithography, such as a vapor deposition film, or by plating.
更に、この表面に第２図（ｅ）に示す如く光導波路を形
成する。まず、発光素子１および受光素子２上で光が入
射あるいは出射する領域を除いて、まず第１低屈折率層
３を形成する。このとき配線６の保護膜として３′を同
時に形成してもよい。第１低屈折率層３は、プラズマＣ
ＶＤ法等により、表１に示した材料を成膜した後、フォ
トリソグラフィ法により所望の形状にパターニングする
ことで形成できる。次に、この第１低屈折率１１３上に
、この第１低屈折率Ｊｉ１３よりも屈折率が大きい材料
（表１参照）により高屈折率層４を形成し、さらに、こ
の第１低屈折率層３、高屈折率層４上に第２低屈折率層
５を同様に所望の形状にして形成する。なお、このよう
に光導波路を構成した時、高屈折率層側から低屈折率層
側へ光が入射する場合、入射角が臨界角θＣ以下ならば
全反射し、方、逆の場合、全反射現象は起こらない。臨
界角θＣは次式で表される。Furthermore, an optical waveguide is formed on this surface as shown in FIG. 2(e). First, the first low refractive index layer 3 is formed on the light emitting element 1 and the light receiving element 2 except for the areas where light enters or exits. At this time, 3' may be formed as a protective film for the wiring 6 at the same time. The first low refractive index layer 3 is made of plasma C
It can be formed by forming a film of the materials shown in Table 1 using a VD method or the like, and then patterning it into a desired shape using a photolithography method. Next, on this first low refractive index 113, a high refractive index layer 4 is formed of a material having a higher refractive index than this first low refractive index Ji13 (see Table 1), and further, this first low refractive index layer 4 is A second low refractive index layer 5 is similarly formed in a desired shape on the layer 3 and the high refractive index layer 4. When the optical waveguide is configured in this way, when light is incident from the high refractive index layer side to the low refractive index layer side, if the incident angle is less than the critical angle θC, it will be totally reflected; No reflex phenomenon occurs. The critical angle θC is expressed by the following formula.
ここで、ｎｌは高屈折率層の屈折率、ｎ！は低屈折率層
の屈折率である。Here, nl is the refractive index of the high refractive index layer, and n! is the refractive index of the low refractive index layer.
効率的な光伝搬のためには、保護膜１２の屈折率ｎｐと
高屈折率層４の屈折率ｎ１の差は界面での反射が低くな
るため、小さい程よい。また、高屈折率層と低屈折率層
において、その屈折率の差は臨界角θＣが大きくなるよ
うに、大きいほどよい。For efficient light propagation, the smaller the difference between the refractive index np of the protective film 12 and the refractive index n1 of the high refractive index layer 4 is, the better, since reflection at the interface is reduced. Further, the difference in refractive index between the high refractive index layer and the low refractive index layer is preferably as large as possible so that the critical angle θC becomes large.
なお、表１に示す組み合わせ例では、θＣ＝４６．０度
、５４．９度となる。In addition, in the combination example shown in Table 1, θC=46.0 degrees and 54.9 degrees.
ここで、発光素子チンプ１からの光は発光部より指向性
が弱く、放射状に発せられているため、光導波路、すな
わち高屈折率層４への入射角は画一でなく数度〜９０度
と多岐にわたり、臨界角θＣを超えて入射する光がある
ことも考察される。臨界角θＣを超えて入射する光は、
第２低屈折率層５を通過して外部へ放出してしまうこと
になる。Here, since the light from the light emitting element chimp 1 has weaker directivity than the light emitting part and is emitted radially, the angle of incidence on the optical waveguide, that is, the high refractive index layer 4 is not uniform, but from several degrees to 90 degrees. It is also considered that there is light that enters beyond the critical angle θC. The light incident beyond the critical angle θC is
The light passes through the second low refractive index layer 5 and is emitted to the outside.
そこで、本実施例では、この第２低屈折率層５を通り抜
けた光が迷光となり、他素子特性に悪影響を及ぼす場合
や光伝搬効率が不足する場合を想定して、第２低屈折率
Ｎ５の表面上に金属反射膜１４を形成している。この金
属反射膜１４はアルミ蒸着膜にて形成するようにすれば
よい。Therefore, in this embodiment, the second low refractive index layer N5 A metal reflective film 14 is formed on the surface. This metal reflective film 14 may be formed of an aluminum vapor-deposited film.
以上のように構成することにより、発光素子１から発せ
られた光を、高屈折率１１４と第１および第２低屈折率
層３，５の界面で反射を繰り返しさせながら、高屈折率
層４内を通って受光素子２へと至るように光結合させた
光半導体装置が製造される。ここで、高屈折率層４と第
１、第２低屈折率Ｎ３，５からなる光導波路はモノリシ
ックに形成され、光透過性材料のパターニングという非
常に簡単な工程で形成できる。さらに、本例による光半
導体装置はプレーナ形であり、モノリシック並の高密度
集積が可能であるため、これを各種電子回路の入出力部
と結合すべく形成すれば、耐ノイズ特性に優れたものを
コンパクトに実現できる。With the above configuration, the light emitted from the light emitting element 1 is repeatedly reflected at the interface between the high refractive index 114 and the first and second low refractive index layers 3 and 5, while the high refractive index layer 4 An optical semiconductor device that is optically coupled to the light-receiving element 2 through the inside is manufactured. Here, the optical waveguide consisting of the high refractive index layer 4 and the first and second low refractive index layers N3 and 5 is formed monolithically, and can be formed by a very simple process of patterning a light-transmitting material. Furthermore, since the optical semiconductor device according to this example is planar and can be integrated at a high density comparable to that of a monolith, if it is formed to be connected to the input/output section of various electronic circuits, it will have excellent noise resistance characteristics. can be realized compactly.
さらに、本例によれば、金属反射膜１４により光を密閉
するようにしているため、他信号回路への迷光の心配が
なく、信号ラインの多チャネル化にも容易に対応可能で
ある。Furthermore, according to this example, since the metal reflective film 14 seals the light, there is no worry of stray light entering other signal circuits, and it is possible to easily accommodate multi-channel signal lines.
次に、本発明第２実施例について説明する。Next, a second embodiment of the present invention will be described.
上記第１実施例では発光素子ｌおよび受光素子をチップ
状態で基板８に埋め込むようにして集積化するものであ
ったが、これら各素子のうち少なくとも一方が予め基板
８に作り込まれているようにしたものであってもよい。In the first embodiment, the light-emitting element l and the light-receiving element are integrated by being embedded in the substrate 8 in the form of a chip. It may also be a
−例として、受光素子２が基板８内に作り込まれている
ものを第３図（ａ）、 （ｂ）に示す。- As an example, FIGS. 3(a) and 3(b) show an example in which the light receiving element 2 is built into the substrate 8.
また、上記第１実施例では光を屈折率の差により全反射
させて導波するものであったが、第３図（ａ）、 （ｂ
）に示すものは、光反射膜により光を光透過材料の中に
閉じ込めて伝送するものである。以下、第３図（ａ）、
（ｂ）に示すものの光導波路の構成例について説明す
る。第３図（ａ）、 （ｂ）において、３′および５′
は光反射膜を形成する金属膜であり、例えば、１１蒸着
膜（反射率９０％以上）にて形成されている。また、４
′は無機材膜あるいは透光性ポリイミド樹脂膜等の光透
過材料よりなる光導波層であり、望ましくは発光素子チ
ップ１、基板８の保護膜１２と近似の屈折率をもつ光透
過材料より構成される。また、１５は同じく光透過性の
絶縁膜で、保護膜１２と同じ材質であっても、さらには
基板８の保護膜１２と同時に形成するようにしてもよい
。Furthermore, in the first embodiment, the light is guided by total reflection due to the difference in refractive index;
) is one in which light is transmitted by confining it in a light-transmitting material using a light-reflecting film. Below, Figure 3(a),
An example of the configuration of the optical waveguide shown in (b) will be explained. In Figures 3(a) and (b), 3' and 5'
is a metal film forming a light reflecting film, and is formed of, for example, a 11 vapor deposited film (reflectance of 90% or more). Also, 4
′ is an optical waveguide layer made of a light-transmitting material such as an inorganic film or a transparent polyimide resin film, preferably made of a light-transmitting material having a refractive index similar to that of the protective film 12 of the light emitting element chip 1 and the substrate 8. be done. Further, 15 is a light-transmissive insulating film, which may be made of the same material as the protective film 12, or may be formed simultaneously with the protective film 12 of the substrate 8.
なお、上記第３図（ａ）、 （ｂ）に示すものは、先導
波層４′中を上下に形成された光反射膜３’、５’の金
属面での反射を用いて光を伝送するものであるが、金属
面で反射する際に若干の光吸収があり、光伝搬効率は上
記第１実施例のものに比べやや劣るが、発光・受光素子
１． ２間距離が数鴫程度であれば問題はない。Note that the devices shown in FIGS. 3(a) and 3(b) transmit light by using reflection on the metal surfaces of light reflecting films 3' and 5' formed above and below in the leading wave layer 4'. However, there is some light absorption when reflected by the metal surface, and the light propagation efficiency is slightly inferior to that of the first embodiment. There is no problem if the distance between the two is about a few feet.
次に、本発明第３実施例を第４図に示す。上記第１、第
２実施例では発光素子ｌと受光素子２の電気的分離を半
導体のｐ−ｎ接合で行っている。Next, a third embodiment of the present invention is shown in FIG. In the first and second embodiments described above, the light emitting element 1 and the light receiving element 2 are electrically separated by a semiconductor pn junction.
しかしながら、その場合、高耐圧の絶縁が困難であるた
め、本第３実施例では第４図に示すようにｐ゛のＳｉ基
板８ａとＳｔ基板８とをＳｔｏｗ膜１６を介して直接接
合して、発光素子チップ１裏面の発光素子の電極部とな
る導電性接合部材１０′領域を除いたＳｏｌ基板により
高耐圧化を実現している。However, in that case, it is difficult to insulate with high voltage resistance, so in the third embodiment, as shown in FIG. A high withstand voltage is achieved by using the Sol substrate excluding the region of the conductive bonding member 10' which becomes the electrode part of the light emitting element on the back surface of the light emitting element chip 1.
また、基板８に埋め込む半導体チップは、上記種々の実
施例においては発光素子あるいは受光素子単体のチップ
であったが、これら各素子の他に信号処理回路等の周辺
回路が作り込まれたチップであってもよい。第５図には
、本発明第４実施例として、受光素子側の半導体チップ
２′が、受光素子と周辺回路とが作り込まれたものであ
る例を示す。Further, the semiconductor chip embedded in the substrate 8 is a chip with a single light emitting element or a light receiving element in the various embodiments described above, but it is also a chip in which a peripheral circuit such as a signal processing circuit is built in addition to each of these elements. There may be. FIG. 5 shows a fourth embodiment of the present invention in which a semiconductor chip 2' on the light receiving element side has a light receiving element and a peripheral circuit built therein.
また、上記種々の実施例ではＳｉ基板８内へ半導体チッ
プを埋め込んで集積化するものであったが、第６図の本
発明第５実施例に示すように、平板状のＳｉ基板８上に
発光素子１、受光素子２等の各半導体チップを敷きつめ
るようにして集積化してもよく、このものは上記種々の
実施例よりも高密度に集積可能である。なお、この場合
、光導波路を構成する前に、半導体チップ間溝をポリイ
ミド樹脂等の平坦化材料により平坦化するようにしてお
くとよい。半導体チップ間は、平坦化材料の有する表面
張力により良好に平坦化材料を架けることができ、容易
に平坦化することができる。In addition, in the various embodiments described above, semiconductor chips were integrated by embedding them in the Si substrate 8, but as shown in the fifth embodiment of the present invention shown in FIG. The semiconductor chips such as the light-emitting element 1 and the light-receiving element 2 may be integrated by laying them one on top of the other, and this can be integrated at a higher density than in the various embodiments described above. In this case, it is preferable to flatten the groove between the semiconductor chips with a flattening material such as polyimide resin before constructing the optical waveguide. The surface tension of the planarization material allows the planarization material to be satisfactorily spread between the semiconductor chips, and the semiconductor chips can be easily planarized.
次に、本発明第６実施例を第７図（ａ）、 （ｂ）を用
いて説明する。第７図（ａ）は本発明第６実施例の断面
図、同図（ｂ）はその平面図である。上記種々の実施例
では、発光素子と受光素子を１：１に光結合するもので
あったが、本例は受光素子をアレイ状に配列するように
したものである。これは、受光素子２からの起電圧が一
つの受光素子だけでは不足する場合に対応したものであ
り、一つの発光素子１と複数の受光素子２を光結合させ
て、各々の受光素子２を配線６により直列接続しており
、起電圧の増幅を実現することができる。また、受光素
子とアレイ状に配列しても、基板上に構成された光導波
路はモノリシックに形成されているので、高密度に集積
可能であり、また、アレイを構成する光導波路も光透過
材料のパターニングで形成できるため、製造工程が複雑
化することもない。Next, a sixth embodiment of the present invention will be explained using FIGS. 7(a) and 7(b). FIG. 7(a) is a sectional view of a sixth embodiment of the present invention, and FIG. 7(b) is a plan view thereof. In the various embodiments described above, the light-emitting element and the light-receiving element are optically coupled in a 1:1 ratio, but in this example, the light-receiving elements are arranged in an array. This corresponds to the case where the electromotive force from the light receiving element 2 is insufficient for only one light receiving element, and one light emitting element 1 and a plurality of light receiving elements 2 are optically coupled to each other. They are connected in series through wiring 6, and can amplify the electromotive voltage. Furthermore, even when arranged in an array with photodetectors, the optical waveguides configured on the substrate are monolithically formed, so they can be integrated at high density, and the optical waveguides that make up the array can also be made of light-transmitting material Since it can be formed by patterning, the manufacturing process does not become complicated.
以上詳述したように、本発明による光半導体装置は、平
面型発光素子と平面型受光素子とを同一基板に構成し、
発光素子から出力された光を導く光導波路を、これら発
光・受光素子あるいは基板上に沿って受光素子に結合す
べく形成されているために、発光・受光素子間の電気絶
縁化により耐ノイズ性を向上させるとともに、信号伝送
の高速性が確保でき、しかもコンパクトに形成できると
いう優れた効果がある。As detailed above, the optical semiconductor device according to the present invention includes a planar light emitting element and a planar light receiving element on the same substrate,
Since the optical waveguide that guides the light output from the light emitting element is formed to couple to the light emitting/receiving element or the light receiving element along the substrate, noise resistance is improved by electrically insulating the light emitting/receiving element. It has the excellent effect of improving speed, ensuring high-speed signal transmission, and being able to be formed compactly.
第１図（ａ）、 （ｂ）はそれぞれ本発明第１実施例の
断面図、平面図、第２図（ａ）〜（ｅ）は本発明第１実
施例の製造工程順の断面図、第３図（ａ）、■）はそれ
ぞれ本発明第２実施例の断面図、平面図、第４図は本発
明第３実施例の断面図、第５図は本発明第４実施例の断
面図、第６図は本発明第５実施例の断面図、第７図（ａ
）、 （ｂ）はそれぞれ本発明第６実施例の断面図、平
面図、第８図（ａ）、 （ｂ）は従来の光結合アイソレ
ータの構造を示す斜視図、断面図である。
ｌ・・・発光素子、２・・・受光素子、３・・・第１低
屈折率層、３′・・・光反射膜、４・・・高屈折率層、
４′・・・光導波層、５・・・第２低屈折率層、５′・
・・光反射膜。
６・・・配線、７・・・平坦化材料、８．８ａ・・・Ｓ
ｔ基板。
ｌＯ・・・絶縁性接合部材、１０’・・・導電性接合部
材。
１３・・・凹部、１６・・・Ｓｉｎ、膜。FIGS. 1(a) and 1(b) are a sectional view and a plan view of the first embodiment of the present invention, respectively, and FIGS. 2(a) to (e) are sectional views of the first embodiment of the present invention in the order of manufacturing steps. 3(a) and ■) are a cross-sectional view and a plan view of the second embodiment of the present invention, FIG. 4 is a cross-sectional view of the third embodiment of the present invention, and FIG. 5 is a cross-sectional view of the fourth embodiment of the present invention. Figure 6 is a sectional view of the fifth embodiment of the present invention, and Figure 7 (a
) and (b) are a cross-sectional view and a plan view of the sixth embodiment of the present invention, respectively, and FIGS. 8(a) and (b) are a perspective view and a cross-sectional view showing the structure of a conventional optical coupling isolator. l... Light emitting element, 2... Light receiving element, 3... First low refractive index layer, 3'... Light reflecting film, 4... High refractive index layer,
4'... Optical waveguide layer, 5... Second low refractive index layer, 5'...
...Light reflective film. 6... Wiring, 7... Flattening material, 8.8a...S
t board. 10: Insulating joining member, 10': Conductive joining member. 13... Concavity, 16... Sin, film.
Claims (1)
の平面型受光素子とが、それぞれ発光面、受光面を同一
方向に面するようにして構成され、前記平面型発光素子
の発光面から出力する光を前記発光面と前記受光面とが
為す面に沿って前記平面型受光素子の受光面へと導く光
導波路が、前記基板上において少なくとも前記平面型発
光素子の発光面と前記平面型受光素子の受光面とを覆着
するようにして形成されていることを特徴とする光半導
体装置。A surface-emitting planar light-emitting element and a surface-receiving planar light-receiving element are configured on the same substrate with their light-emitting and light-receiving surfaces facing in the same direction, and the light-emitting element of the planar light-emitting element An optical waveguide that guides light output from a surface to a light-receiving surface of the planar light-receiving element along a plane formed by the light-emitting surface and the light-receiving surface is provided on the substrate at least between the light-emitting surface of the planar light-emitting element and the light-receiving surface of the planar light-receiving element. An optical semiconductor device characterized in that it is formed so as to cover a light-receiving surface of a flat type light-receiving element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33158089A JPH03191572A (en) | 1989-12-21 | 1989-12-21 | Optical semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33158089A JPH03191572A (en) | 1989-12-21 | 1989-12-21 | Optical semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03191572A true JPH03191572A (en) | 1991-08-21 |
Family
ID=18245243
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33158089A Pending JPH03191572A (en) | 1989-12-21 | 1989-12-21 | Optical semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03191572A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06232126A (en) * | 1993-02-03 | 1994-08-19 | Nippon Telegr & Teleph Corp <Ntt> | Composite semiconductor circuit device and manufacture thereof |
| US5438210A (en) * | 1993-10-22 | 1995-08-01 | Worley; Eugene R. | Optical isolation connections using integrated circuit techniques |
| JP2005327808A (en) * | 2004-05-12 | 2005-11-24 | Tohoku Univ | Semiconductor device |
| JP2008170776A (en) * | 2007-01-12 | 2008-07-24 | Fujikura Ltd | Optical transmitter-receiver |
| WO2008093880A1 (en) * | 2007-02-02 | 2008-08-07 | Sanyo Electric Co., Ltd. | Semiconductor device and method for manufacturing the same |
| WO2008123020A1 (en) * | 2007-03-09 | 2008-10-16 | Sanyo Electric Co., Ltd. | Semiconductor device and method for manufacturing the same |
| CN114460683A (en) * | 2020-11-10 | 2022-05-10 | 中国科学院半导体研究所 | Microwave photon on-chip system based on optical core particles |
-
1989
- 1989-12-21 JP JP33158089A patent/JPH03191572A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06232126A (en) * | 1993-02-03 | 1994-08-19 | Nippon Telegr & Teleph Corp <Ntt> | Composite semiconductor circuit device and manufacture thereof |
| US5438210A (en) * | 1993-10-22 | 1995-08-01 | Worley; Eugene R. | Optical isolation connections using integrated circuit techniques |
| JP2005327808A (en) * | 2004-05-12 | 2005-11-24 | Tohoku Univ | Semiconductor device |
| JP2008170776A (en) * | 2007-01-12 | 2008-07-24 | Fujikura Ltd | Optical transmitter-receiver |
| WO2008093880A1 (en) * | 2007-02-02 | 2008-08-07 | Sanyo Electric Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US8188497B2 (en) | 2007-02-02 | 2012-05-29 | Sanyo Semiconductor Co., Ltd. | Semiconductor device and method of manufacturing the same |
| JP5295783B2 (en) * | 2007-02-02 | 2013-09-18 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | Semiconductor device |
| WO2008123020A1 (en) * | 2007-03-09 | 2008-10-16 | Sanyo Electric Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US7855425B2 (en) | 2007-03-09 | 2010-12-21 | Sanyo Electric Co., Ltd. | Semiconductor device and method of manufacturing the same |
| CN114460683A (en) * | 2020-11-10 | 2022-05-10 | 中国科学院半导体研究所 | Microwave photon on-chip system based on optical core particles |
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