JPH031912B2 - - Google Patents
Info
- Publication number
- JPH031912B2 JPH031912B2 JP55172855A JP17285580A JPH031912B2 JP H031912 B2 JPH031912 B2 JP H031912B2 JP 55172855 A JP55172855 A JP 55172855A JP 17285580 A JP17285580 A JP 17285580A JP H031912 B2 JPH031912 B2 JP H031912B2
- Authority
- JP
- Japan
- Prior art keywords
- current
- base
- transistor
- collector
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000003321 amplification Effects 0.000 claims description 4
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 7
- 230000007257 malfunction Effects 0.000 description 2
Landscapes
- Electronic Switches (AREA)
- Amplifiers (AREA)
- Rectifiers (AREA)
- Control Of Electrical Variables (AREA)
Description
【発明の詳細な説明】
本発明は入力電流の一方向にのみ応じて電流を
出力する整流回路の入力電流符号を出力する符号
出力付整流回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a rectifier circuit with a sign output that outputs the sign of an input current of a rectifier circuit that outputs a current in response to only one direction of an input current.
整流回路は第１図ａの様な入出力特性を呈す
る。第１図ｂは入力電流の方向に応じた出力の有
無を示す符号出力の特性である。 The rectifier circuit exhibits input/output characteristics as shown in FIG. 1a. FIG. 1b shows the sign output characteristic indicating the presence or absence of output depending on the direction of input current.
第２図はカレントミラー回路を用いた符号出力
付整流回路の従来例である。同図において、１は
電流入力端子、２は電流出力端子、３は符号出力
端子、４は電源端子、５，６，７はPNP型のト
ランジスタでベース同志およびエミツタ同志がそ
れぞれ共通接続され、カレントミラー回路を構成
している。トランジスタ７のコレクタはエミツタ
接地されたNPN型のトランジスタ８のベースと、
一端が接地された抵抗９の両方に接続されてい
る。 FIG. 2 shows a conventional example of a rectifier circuit with sign output using a current mirror circuit. In the figure, 1 is a current input terminal, 2 is a current output terminal, 3 is a sign output terminal, 4 is a power supply terminal, 5, 6, and 7 are PNP type transistors whose bases and emitters are connected in common, and the current It constitutes a mirror circuit. The collector of transistor 7 is connected to the base of NPN type transistor 8 whose emitter is grounded.
It is connected to both of the resistors 9, one end of which is grounded.
出力電流I2は、トランジスタ５および６のカレ
ントミラー動作により、入力電流I1が第１図に示
す方向の時にのみ流れ、第３図ａに示すようにI2
∝A1の関係を保つ。トランジスタ７のコレクタ
電流I7もI7∝I1であるが、抵抗９の両端電圧がト
ランジスタ８をオンさせる値になるまで電流I3は
流れない。即ち第３図ｂに示すように、I3とI1と
の関係にはI0だけの不感部分が存在する。I0を小
さくするためには抵抗９を大きくするか、或は接
続しないかであるが、トランジスタ７のリーク電
流によつてトランジスタ８が誤動作しない必要が
ある。したがつて、I0はあまり小さくできない。 Due to the current mirror operation of transistors 5 and 6, the output current I 2 flows only when the input current I 1 is in the direction shown in FIG. 1, and the output current I 2 flows as shown in FIG.
∝A Maintain the relationship of 1 . Although the collector current I 7 of the transistor 7 is also I 7 ∝I 1 , the current I 3 does not flow until the voltage across the resistor 9 reaches a value that turns on the transistor 8 . That is, as shown in FIG. 3b, there is an insensitive portion of I 0 in the relationship between I 3 and I 1 . In order to reduce I 0 , the resistor 9 should be made larger or not connected, but it is necessary that the transistor 8 not malfunction due to the leakage current of the transistor 7 . Therefore, I 0 cannot be made very small.
本発明は上記欠点をなくすべくなされたもの
で、以下、図面を参照して説明する。 The present invention has been made to eliminate the above-mentioned drawbacks, and will be described below with reference to the drawings.
第４図は本発明の一実施例の回路構成図を示
す。同図において、PNP型のトランジスタ５お
よび６はベース同志およびエミツタ同志がそれぞ
れ共通接続され、トランジスタ５のベースとコレ
クタも直接接続されてカレントミラー回路を構成
している。PNP型のトランジスタ１１のベース
はカレントミラー回路の共通ミエツタに接続さ
れ、エミツタは電源端子４に接続され、コレクタ
は出力端子１０に接続されている。 FIG. 4 shows a circuit diagram of an embodiment of the present invention. In the figure, the bases and emitters of PNP type transistors 5 and 6 are connected in common, and the base and collector of transistor 5 are also directly connected to form a current mirror circuit. The base of the PNP type transistor 11 is connected to the common emitter of the current mirror circuit, the emitter is connected to the power supply terminal 4, and the collector is connected to the output terminal 10.
入力端子１の入力電流I1が流出する方向の場
合、カレントミラー動作によつてI1∝I2となり、
第５図のI2のような特性を呈する。また、入力電
流I1が流入する方向の場合はカレントミラー動作
せず、I2＝Ｏとなる。I2＞Ｏのとき、カレントミ
ラー回路のエミツタ側の全電流は（I1＋I2）とな
り、これはトランジスタ１１のベース電流とな
る。従つて、トランジスタ１１のコレクタ電流
I10は、I10＝（I1＋I2）×hFE（ただし、hFEはトランジ
スタ１１の電流増幅率）となり、第５図にI10で
示す様になる。したがつて、I10がIthに達する入
力電流はI0′となつて、I2＝Ithとなる時の入力電流
I0の約１／2hFEとなり、不感部分が極めて小さくな
る。 When the input current I 1 of input terminal 1 is in the outflow direction, I 1 ∝I 2 due to current mirror operation,
It exhibits characteristics like I 2 in FIG. Furthermore, when the input current I 1 is in the direction of inflow, the current mirror does not operate and I 2 =O. When I 2 >O, the total current on the emitter side of the current mirror circuit is (I 1 +I 2 ), which becomes the base current of the transistor 11. Therefore, the collector current of transistor 11
I 10 becomes I 10 =(I 1 +I 2 )×h FE (where h FE is the current amplification factor of the transistor 11), as shown by I 10 in FIG. 5. Therefore, the input current when I 10 reaches I th becomes I 0 ', and the input current when I 2 = I th
The result is approximately 1/2h FE of I 0 , and the insensitive area becomes extremely small.
第６図は本発明の他の実施例であり、トランジ
スタ１１のコレクタがエミツタ接地型トランジス
タ８のベース、および一端が接地された抵抗９に
接地され、トランジスタ８のコレクタが出力端子
３に接続されている。I1，I2，I10の関係は先の実
施例と同様である。I10による抵抗９の両端の電
圧がトランジスタ８をオンさせる電圧に達する時
のI1の値は前述した如く十分小さいため、出力電
流I3は第７図に示す様になる。また、トランジス
タ１１のコレクタにリーク電流が流れた場合でも
抵抗９があるため誤動作しないことは明らかであ
る。 FIG. 6 shows another embodiment of the present invention, in which the collector of the transistor 11 is grounded to the base of a common emitter transistor 8 and a resistor 9 whose one end is grounded, and the collector of the transistor 8 is connected to the output terminal 3. ing. The relationship among I 1 , I 2 , and I 10 is the same as in the previous embodiment. Since the value of I 1 when the voltage across the resistor 9 due to I 10 reaches the voltage that turns on the transistor 8 is sufficiently small as described above, the output current I 3 becomes as shown in FIG. Furthermore, it is clear that even if a leakage current flows through the collector of the transistor 11, malfunction will not occur because of the presence of the resistor 9.
以上に述べた如く、本発明は素子数を増加させ
ることなく、入力電流の符号出力に対する不感部
分を極めて小さくすることができる符号出力付整
流回路を実現し得るものであり、その効果は極め
て大きいものがある。 As described above, the present invention makes it possible to realize a rectifier circuit with a sign output that can extremely reduce the insensitive part to the sign output of the input current without increasing the number of elements, and the effect is extremely large. There is something.
なお、本発明の実施例において、トランジスタ
の導電型を全て逆にしても、あるいは、他の構成
のカレントミラー回路を使用しても同様に実施で
き、本発明に含まれることはいうまでもない。 Note that in the embodiments of the present invention, the conductivity types of all transistors may be reversed, or a current mirror circuit with a different configuration may be used, and the same implementation is possible, and it goes without saying that this is included in the present invention. .
第１図ａ，ｂは整流回路特性図、第２図は従来
例の回路構成図、第３図ａ，ｂは従来例の入出力
特性図、第４図は本発明の一実施例の回路構成
図、第５図は同実施例の特性図、第６図は本発明
の他の実施例の回路構成図、第７図は第６図の回
路の特性図である。
１……入力端子、２，３……出力端子、４……
電源端子、５，６，７，８，１１……トランジス
タ。
Figures 1a and b are rectifier circuit characteristic diagrams, Figure 2 is a circuit configuration diagram of a conventional example, Figure 3 a and b are input/output characteristic diagrams of a conventional example, and Figure 4 is a circuit of an embodiment of the present invention. 5 is a characteristic diagram of the same embodiment, FIG. 6 is a circuit diagram of another embodiment of the present invention, and FIG. 7 is a characteristic diagram of the circuit of FIG. 6. 1...Input terminal, 2, 3...Output terminal, 4...
Power supply terminal, 5, 6, 7, 8, 11...transistor.
Claims (1)
れ入力電流の一方向にのみ応じて前記入力電流と
比例し反対方向の電流を出力するカレントミラー
回路と、前記カレントミラー回路の共通エミツタ
側の全電流がベース電流となるように前記カレン
トミラー回路の前記共通エミツタ側にベースが接
続され、エミツタが接地もしくは電源に接続さ
れ、コレクタが前記入力電流の符号を出力する符
号出力発生手段に接続された電流増幅トランジス
タを具備してなることを特徴とする符号出力付整
流回路。 ２ 符号出力発生手段は電流増幅トランジスタと
は逆の導伝型のトランジスタで構成され、前記電
流増幅トランジスタのコレクタ電流がベース電流
となるようにベースが接続され、エミツタが電源
もしくは接地され、ベース・エミツタ間に抵抗が
接続され、コレクタ電流を入力電流の符号出力信
号とすることを特徴とする特許請求の範囲第１項
記載の符号出力付整流回路。[Scope of Claims] 1. A current mirror circuit that is composed of at least two or more transistors and outputs a current in the opposite direction in proportion to the input current in response to only one direction of the input current, and a common emitter of the current mirror circuit. A base is connected to the common emitter side of the current mirror circuit so that the entire current on the side becomes the base current, the emitter is connected to ground or a power supply, and the collector is a sign output generating means for outputting the sign of the input current. A rectifier circuit with a sign output, comprising a current amplification transistor connected to the rectifier circuit. 2. The sign output generation means is composed of a transistor of a conductivity type opposite to that of the current amplification transistor, the base is connected so that the collector current of the current amplification transistor becomes the base current, the emitter is connected to the power supply or grounded, and the base 2. The rectifier circuit with sign output according to claim 1, wherein a resistor is connected between the emitters and the collector current is used as a sign output signal of the input current.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55172855A JPS5797211A (en) | 1980-12-08 | 1980-12-08 | Rectifying circuit with coding output |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55172855A JPS5797211A (en) | 1980-12-08 | 1980-12-08 | Rectifying circuit with coding output |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5797211A JPS5797211A (en) | 1982-06-16 |
| JPH031912B2 true JPH031912B2 (en) | 1991-01-11 |
Family
ID=15949539
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55172855A Granted JPS5797211A (en) | 1980-12-08 | 1980-12-08 | Rectifying circuit with coding output |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5797211A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0824255B2 (en) * | 1987-01-14 | 1996-03-06 | 日本電気アイシーマイコンシステム 株式会社 | Switch circuit |
| JPH02105089A (en) * | 1988-10-14 | 1990-04-17 | Toshiba Corp | Switch circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4939213A (en) * | 1972-08-24 | 1974-04-12 |
-
1980
- 1980-12-08 JP JP55172855A patent/JPS5797211A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4939213A (en) * | 1972-08-24 | 1974-04-12 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5797211A (en) | 1982-06-16 |
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