JPH03183178A - Joining method of semiconductor laser - Google Patents
Joining method of semiconductor laserInfo
- Publication number
- JPH03183178A JPH03183178A JP32188389A JP32188389A JPH03183178A JP H03183178 A JPH03183178 A JP H03183178A JP 32188389 A JP32188389 A JP 32188389A JP 32188389 A JP32188389 A JP 32188389A JP H03183178 A JPH03183178 A JP H03183178A
- Authority
- JP
- Japan
- Prior art keywords
- layers
- layer
- chip
- widths
- submount
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 11
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 229910000679 solder Inorganic materials 0.000 claims abstract description 15
- 230000004888 barrier function Effects 0.000 claims abstract description 13
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 8
- 239000000956 alloy Substances 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 6
- 229910052751 metal Inorganic materials 0.000 claims abstract description 6
- 230000017525 heat dissipation Effects 0.000 claims description 10
- 239000006023 eutectic alloy Substances 0.000 abstract description 5
- 229910052718 tin Inorganic materials 0.000 abstract description 4
- 229910052737 gold Inorganic materials 0.000 abstract description 2
- 230000008020 evaporation Effects 0.000 abstract 3
- 238000001704 evaporation Methods 0.000 abstract 3
- 230000005855 radiation Effects 0.000 abstract 2
- 238000007740 vapor deposition Methods 0.000 description 8
- 239000008188 pellet Substances 0.000 description 5
- 238000005201 scrubbing Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
Landscapes
- Semiconductor Lasers (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体レーザの半田接合方法に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for soldering semiconductor lasers.
第２図は従来の半導体レーザの接合方法を示す断面図で
ある。図にかいて、（１）は半導体レーザチップＣ以下
ＬＤチップと称す）、伐）はＬＤチップ（１）の裏面電
極で、最表面Ａｕ層で形成されている。FIG. 2 is a cross-sectional view showing a conventional semiconductor laser bonding method. In the figure, (1) is a semiconductor laser chip (hereinafter referred to as LD chip), and (1) is a back electrode of the LD chip (1), which is formed of an Au layer on the outermost surface.
（３）はＡｕ８ｎ半田ペレツトで、ｓｒｌが２０％（Ｗ
ｔ＊）のもの、（４）はサブマウント、（５）はサブマ
ウント（４）の主面及び裏面に形成された最表面Ａｕ層
より成るバリヤ層、（６）は放熱用ブロックで、仕上げ
はＡｕめつき層より成るっ
次に動作について説明する。ＬＤチップ（１）はｌｉ！
装状態に於いて議事領域からの発光以外は熱に変換され
かなりの高温状態になり、この熱によりレーザ特性が低
下する。従って、−収約には熱伝導の高い金属ブロック
に載置されるが、熱膨張 の差に起因して寿命特性が
悪くなることから、ＬＤチップ（１）はサブマウント（
４）を介して放熱用ブロック（６）に載置される。接着
は、従来、信頼性（特にヒートサイク〃特性）の高いＡ
ｕＳｎ （Ｓｒ＋２０Ｉｖｗｔ％）半田を用いて行って
いた。サブマウント（４）の主面（ＬＤチップ（１）が
載置される側）に、Ａｕ５ＬＩＴペレツト（３）を仮付
し、ＬＤチップ（１）をスクラブして、ＬＤチップ（１
）の裏面に形成された最表面Ａｕ層より成る裏面型！Ｍ
（２）とサブマウント（４）の主面に形成された最表面
Ａｕ層より成るバリヤ層との間で合金接着を行っていた
。次に、放熱用ブロック（６）の上に、同様にＡｕＳｎ
ベレット（３）を仮付し、ＬＤチップ（１）が接着され
たサブマウント（４）をスクラブし、サブマウント（４
）の裏面に形成された最表面Ａｕ層より成るバリヤ層（
５）と最表面仕上げＡｕ層より成る放熱用ブロック（６
）との間で合金接着を行なっていた。(3) is an Au8n solder pellet with an srl of 20% (W
t*), (4) is the submount, (5) is the barrier layer consisting of the outermost Au layer formed on the main surface and back surface of the submount (4), (6) is the heat dissipation block, and is finished. The operation of the layer made of Au plated layer will be explained below. LD chip (1) is li!
In the installed state, all light emitted from the discussion area is converted into heat, resulting in a considerably high temperature state, and this heat deteriorates the laser characteristics. Therefore, the LD chip (1) is mounted on a metal block with high thermal conductivity, but the life characteristics deteriorate due to the difference in thermal expansion, so the LD chip (1) is mounted on a submount (
4) and placed on the heat dissipation block (6). Adhesion has traditionally been achieved using A, which has high reliability (especially heat cycle characteristics).
This was done using uSn (Sr+20Ivwt%) solder. Temporarily attach the Au5LIT pellet (3) to the main surface of the submount (4) (the side on which the LD chip (1) is placed), scrub the LD chip (1), and remove the LD chip (1).
) is a back type consisting of the outermost Au layer formed on the back side! M
(2) and a barrier layer made of the outermost Au layer formed on the main surface of the submount (4), alloy adhesion was performed. Next, on top of the heat dissipation block (6), AuSn
Temporarily attach the pellet (3), scrub the submount (4) to which the LD chip (1) is attached, and then
A barrier layer consisting of the outermost Au layer formed on the back surface of the
5) and a heat dissipation block (6) consisting of a top-finished Au layer.
) was used for alloy bonding.
〔発明が解決しようとする１１題Ｊ
従来の半導体レーザ装置の接合方法は以上のように構成
されていたので、作業者が限矯されると共に、ＡｕＳｎ
半田ベレットを供給して接着する場合に、Ａｕ８口半田
ベレットの表面に形成された酸化膜を除去する為にスク
ラブ作業を必要とし、量産する上でネックとなり、特に
ＡｕＳｎ合金中の鋤はエントロピーが高く、酸化膜を除
去する為のスクラブ作業を避けられないなどの問題点が
あった。[11 Problems to be Solved by the Invention J Since the conventional bonding method for semiconductor laser devices is configured as described above, the number of workers is limited and the number of AuSn
When supplying and bonding solder pellets, scrubbing is required to remove the oxide film formed on the surface of the 8-hole Au solder pellet, which is a bottleneck in mass production. There were problems such as the high cost and the unavoidable scrubbing work to remove the oxide film.
この発明は上記のような問題点を解消するためになされ
たもので、半田供給及びスクラブ作業を不要にした信頼
性の高い半導体レーザの接合方法を得ることを目的とす
る。The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a highly reliable semiconductor laser bonding method that eliminates the need for solder supply and scrubbing operations.
第１の発明に係る半導体レーザの接合方法は、サブマウ
ントの主面（ＬＤチップが接着する面）及び裏面の最表
面に、Ａｕ層とＳｎ層を交互にあるピッチで（Ｓｎ層の
幅をＷｌ、Ａｕ層の幅をＷ２とした場合、 Ｗ２＝１，
５ＸＷＩ ）蒸着により形成し、半田溶融時にＡｕＳｎ
合金半田（８０２０％：ｗｔ％）を形成して接着したも
のである。The method for bonding a semiconductor laser according to the first invention is to form Au layers and Sn layers alternately at a certain pitch (the width of the Sn layer is When Wl and the width of the Au layer are W2, W2=1,
5XWI) formed by vapor deposition, and AuSn is formed during solder melting.
Alloy solder (8020%:wt%) was formed and bonded.
〔作用］
この発明にかける半導体レーザの接合方法は、サブマウ
ントの主面及び裏面に各々Ａｕ層とＳｎ層が交互に形成
されている為、半田溶融時に８０層の中にＡｕ、１１１
が拡散しｓ Ａｕ８ｎの合金半田が形成されると共に、
金属の幅Ｗ２＝１．５Ｘ（Ｓｎ層の幅Ｗｌ）としている
事で、信頼性の高いＡｕＳｎ合金半田（５ｎ２０ｑ６：
ｗｔ９６）が形成される。[Function] In the semiconductor laser bonding method according to the present invention, since Au and Sn layers are alternately formed on the main surface and back surface of the submount, Au and 111 layers are formed in the 80 layers during solder melting.
is diffused and an alloy solder of Au8n is formed.
By setting the metal width W2 = 1.5X (Sn layer width Wl), highly reliable AuSn alloy solder (5n20q6:
wt96) is formed.
以下、この発明の一実施例を図について説明する。第１
図にかいて、（１）はＬＤチップ、伐）はＬＤチップ（
１）の裏面電極（最表面Ａｕ層よシ成る）（６）は放熱
用ブロック、（７）はＡｕ層（７１） ＆１層（７２）
が交互に蒸着により形成された蒸着層で、サブマウント
（４）の主面及び裏面のバリヤ層（５）の上に形成され
ている。An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, (1) is the LD chip, and (1) is the LD chip (
1) Back electrode (consisting of the outermost Au layer) (6) is a heat dissipation block, (7) is the Au layer (71) & 1 layer (72)
are vapor deposited layers formed alternately by vapor deposition, and are formed on the barrier layer (5) on the main surface and the back surface of the submount (4).
火に、この発明のｔＩｊＪ作について説明する。I will now explain the tIjJ creation of this invention.
サブマウント（４）の主面（ＬＤチップ（１）が載置さ
れる面）及び裏面（放熱用ブロック（６）と接着する面
）に、最表面Ａｕ層より成るバリヤ層（５）を形成し、
このバリヤ層（５）の上には、主面側に、ＬＤチップ（
１）が載置される領域に釦層（７１） （＠Ｗ２ ）
、加層（７２）（幅Ｗｌ）を交互にメタルマスクを用い
て蒸着形成する。裏面側に、全領域に、Ａｕ層（７１）
（幅Ｗ２）、Ｓｎ層（７２） （［Ｗｌ ）を交互に
、蒸着形成する。A barrier layer (5) consisting of the outermost Au layer is formed on the main surface (the surface on which the LD chip (1) is placed) and the back surface (the surface to be bonded to the heat dissipation block (6)) of the submount (4). death,
On this barrier layer (5), an LD chip (
1) Button layer (71) (@W2) in the area where it is placed
, additional layers (72) (width Wl) are alternately formed by vapor deposition using a metal mask. Au layer (71) on the entire area on the back side
(width W2) and Sn layers (72) ([Wl) are alternately formed by vapor deposition.
この時、Ａｕ層（７１）とＳｎ層（７２）の膜厚は同じ
にし、幅をＷ２＝１．５ｘＷｔに設定する。サブマウン
トを用いて、ＬＤチップ（１）、放熱用ブロック（６）
を同時にある一定荷重で加圧して加熱すると、鋤層（７
２）の中に、Ａｕ層（７１）が拡散し、んとＳｎが合金
半田を形成するっ全層とＳＫ１層の比は、 Ｗ２＝１．
５ｘＷ＋としている事から、信頼性の高いＡｕ８ｎ （
Ｓｎ ２０％：ｗｔ％）の共晶合金が形成され、ＬＤチ
ップ（１）とサブマウント（４）放熱用ブロック（６）
の接合面カ１共晶合金で接着されることになる。At this time, the thickness of the Au layer (71) and the Sn layer (72) are made the same, and the width is set to W2=1.5xWt. Using a submount, LD chip (1), heat dissipation block (6)
When simultaneously pressurized and heated under a certain load, the plow layer (7
2), in which the Au layer (71) is diffused and the Sn and Sn form an alloy solder.The ratio of the total layer to the SK1 layer is W2=1.
Since it is 5xW+, it is highly reliable Au8n (
A eutectic alloy of Sn (20%:wt%) is formed, and the LD chip (1), submount (4), and heat dissipation block (6) are formed.
The joint surface of the two is bonded with a eutectic alloy.
なか、上記実施例で＃ｉＡｕ層と８口層の幅をある一定
比率になる様にした場合を示したが、幅を同じにして、
Ａｕ層の厚みｔ２．５ＸＩＩ層の厚みｔｌとした場合、
ｔ２＝ｊｌとなる様に蒸着してもよい。In the above example, the width of the #iAu layer and the 8-hole layer were made to have a certain ratio, but if the widths were made the same,
When the thickness of the Au layer is t2.5 and the thickness of the XII layer is tl,
Vapor deposition may be performed so that t2=jl.
又、蒸着形成以外はスパッタでもよい。In addition, sputtering may be used for formation other than vapor deposition.
〔発明の効果ｊ
以上のようにこの発明によれば、サブマウントの主面及
び裏面のバリヤ層の上に、Ａｕ層（輻Ｗ２）、８ｒ＋層
（幅Ｗｌ）を１２ ＝ １．５ Ｗｌとなる様に交互に
蒸着形成したので、作業時に半田供給を必要とせず、又
、Ａｕと鋤が別々に形成されて、半田溶融時に、ＡｕＳ
ｎ （５ｎ２０％ ： ｗｔ％ ）共晶合金が形成され
る為に、スクラブ作業を不要とし、量産性に適合した信
頼性の高い接合が得られる。[Effects of the Invention j As described above, according to the present invention, the Au layer (width W2) and the 8r+ layer (width Wl) are formed with a width of 12 = 1.5 Wl on the barrier layers on the main and back surfaces of the submount. Since they are formed by vapor deposition alternately, there is no need to supply solder during work, and since the Au and spade are formed separately, when the solder is melted, the AuS
Since a n (5n20%: wt%) eutectic alloy is formed, scrubbing is not necessary and a highly reliable bond suitable for mass production can be obtained.
第１図はこの発明の一実施例による半導体レーザの接合
方法を示す断面図、第２図は従来の半導体レーザの接合
方法を示す断面図であるう図に釦いて、（１）はＬＤチ
ップ、（２）はＬＤチップ（１）の裏面！極、（４）は
すブマウン１− 、（５）はサブマウント（４）の主面
及び裏面に形成されたバリヤ層、（６）は放熱用ブロッ
ク、（７）はＡｕ層（７１）、お層（７２）が各々交互
に蒸着により形成された蒸着層を示すつ尚１図中、同一
符号は同一、又は相当部分を示す。FIG. 1 is a sectional view showing a semiconductor laser bonding method according to an embodiment of the present invention, and FIG. 2 is a sectional view showing a conventional semiconductor laser bonding method. , (2) is the back side of the LD chip (1)! pole, (4) a submount 1-, (5) a barrier layer formed on the main and back surfaces of the submount (4), (6) a heat dissipation block, (7) an Au layer (71), The layers (72) each represent a vapor deposited layer formed by vapor deposition alternately, and the same reference numerals in FIG. 1 indicate the same or corresponding parts.
Claims (1)
固着される接合に於いて、前記サブマウントの主面及び
裏面にはバリヤ層が形成され、そのバリヤ層上に、主面
側には前記レーザチップが載置される領域に、裏面側に
は全領域に、２元より成る合金半田を最終的に形成する
為の各々の金属を交互にあるピッチで形成した事を特徴
とする半導体レーザの接合方法。In the bonding process in which the laser chip is fixed to the heat dissipation block via the submount, a barrier layer is formed on the main surface and the back surface of the submount, and the laser chip is placed on the main surface side of the barrier layer. Bonding of a semiconductor laser, characterized in that each metal is alternately formed at a certain pitch in the area where the metal is placed, and in the entire area on the back side, to ultimately form an alloy solder consisting of two elements. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32188389A JPH03183178A (en) | 1989-12-12 | 1989-12-12 | Joining method of semiconductor laser |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32188389A JPH03183178A (en) | 1989-12-12 | 1989-12-12 | Joining method of semiconductor laser |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03183178A true JPH03183178A (en) | 1991-08-09 |
Family
ID=18137470
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32188389A Pending JPH03183178A (en) | 1989-12-12 | 1989-12-12 | Joining method of semiconductor laser |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03183178A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5305340A (en) * | 1992-12-16 | 1994-04-19 | International Business Machines Corporation | Waveguide ridge laser device with improved mounting and ridge protection |
| US5307357A (en) * | 1992-11-05 | 1994-04-26 | International Business Machines Corporation | Protection means for ridge waveguide laser structures using thick organic films |
| JPH0891970A (en) * | 1994-09-16 | 1996-04-09 | Nippon Steel Corp | Method for forming copper alloy layer on surface of ceramic |
| JP2010073758A (en) * | 2008-09-16 | 2010-04-02 | Furukawa Electric Co Ltd:The | Semiconductor laser module |
-
1989
- 1989-12-12 JP JP32188389A patent/JPH03183178A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5307357A (en) * | 1992-11-05 | 1994-04-26 | International Business Machines Corporation | Protection means for ridge waveguide laser structures using thick organic films |
| US5305340A (en) * | 1992-12-16 | 1994-04-19 | International Business Machines Corporation | Waveguide ridge laser device with improved mounting and ridge protection |
| JPH0891970A (en) * | 1994-09-16 | 1996-04-09 | Nippon Steel Corp | Method for forming copper alloy layer on surface of ceramic |
| JP2010073758A (en) * | 2008-09-16 | 2010-04-02 | Furukawa Electric Co Ltd:The | Semiconductor laser module |
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