JPH03180070A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH03180070A JPH03180070A JP31925689A JP31925689A JPH03180070A JP H03180070 A JPH03180070 A JP H03180070A JP 31925689 A JP31925689 A JP 31925689A JP 31925689 A JP31925689 A JP 31925689A JP H03180070 A JPH03180070 A JP H03180070A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor
- film
- grooves
- sio2
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 66
- 238000000034 method Methods 0.000 claims abstract description 16
- 238000005498 polishing Methods 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 18
- 229910052681 coesite Inorganic materials 0.000 abstract description 8
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 8
- 239000000377 silicon dioxide Substances 0.000 abstract description 8
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 8
- 229910052682 stishovite Inorganic materials 0.000 abstract description 8
- 229910052905 tridymite Inorganic materials 0.000 abstract description 8
- 230000010354 integration Effects 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 239000012212 insulator Substances 0.000 abstract 1
- 239000010408 film Substances 0.000 description 32
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
Landscapes
- Element Separation (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野］
本発明は半導体装置に係り、より詳しくは、ＳＯＩ （
Ｓｉｌｉｃｏｎ ｏｎ Ｉｎ５ｕｌａｔｏｒ、以下ＳＯ
Ｉと略記する。）構造を有する半導体装置及びその製造
方法に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device, and more specifically, to a semiconductor device (SOI).
Silicon on In5ulator, hereinafter SO
It is abbreviated as I. ) structure and a method for manufacturing the same.
〔従来の技術］
近年、半導体集積回路装置の高集積化、多機能化の進展
にともない、３次元半導体集積回路装置をはじめ、パワ
ーＭＯ３、センサーなどの分野においては、ＳＯＩ技術
の検討が進められている。[Prior Art] In recent years, with the progress of semiconductor integrated circuit devices becoming highly integrated and multi-functional, SOI technology has been studied in fields such as three-dimensional semiconductor integrated circuit devices, power MO3, and sensors. ing.
例えば、” ５ｉｌｉｃｏｎ −ｏｎ −Ｉｎ５ｕｌａ
ｔｏｒ （ＳＯＩＩｂｙ Ｂｏｎｄｉｎｇ ａｎｄ Ｅ
ｔｃｈ −Ｂａｃｋ” ＩＥＥＥ Ｉｎｔｅｒｎａｔｉ
ｏｎａｌ Ｅｌｅｃｔｒｏｎ Ｄｅｖｉｃｅ Ｍｅｅｔ
ｉｎｇ （ＩＥＤＭＩ ＴｅｃｈｎｉｃａｌＤｉｇｅｓ
ｔ 、ＰＰ、６８４−６８７ 、１９８５に開示されて
いるような基板張り合わせ技術がある。For example, “5ilicon -on -In5ula
tor (SOIIby Bonding and E
tch-Back” IEEE International
onal Electron Device Meet
ing (IEDMI Technical Diges
There is a substrate bonding technique as disclosed in J.T., PP, 684-687, 1985.
この場合、２枚のＳｉウェハの表面を重ね合わせた後、
静電圧着により張り合わせる。さらに、Ｓｉウェハの一
方を所望の膜厚になるように研摩するのが一般的である
。In this case, after overlapping the surfaces of two Si wafers,
Paste together using electrostatic bonding. Furthermore, it is common to polish one side of the Si wafer to a desired thickness.
［発明が解決しようとする課題１
しかしながら、前述の従来の技術では、Ｓｌウェハの一
方を所望の膜厚に薄膜化する際に、研摩と同時に薄膜を
モニターする方法がないため、所望の膜厚を容易に得る
ことができない、また、Ｓ１層の膜厚が約２μ以下と薄
い場合は、特にその膜厚を精度よく制御する方法がない
、その結果、薄膜のＳｉ層を有するＳｏｌ素子の実現が
困難であった。[Problem to be Solved by the Invention 1] However, in the conventional technology described above, when thinning one side of the Sl wafer to a desired film thickness, there is no way to monitor the thin film at the same time as polishing. Moreover, when the thickness of the S1 layer is as thin as about 2μ or less, there is no way to precisely control the thickness.As a result, it is difficult to realize a Sol element with a thin Si layer. was difficult.
そこで、本発明はこのような課題を解決するものであり
、その目的とするところは、容易に高集積化、高機能化
することが可能なＳＯＩ構造を有する半導体装置及びそ
の製造方法を提供するところにある。SUMMARY OF THE INVENTION The present invention is intended to solve these problems, and its purpose is to provide a semiconductor device having an SOI structure that can easily be highly integrated and highly functional, and a method for manufacturing the same. There it is.
［課題を解決するための手段］
本発明の半導体装置は、基板表面に複数の一定量さの溝
が形成され、前記溝には絶縁膜もしくは半導体層が埋込
まれた第１半導体基板と、基板表面上に絶縁膜を有する
第２半導体基板とが、前記基板表面が対向する方向に接
合され、前記第１半導体基板の接合面と反対側の前記第
１半導体基板の表面から前記溝表面までの半導体層が除
去されてなることを特徴とする。[Means for Solving the Problems] A semiconductor device of the present invention includes a first semiconductor substrate in which a plurality of grooves of a certain length are formed on the surface of the substrate, and an insulating film or a semiconductor layer is embedded in the grooves; A second semiconductor substrate having an insulating film on the surface of the substrate is bonded in a direction in which the surfaces of the substrates face each other, and from the surface of the first semiconductor substrate opposite to the bonding surface of the first semiconductor substrate to the surface of the groove. The semiconductor layer is removed.
また、本発明の半導体装置の製造方法は、基板表面に複
数の一定量さの溝が形成され、前記溝には絶縁膜もしく
は半導体層が埋込まれた第１半導体基板と、基板表面上
に絶縁膜を有する第２半導体基板とを、前記基板表面が
対向する方向に接合する工程と、前記第１半導体基板の
接合面と反対側の前記第１半導体基板表面から、前記溝
の表面を目印として、前記第１半導体基板を一定量除去
する工程とを具備することを特徴とする。Further, in the method for manufacturing a semiconductor device of the present invention, a plurality of grooves of a certain length are formed on a substrate surface, a first semiconductor substrate in which an insulating film or a semiconductor layer is embedded in the grooves, and a first semiconductor substrate on the substrate surface. bonding a second semiconductor substrate having an insulating film in a direction in which the surfaces of the substrates face each other, and marking the surface of the groove from the surface of the first semiconductor substrate opposite to the bonding surface of the first semiconductor substrate; The method is characterized by comprising a step of removing a predetermined amount of the first semiconductor substrate.
以下、本発明の代表的な実施例を図面を用いて具体的に
説明する。Hereinafter, typical embodiments of the present invention will be specifically described using the drawings.
第１図は、本発明によるＳＯＩ構造を有する半導体装置
の一実施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment of a semiconductor device having an SOI structure according to the present invention.
第１図において、ＳＯＩ構造は、基板内に満２が形成さ
れ、この満２には酸化（Ｓｉｎ−）膜３が埋込まれ、基
板の一表面にＳ ｉ Ｏ２膜４が形成された第１のＳｉ
基基板上、基板表面に５ ｉ ０２膜６が形成された第
２のＳｉ基板５とが、ＳｉＯ２ｉ４及び６とが対向する
ように接合して構成されている。In FIG. 1, the SOI structure includes a silicon oxide film formed within a substrate, an oxide (Sin-) film 3 embedded in the silicon oxide film 3, and an SiO2 film 4 formed on one surface of the substrate. 1 Si
A second Si substrate 5 on which a 5 i 02 film 6 is formed on the substrate surface is bonded to the base substrate so that the SiO 2 i 4 and 6 face each other.
第１のＳｉ基板ｌ内の、Ｓ ｉ Ｏｚ ｔｌｉ ３．４
．６により絶縁分離された各類ｔｅｌ Ｏａ、１０ｂ、
１０ｃ、ｌｏｄには、それぞれ能動素子が形成される。S i Oz tli 3.4 in the first Si substrate l
．． Each type tel Oa, 10b, isolated by 6
Active elements are formed in 10c and lod, respectively.
上記実施例の構造によれば、能動素子領域は、ＳｉＯ，
ｌｉ３．４．６により完全に絶縁膜分離されているため
、寄生容量が少なく、ラッチアップ・フリー等の素子分
離特性１優れたＳＯＩ素子が得られる。According to the structure of the above embodiment, the active element region includes SiO,
Since the insulating film is completely isolated by li3.4.6, an SOI element with excellent element isolation characteristics 1 such as low parasitic capacitance and latch-up freedom can be obtained.
次に、上記実施例のＳＯＩ構造を有する半導体装置の製
造方法を第３図について順次説明する。Next, a method for manufacturing the semiconductor device having the SOI structure of the above embodiment will be sequentially explained with reference to FIGS.
（１）第３図（ａ）、（ｂ）は、本発明によるＳＯＩ構
造を有する半導体装置を製造するためにそれぞれ予備加
工された半導体基板を示す。(1) FIGS. 3(a) and 3(b) show semiconductor substrates that have been preprocessed to manufacture a semiconductor device having an SOI structure according to the present invention.
（ａ）図において、第１のＳｉ基板１内には、基板表面
から一定の深さ１例えば１〜４μｍを有する溝２が形成
され、この満２内には、気相成長（ＣＶＤ）法とエッチ
バック法との併用等によりＳ ｉ Ｏ２膜３が埋込まれ
ている。さらに、Ｓｉ基板１表面には熱酸化法らしくは
ＣＶＤ法等により５ｉＯ−膜４が形成されている。In the figure (a), a groove 2 having a certain depth 1, for example, 1 to 4 μm from the substrate surface is formed in a first Si substrate 1, and a groove 2 is formed within this depth by a chemical vapor deposition (CVD) method. The SiO2 film 3 is embedded by using a combination of the etch-back method and the like. Furthermore, a 5iO- film 4 is formed on the surface of the Si substrate 1 by a thermal oxidation method such as a CVD method.
（ｂ）図において、第２のＳｉ基板２表面にはＳｌＯ□
１１６が、熱酸化法らしくはＣＶＤ法等により、厚さ１
〜５μｍに形成されている。(b) In the figure, the surface of the second Si substrate 2 has SlO□
116 is reduced to a thickness of 1 by a thermal oxidation method, such as a CVD method.
It is formed to have a thickness of ~5 μm.
なお、第１及び第２のＳｉ基板は厚さ４００〜７００μ
ｍの厚さを有する汎用のＳｉ基板である。Note that the first and second Si substrates have a thickness of 400 to 700 μm.
It is a general-purpose Si substrate with a thickness of m.
（２）第３図（ｃ）は、第１のＳｉ基基板上溝２及び５
ｉＯａ膜４が形成された基板表面と、第２のＳｉ基板２
の５ｉＯａ膜６が形成された基板表面とがそれぞれ対向
する方向に重ね合わせた後、静電圧着により張合わせた
状態を示す。(2) FIG. 3(c) shows the grooves 2 and 5 on the first Si-based substrate.
The surface of the substrate on which the iOa film 4 is formed and the second Si substrate 2
A state in which the substrate surfaces on which the 5iOa film 6 is formed are stacked in opposing directions and then bonded together by electrostatic bonding is shown.
（３）次に、第３図（ｄ）は、前記第１のＳｉ基板１の
接合面と反対面を、前記溝２の表面が露出するまで、基
板表面が平坦になるように研摩した状態を示す、なお、
図において、１ａは研摩により除去されたＳｉ基板を示
す。(3) Next, FIG. 3(d) shows a state in which the surface opposite to the bonding surface of the first Si substrate 1 is polished so that the surface of the substrate is flat until the surface of the groove 2 is exposed. In addition,
In the figure, 1a shows the Si substrate removed by polishing.
この状態で、第１のＳｉ基板の膜厚は、溝３の深さと同
じ１〜４μｍとなり、Ｓｉｎ、膜３．４．６により絶縁
分離された薄膜領域１０ａ、１０ｂ、１０ｃ、１０ｄが
得られる。In this state, the film thickness of the first Si substrate is 1 to 4 μm, which is the same as the depth of the groove 3, and thin film regions 10a, 10b, 10c, and 10d are obtained, which are insulated and isolated by the Sin film 3.4.6. .
以下、従来の半導体装置の製造方法に従い、絶縁分離さ
れた薄膜領域１０ａ、ｌｏｂ、１０ｃ、１０ｄにそれぞ
れ能動素子が形成される。Thereafter, active elements are formed in the isolated thin film regions 10a, lob, 10c, and 10d, respectively, according to a conventional semiconductor device manufacturing method.
上記実施例においては、第１のＳｉ基板と第２のＳｉ基
板との接着性を向上するために、第１のＳｉ基板表面に
Ｓ ｉ Ｏ２膜４を形成したが、両者の接着性が良好な
場合には、この５ｉＯａ膜４は不用である。In the above example, in order to improve the adhesiveness between the first Si substrate and the second Si substrate, the SiO2 film 4 was formed on the surface of the first Si substrate, but the adhesiveness between the two was good. In such a case, this 5iOa film 4 is unnecessary.
また、上記溝３の幅を一定、例えば１〜２μｍとするこ
とにより、Ｓｉｎ、膜の充填性や加工制御性を向上する
ことができる。Further, by setting the width of the groove 3 to be constant, for example, 1 to 2 μm, it is possible to improve the filling properties of the Sin and film and the processing controllability.
能動素子形成領域１０ａ、ｆｏｂ、ｌＯｃ、１ＯｄのＳ
ｉ［の膜厚は、溝２の深さを変えることにより任意に設
定することが可能である。S of active element formation region 10a, fob, lOc, 1Od
The film thickness of i[ can be arbitrarily set by changing the depth of the groove 2.
上記実施例においては、基板張合わせ方法として静電圧
着法を用いたが、それに変えて、基板を重ね合わせた後
、加熱する方法等を用いて６よい。In the above embodiment, an electrostatic bonding method was used as a method for laminating the substrates, but instead of this, a method of heating the substrates after laminating them may be used.
第２図は、本発明の他の実施例を示す断面図である。図
において、１〜６．１０ａ、１０ｂ、１０ｃ、１０ｄの
部分は第１図と同一の符号を用いた。FIG. 2 is a sectional view showing another embodiment of the invention. In the figure, parts 1 to 6.10a, 10b, 10c, and 10d use the same symbols as in FIG.
第２図において、第１のＳｉ基板１内に形成された満２
の側壁にはＳｉＯ＊膜７が形成され、さらに、この溝２
は多結晶Ｓｉ膜８が埋込まれている。他の部分は、第１
図に示す半導体装置と同様である。In FIG.
A SiO* film 7 is formed on the side wall of the groove 2.
A polycrystalline Si film 8 is embedded. The other parts are the first
This is similar to the semiconductor device shown in the figure.
この構造によれば、第１図に示す半導体装置と同様な効
果が得られるとと６に、溝２が充填性の良い多結晶Ｓｉ
膜８により埋込まれているため、溝の充填性及び加工制
御性のよりよい半導体装置が得られる。According to this structure, the same effect as the semiconductor device shown in FIG.
Since it is buried with the film 8, a semiconductor device with better trench filling performance and better processing controllability can be obtained.
なお、上記実施例においては、溝の充填材料として、Ｓ
ｉ Ｏ＊膜もしくは多結晶Ｓｉ膜を用いたが、それに
変えてアモルファスシリコン膜らしくは半導体層を用い
てもよい。In the above embodiment, S is used as the groove filling material.
Although an iO* film or a polycrystalline Si film is used, a semiconductor layer such as an amorphous silicon film may be used instead.
〔発明の効果１
以上述べたように、本発明によれば、基板表面に複数の
一定深さの溝が形成され、この溝には絶縁膜らしくは半
導体層が埋込まれた第１の半導体基板と、基板表面に絶
縁膜を有する第２の半導体基板とを、それぞれの基板表
面が対向する方向に接合した後、第１の半導体基板の接
合面と反対面を、前記溝の表面を目印として、溝の表面
が露出するまで平坦に研摩して、絶縁膜で絶縁分離され
た薄膜領域を形成する。その場合、研摩時には、溝を目
印として第１の半導体基板の膜厚のモニターができるた
め、精度よく薄膜の半導体層を有するＳＯＩ素子を実現
することができる。また、繁雑なプロセスを使用してい
ないため、高集積度で、良品歩留りの高い半導体装置を
容易に得ることができるという効果を有する。[Effects of the Invention 1] As described above, according to the present invention, a plurality of grooves with a constant depth are formed on the surface of a substrate, and in these grooves, a first semiconductor layer, which is like an insulating film, is embedded with a semiconductor layer. After bonding a substrate and a second semiconductor substrate having an insulating film on the surface of the substrate in a direction in which the surfaces of the respective substrates face each other, a surface of the first semiconductor substrate opposite to the bonding surface is marked with the surface of the groove. Then, the groove is polished flat until the surface is exposed, forming a thin film region isolated by an insulating film. In this case, during polishing, the film thickness of the first semiconductor substrate can be monitored using the grooves as marks, so an SOI element having a thin semiconductor layer can be realized with high precision. Further, since no complicated process is used, it is possible to easily obtain a semiconductor device with a high degree of integration and a high yield of non-defective products.
以上本発明を実施例に基づいて具体的に説明したが、本
発明は上述の実施例に限定されず、その要旨を逸しない
範囲で種々変更が可能であることは言うまでちない。Although the present invention has been specifically described above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples and can be modified in various ways without departing from the gist thereof.
第１図は本発明の半導体装置の一実施例を示す断面図、
第２図は本発明の他の実施例を示す断面図、第３図（ａ
）〜（ｄ）は本発明の半導体装置の製造工程別断面説明
図である。
１．５．
２ ・ ・ ・
３、４．
８ ・ ・ ・
１０ａ、
１０ｃ、
ｌａ・・・・Ｓｉ基板
・溝
６．７・・・５ｉＯａｔｌｉ
・・・・・多結晶Ｓｉ膜
１０ｂ。
１０ｄ・・・能動素子形成領域
以上
第
１
図
第
鉛
第
図FIG. 1 is a sectional view showing an embodiment of the semiconductor device of the present invention;
FIG. 2 is a sectional view showing another embodiment of the present invention, and FIG.
) to (d) are cross-sectional explanatory views according to manufacturing steps of the semiconductor device of the present invention. 1.5. 2 ・ ・ ・ 3, 4. 8...10a, 10c, la...Si substrate/groove 6.7...5iOatli...polycrystalline Si film 10b. 10d...Active element formation area and above Figure 1 Figure 1
Claims (2)
溝には絶縁膜もしくは半導体層が埋込まれた第１半導体
基板と、 基板表面上に絶縁膜を有する第２半導体基板とを、 前記基板表面が対向する方向に接合してなることを特徴
とする半導体装置。(1) A first semiconductor substrate in which a plurality of grooves with a constant depth are formed on the surface of the substrate, and an insulating film or a semiconductor layer is embedded in the grooves, and a second semiconductor substrate having an insulating film on the surface of the substrate. A semiconductor device, wherein the substrate surfaces are bonded in opposing directions.
溝には絶縁膜もしくは半導体層が埋込まれた第１半導体
基板と、基板表面上に絶縁膜を有する第２半導体基板と
を、前記基板表面が対向する方向に接合する工程と、 前記第１半導体基板の接合面と反対面を、前記溝の表面
を目印として、一定量研摩する工程とを具備することを
特徴とする半導体装置の製造方法。(2) A first semiconductor substrate in which a plurality of grooves with a constant depth are formed on the substrate surface, and an insulating film or a semiconductor layer is embedded in the grooves; and a second semiconductor substrate having an insulating film on the substrate surface. and a step of polishing a surface of the first semiconductor substrate opposite to the bonding surface by a certain amount using the surface of the groove as a mark. A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31925689A JPH03180070A (en) | 1989-12-08 | 1989-12-08 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31925689A JPH03180070A (en) | 1989-12-08 | 1989-12-08 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03180070A true JPH03180070A (en) | 1991-08-06 |
Family
ID=18108165
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31925689A Pending JPH03180070A (en) | 1989-12-08 | 1989-12-08 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03180070A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0563070A (en) * | 1991-09-03 | 1993-03-12 | Fujitsu Ltd | Semiconductor device and its manufacture |
| JPH05326693A (en) * | 1991-10-24 | 1993-12-10 | Mitsubishi Electric Corp | Manufacture of semiconductor device, and semiconductor device |
| US5399233A (en) * | 1991-12-05 | 1995-03-21 | Fujitsu Limited | Method of and apparatus for manufacturing a semiconductor substrate |
| JPH1050824A (en) * | 1995-12-30 | 1998-02-20 | Hyundai Electron Ind Co Ltd | Manufacture of soi board |
| KR100348578B1 (en) * | 1999-12-23 | 2002-08-13 | 동부전자 주식회사 | Semiconductor device having improved plate electrode and fabrication method thereof |
-
1989
- 1989-12-08 JP JP31925689A patent/JPH03180070A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0563070A (en) * | 1991-09-03 | 1993-03-12 | Fujitsu Ltd | Semiconductor device and its manufacture |
| JPH05326693A (en) * | 1991-10-24 | 1993-12-10 | Mitsubishi Electric Corp | Manufacture of semiconductor device, and semiconductor device |
| US5399233A (en) * | 1991-12-05 | 1995-03-21 | Fujitsu Limited | Method of and apparatus for manufacturing a semiconductor substrate |
| JPH1050824A (en) * | 1995-12-30 | 1998-02-20 | Hyundai Electron Ind Co Ltd | Manufacture of soi board |
| KR100348578B1 (en) * | 1999-12-23 | 2002-08-13 | 동부전자 주식회사 | Semiconductor device having improved plate electrode and fabrication method thereof |
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