JPH03175734A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH03175734A JPH03175734A JP1316016A JP31601689A JPH03175734A JP H03175734 A JPH03175734 A JP H03175734A JP 1316016 A JP1316016 A JP 1316016A JP 31601689 A JP31601689 A JP 31601689A JP H03175734 A JPH03175734 A JP H03175734A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- lsi
- output
- output buffer
- buffer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 239000000758 substrate Substances 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 16
- 230000001681 protective effect Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 3
- 238000003491 array Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
Landscapes
- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔成業上の利用分野〕
この発明はゲートアレイに代表されるマスタースライス
ＬＳＩの内、相補型酸化膜半導体（以下ＣＭＯ８と呼ぶ
）で構成されたり、ＳＩのＬＳＩ外部への出力回路Ｃ以
下出力バッファと呼ぶ）に関するものである。[Detailed Description of the Invention] [Field of Commercial Application] This invention is applicable to master slice LSIs typified by gate arrays, which are constructed of complementary oxide film semiconductors (hereinafter referred to as CMO8), and which are external to the LSI of SI. This relates to an output circuit C (hereinafter referred to as an output buffer).
第３図はマスタースライスＬＳＩチップ上のＩ１０バッ
ファの内部構成を示した配置図である。FIG. 3 is a layout diagram showing the internal configuration of the I10 buffer on the master slice LSI chip.
この工１０バッファ（１）はボンゲインクバット（２）
、入力用バッファ（３）、保護抵抗（４）、出力用バッ
ファ（５）と内部信号端子（６）を有している。This work 10 buffer (1) is Bonga Kubat (2)
, an input buffer (3), a protection resistor (4), an output buffer (5), and an internal signal terminal (6).
第４図はＩ１０バンファ（１）を入カバソファとして用
いる場合の接続図で、ボンディングバンド（２）は保護
抵抗（４）の一端（４ａ）に、保護抵抗（４）のもう−
万の端子（４ｂ）は入力用バッファ（３）の入力端子（
３ａ）に、入力用バッファ（３）の出力端子（３ｂ）は
内部信号端子（６）にそれぞれ接続されている。Figure 4 is a connection diagram when using the I10 bumper (1) as an input cover sofa, where the bonding band (2) is connected to one end (4a) of the protective resistor (4) and the other end of the protective resistor (4).
The input terminal (4b) of the input buffer (3) is the input terminal (
3a), the output terminals (3b) of the input buffer (3) are connected to the internal signal terminals (6), respectively.
第５図はＩ１０バッファ（１） ’！に出力バッファと
して用いる場合の接続図で、内部信号端子（６）は出力
用バッファ（５）の入力端子（５ａ）に、出力用バッフ
ァ（５）の出力端子（５ｂ）はボンディングバント（２
）にそれぞれ接続されている。Figure 5 shows I10 buffer (1)'! In this connection diagram, the internal signal terminal (6) is connected to the input terminal (5a) of the output buffer (5), and the output terminal (5b) of the output buffer (5) is connected to the bonding band (2).
) are connected to each other.
第６図は出力に第５図の構成を持つＬ Ｓ Ｉ （７）
で他のＬ Ｓ Ｉ （８）を駆動する場合の接続図で、
ＬＳＩ（７）の出力（７ａ）はダンプ抵抗（９）の一端
（９ａ）に、ダンプ抵抗（９）のもう一端（９ｂ）はＬ
Ｓ Ｉ （８）の入力端子（８ａ）に、ＬＳＩ（７）
の接地端子（７ｂ）とＬ ＳＩ ｆ８）の接地端子（８
ｂ）は接地にそれぞれ接続されている。この接続はＬ
Ｓ Ｉ （７）の出力インピーダンスが低く。Figure 6 shows an LSI (7) whose output has the configuration shown in Figure 5.
The connection diagram when driving another LSI (8) with
The output (7a) of the LSI (7) is connected to one end (9a) of the dump resistor (9), and the other end (9b) of the dump resistor (9) is connected to the L
The LSI (7) is connected to the input terminal (8a) of the S I (8).
The ground terminal (7b) of LSI f8) and the ground terminal (8
b) are each connected to ground. This connection is L
The output impedance of S I (7) is low.
Ｌ Ｓ Ｉ （８）の入力インピーダンスが高い場合、
通常的に用いられる構成である。When the input impedance of LSI (8) is high,
This is a commonly used configuration.
第７図は第６図を電気素子で等測的に表現した回路図で
、出力信号源αＱ１出力（７ａ）の出力抵抗Ｏυ、ダン
プ抵抗（９）、入力（８ａ）の入力容量ａの及びＬＳＩ
（７） 、 （８）間の結線のインダクタンス（至）が
直列に接続されている。なか、出力抵抗Ｑｌ）にはＬ
Ｓ Ｉ （７） 、 （８）関の結線の抵抗弁をも含ん
でいる。Fig. 7 is a circuit diagram isometrically expressing Fig. 6 using electric elements, and shows the output resistance Oυ of the output signal source αQ1 output (7a), the dump resistance (9), the input capacitance a of the input (8a), and LSI
The inductances of the connections between (7) and (8) are connected in series. Among them, the output resistance Ql) is L.
It also includes resistance valves for the connections S I (7) and (8).
次に動作について説明する。第７図にかいて。Next, the operation will be explained. Draw it in Figure 7.
Ｌ Ｓ Ｉ （８）の入力（８ａ）の電圧は出力信号源
α０がデジタル波形の場合、次式で表わすことができる
。When the output signal source α0 is a digital waveform, the voltage at the input (8a) of LSI (8) can be expressed by the following equation.
７’Ｃだし、
ψ＝ ｔａｎ−’ −”−
ω、ｆ−フＴ
Ｃ
Ｌ：インダクタンスＱ３ Ｃ：入力容量（２）こ
こで、ダンプ抵抗（９）の抵抗値を適度に調節すること
によ５．ＬＳＩ（８）の入力（８ａ）の入力波形には、
オーバーシュート電圧や、アンダーシュート電圧が加わ
らないように調節できる。7'C, ψ= tan-'-"- ω, f-F T C L: Inductance Q3 C: Input capacitance (2) Here, by appropriately adjusting the resistance value of the dump resistor (9), 5.The input waveform of the input (8a) of the LSI (8) is as follows:
It can be adjusted so that overshoot voltage and undershoot voltage are not applied.
〔発明が解決しようとする課題］
従来の半導体集積回路装置は以上のように構成されてい
たので、Ｌ Ｓ Ｉ （７）でＬＳＩ（８）’ｆ−駆動
する場合にはダンプ抵抗が必要で、駆動する本数分だけ
、ダンプ抵抗を必要とし、実装上必要なダンプ抵抗の数
とそれを実装する基板領域會必要とする問題点があった
。[Problems to be Solved by the Invention] Since the conventional semiconductor integrated circuit device is configured as described above, a dump resistor is required when LSI (8)'f- is driven by LSI (7). However, there is a problem in that the number of dump resistors required for mounting is equal to the number of dump resistors to be driven, and the board area for mounting them is also required.
この発明は上記のような問題点を解消するためになされ
たもので、実装基板面積及び実装部品点数を削減できる
半導体集積回路装置を得ることを目的とする。The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor integrated circuit device that can reduce the mounting board area and the number of mounted components.
この発明に係る半導体集積装置は、外付けのダンプ抵抗
の代ジに、ＬＳＩ（９）内の出力バッファ内で本来出カ
バソファ時には用いられない保護抵抗の全部１７′ｃは
一部をダンプ抵抗として用いたものである。In the semiconductor integrated device according to the present invention, in place of the external dump resistor, all of the protective resistors 17'c, which are not originally used in the output buffer in the LSI (9), are partially used as dump resistors. This is what I used.
この発明に釦けるダンプ抵抗は、外付けしなければなら
なかったダンプ抵抗を駆動ＬＳＩ内に取シ込み、なおか
つ取り込んだ抵抗は、出力バッファを構成した場合には
用いられていなかった保護抵抗を用い７’（ため、駆動
ＬＳＩのチップ面積を増すことなく、実装基板面積、実
装部品点数が削減できる。The dump resistor of this invention incorporates the dump resistor that had to be externally connected into the driving LSI, and the incorporated resistor also replaces the protective resistor that was not used when an output buffer was configured. Therefore, the mounting board area and the number of mounted parts can be reduced without increasing the chip area of the drive LSI.
以下、この発明の一実施例を図について説明する。第１
図はこの発明の一実施例であるＩ１０バッファ（１）４
Ｃ出力バツフアを構成する場合の接続図で、内部信号端
子（６）は出力用バッファ（５）の入力（臘）に、出力
用バッファ（５）の出力（５ｂ）は保護抵抗（４）の端
子（４ａ）に、保護抵抗（４）のもう一端（４ｂ）ｌｄ
ポンディングパッド（２）にそれぞれ接続されている。An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows an I10 buffer (1) 4 which is an embodiment of this invention.
In the connection diagram when configuring a C output buffer, the internal signal terminal (6) is connected to the input (臘) of the output buffer (5), and the output (5b) of the output buffer (5) is connected to the protective resistor (4). Connect the other end (4b) of the protective resistor (4) to the terminal (4a).
Each is connected to a bonding pad (2).
第２図は第１図の構成を持つ出力バッファを用いて他の
Ｌ ＳＩ （８）を駆動する場合の接続図で、ＬＳＩ（
７）の出力（７ａ）はＬ Ｓ Ｉ ｔ＆＞の入力（８ａ
）に、ＬＳＩ ｆ７１ 、 （８）の接地端子（７ｂ＞
、 （８ｂ）は接地にそれぞれ接続されている。Figure 2 is a connection diagram when another LSI (8) is driven using the output buffer having the configuration shown in Figure 1.
The output (7a) of 7) is the input (8a) of L S I t&>
), LSI f71, (8) ground terminal (7b>
, (8b) are each connected to ground.
この発明の動作は前記従来のものの等価回路図である第
７図中のダンプ抵抗（９）がＬ Ｓ Ｉ （７）中に入
った回路と等価なため従来例と全く同じ動作を行なう。The operation of the present invention is exactly the same as that of the conventional example because the dump resistor (9) in FIG. 7, which is an equivalent circuit diagram of the conventional example, is equivalent to the circuit included in the LSI (7).
以上のようにこの発明によれば、従来外付けしていたダ
ンプ抵抗を駆動ＬＳＩの出力バッファ内にある保護抵抗
を用いたので、実装面積、実装部品点数が削減でき、よ
って実装基板が安価に、鵞た小型化できるという効果が
ある。As described above, according to the present invention, the dump resistor, which was conventionally attached externally, is replaced by the protective resistor in the output buffer of the drive LSI, so the mounting area and the number of mounted parts can be reduced, and the mounting board can be made at a lower cost. , it has the effect of being able to be significantly downsized.
第１図はこの発明の一実施例による半導体集積回路装置
の出力バッファを構成する接続図、第２図は第１図の実
装基板上でのＬＳＩ同士の接続図、第３図は従来のマス
タースライスＬＳＩの１１０バソファの構成を示す配置
図、第４図は第３図を用いて従来の入力バッファを構成
した時の接続図、第５図は第３図を用いて従来の出力バ
ッファを構成した時の接続図、第６図は第５図の出カバ
ソファを用いた時の実装基板上でのＬＳＩ同士の接続図
、第７図は第６図の等価＠Ｊ路図である。
図に訟いて、Ｃ１）はＩ１０バンファ、（２）はボンデ
ィングパント、 （３）は入力用バッファ、（４）は保
護抵抗。
（５）は出カバソファ、（６）は内部信号端子、（７）
、 （８）はＬＳＩを示す。
なか、図中、同一符号は同一、または相当部分を示す。Fig. 1 is a connection diagram configuring an output buffer of a semiconductor integrated circuit device according to an embodiment of the present invention, Fig. 2 is a connection diagram between LSIs on the mounting board of Fig. 1, and Fig. 3 is a connection diagram of a conventional master. A layout diagram showing the configuration of a 110-bath sofa of a slice LSI, Figure 4 is a connection diagram when a conventional input buffer is configured using Figure 3, and Figure 5 is a configuration diagram of a conventional output buffer using Figure 3. FIG. 6 is a connection diagram of the LSIs on the mounting board when the output sofa of FIG. 5 is used, and FIG. 7 is an equivalent @J path diagram of FIG. 6. In the figure, C1) is an I10 bumper, (2) is a bonding punt, (3) is an input buffer, and (4) is a protection resistor. (5) is the output cover sofa, (6) is the internal signal terminal, (7)
, (8) indicates an LSI. In the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
ァを形成する際、前記出力バッファ内の最終出力段のト
ランジスタと、前記出力バッファの出力端子との間に挿
入する抵抗素子を入力バッファ構成時使用する抵抗素子
と同一の抵抗素子の全部または一部を使用したことを特
徴とする半導体集積回路装置。In a CMOS master slice LSI, when forming an output buffer, the resistance element inserted between the final output stage transistor in the output buffer and the output terminal of the output buffer is the same as the resistance element used when configuring the input buffer. 1. A semiconductor integrated circuit device characterized in that all or part of a resistive element is used.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1316016A JPH03175734A (en) | 1989-12-04 | 1989-12-04 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1316016A JPH03175734A (en) | 1989-12-04 | 1989-12-04 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03175734A true JPH03175734A (en) | 1991-07-30 |
Family
ID=18072312
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1316016A Pending JPH03175734A (en) | 1989-12-04 | 1989-12-04 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03175734A (en) |
-
1989
- 1989-12-04 JP JP1316016A patent/JPH03175734A/en active Pending
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