JPH0317453Y2 - - Google Patents

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Publication number
JPH0317453Y2
JPH0317453Y2 JP16951384U JP16951384U JPH0317453Y2 JP H0317453 Y2 JPH0317453 Y2 JP H0317453Y2 JP 16951384 U JP16951384 U JP 16951384U JP 16951384 U JP16951384 U JP 16951384U JP H0317453 Y2 JPH0317453 Y2 JP H0317453Y2
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JP
Japan
Prior art keywords
signal
input
level
circuit
pnp transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP16951384U
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Japanese (ja)
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JPS6185922U (en
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Priority to JP16951384U priority Critical patent/JPH0317453Y2/ja
Publication of JPS6185922U publication Critical patent/JPS6185922U/ja
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Expired legal-status Critical Current

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Description

【考案の詳細な説明】 (イ)産業上の利用分野 本考案は、VTR(磁気記録再生装置)に用いら
れるRFコンバータ等に最適なFM変調回路に係
り、特に該FM変調回路の動作開始時の特性を改
善したFM変調器の入力回路に関する。
[Detailed explanation of the invention] (a) Industrial application field The present invention relates to an FM modulation circuit that is most suitable for an RF converter used in a VTR (magnetic recording/reproduction device), and especially when the FM modulation circuit starts operating. This invention relates to an input circuit for an FM modulator with improved characteristics.

(ロ)従来の技術 一般にVTRにおいては、出力を通常のテレビ
受像機のアンテナ端子に加え、受像回路に入力す
るため、高周波信号に変換しなければならず、
RFコンバータ(又はモジユレータ)と呼ばれる
変換器が使用される。
(B) Prior art In general, in a VTR, the output is added to the antenna terminal of a normal television receiver and input to the image receiving circuit, so it must be converted into a high frequency signal.
A converter called an RF converter (or modulator) is used.

基本的にはNTSC方式の場合オーデイオ信号で
変調した中心周波数が4.5MHzのFM波とビデオ
AM信号とを加え合せて、この信号で所定のRF
信号(VHF又はUHF信号)を振幅変調し、帯域
フイルタを通して出力している。
Basically, in the case of the NTSC system, an FM wave with a center frequency of 4.5MHz modulated by an audio signal and a video
AM signal is added to the specified RF signal.
The signal (VHF or UHF signal) is amplitude modulated and output through a bandpass filter.

そこで斯るRFコンバータには近年NTSC方式
の場合、4.5MHzの電圧制御発振回路(VOC)振
幅変調YAM)回路を内蔵したICが多用され、そ
の外部に4.5MHzの並列共振回路、映像搬送波用
のSAWレゾネータ等を接続する構成が採用され
ている。
Therefore, in recent years, in the case of the NTSC system, such RF converters often use ICs with a built-in 4.5MHz voltage-controlled oscillator (VOC) amplitude modulation YAM) circuit, and an external 4.5MHz parallel resonant circuit and a video carrier wave. A configuration that connects a SAW resonator, etc. is adopted.

その一例として、東京三洋電機(株)半導体事
業部発行の「三洋半導体ニユーズNo.1488」に掲載
されているLA7015Nの等価回路ブロツク図が上
げられ、オーデイオ信号の入力端子(ピン)に
対して結合コンデンサが接続されている。
As an example, the equivalent circuit block diagram of the LA7015N published in "Sanyo Semiconductor News No. 1488" published by the Semiconductor Division of Tokyo Sanyo Electric Co., Ltd. is listed, and it is connected to the input terminal (pin) of the audio signal. A capacitor is connected.

前記構成を第3図を用いて説明すると、制御信
号が印加される制御端子1は結合コンデンサ2を
介して例えばFM変調用の電圧制御発振回路(以
下VOCと称する)3に接続されている。ここで
該VCO3には所定の直流電圧E1及びE2をバイア
ス電圧として所定のダイナミツクレンジを得てい
る。前記VCOの第3図における右側の基準電圧
としてのE2に対応する直流電源は、電源スイツ
チのオン、オフに直ちに追従するが、同図左側の
制御側は、結合コンデンサ2が通常数μFに設定
されているため、制御端子1の電位の上昇、下降
に時間がかかり、これに伴つて制御端子1の電位
と基準電位との差が時間的に変動することから発
振周波数が安定しない。特に電源スイツチのオン
時安定状態に達するまでの時間を短縮しようとす
ると前記コンデンサの値を小さくすれば良いが、
これではS/Nが劣化する。
The above configuration will be explained with reference to FIG. 3. A control terminal 1 to which a control signal is applied is connected via a coupling capacitor 2 to, for example, a voltage controlled oscillation circuit (hereinafter referred to as VOC) 3 for FM modulation. Here, the VCO 3 has a predetermined dynamic range by using predetermined DC voltages E 1 and E 2 as bias voltages. The DC power supply corresponding to E 2 as the reference voltage on the right side of the VCO in Figure 3 immediately follows the on/off of the power switch, but on the control side on the left side of the figure, the coupling capacitor 2 is usually several μF. Because of this setting, it takes time for the potential of the control terminal 1 to rise and fall, and as a result, the difference between the potential of the control terminal 1 and the reference potential fluctuates over time, making the oscillation frequency unstable. In particular, if you want to shorten the time it takes to reach a stable state when the power switch is turned on, you can reduce the value of the capacitor.
This degrades the S/N ratio.

(ハ)考案が解決しようとする問題点 前述の如く、従来例においては電源スイツチの
オン、オフに伴う追随速度の差により発振周波数
の不安定なことから、例えばRFコンバータの場
合正常なFM出力が得られず、前記コンデンサが
所定の電位まで充電されて初めて正常な動作を前
記VCOが開始するという問題点がある。
(c) Problems to be solved by the invention As mentioned above, in the conventional example, the oscillation frequency is unstable due to the difference in tracking speed when the power switch is turned on and off, so for example, in the case of an RF converter, normal FM output There is a problem in that the VCO does not start normal operation until the capacitor is charged to a predetermined potential.

又信号の入力端子がある直流電位をもつている
ようなVCOは電源電圧が急激に生じたり、電源
に大きなリツプルが重畳すると前記端子の電位が
変動して入力信号に加算され、結果的にポツプ音
を生じたり、S/Nを劣化させている。又これら
を解決する方法として時定数を小さくする方法が
あるがこれでは低域での周波数特性が悪くなると
いう新たな欠点が生じる。
In addition, for a VCO whose signal input terminal has a DC potential, if the power supply voltage suddenly occurs or a large ripple is superimposed on the power supply, the potential of the terminal changes and is added to the input signal, resulting in a pop-up. This may cause noise or degrade S/N. In addition, one method to solve these problems is to reduce the time constant, but this causes a new drawback that the frequency characteristics in the low range deteriorate.

(ニ)問題点を解決するための手段 本考案は前記欠点を除去する為に、つまり低域
でのf特を劣化させずに電源変動時(電源印加時
もしくはリツプルがのつている時)のVCOの発
振周波数を安定させる為にレベルシフタ及び入力
段のPNPトランジスタ及びそのベースと接続し
ている接地抵抗により制御端子を接地電位に設定
する構成にする。
(d) Means for solving the problem The present invention was developed in order to eliminate the above-mentioned drawbacks, that is, when the power supply fluctuates (when power is applied or when ripples are present) without deteriorating the f-characteristic in the low range. In order to stabilize the oscillation frequency of the VCO, the control terminal is set to the ground potential using a level shifter, a PNP transistor in the input stage, and a grounding resistor connected to its base.

(ホ)作用 本考案の構成における制御端子は電源電圧が変
動してもつまり電源が印加された直後でも電源が
リツプル変動していても制御端子は接地電位にあ
る為結合コンデンサ及び接地抵抗による充放電時
間は零となり、これら変動が入力信号には加算さ
れず、電源が印加された直後でも発振周波数は直
ちに安定状態になる。また電源リツプル変動に対
してもS/Nが良好である。
(E) Effect The control terminal in the configuration of the present invention is at the ground potential even if the power supply voltage fluctuates, that is, even if the power supply is rippled or fluctuated immediately after the power is applied, the control terminal is at the ground potential, so it is charged by the coupling capacitor and the ground resistance. The discharge time becomes zero, these fluctuations are not added to the input signal, and the oscillation frequency immediately becomes stable even immediately after power is applied. Furthermore, the S/N ratio is good even with respect to power supply ripple fluctuations.

(ヘ)実施例 図面に従つて本考案を説明すると第1図は本考
案のFM変調器の入力回路の基本構成図、第2図
は同回路の一実施例を示す回路図で、図面におい
て、第3図における構成素子と同一のものについ
ては同一番を付してあり4,5は接地用抵抗、
6,7は前記接地抵抗4,5が接続された第1及
び第2の入力トランジスタ、8,9は入力を直線
的にシフトするレベルシフタ,10,11,1
2,13,14,15は定電流源、16はエミツ
タ抵抗、17,18は各々発振部19を有する電
圧制御発振器3を構成する第1及び第2のトラン
ジスタ、20,21は増幅段、22,23は移相
段、24はベクトル合成段、25は共振回路、2
6は直流電源端子を示す。
(F) Embodiment The present invention will be explained with reference to the drawings. Figure 1 is a basic configuration diagram of the input circuit of the FM modulator of the present invention, and Figure 2 is a circuit diagram showing an embodiment of the same circuit. , Components that are the same as those in Fig. 3 are numbered the same, and 4 and 5 are grounding resistors;
6 and 7 are first and second input transistors to which the grounding resistors 4 and 5 are connected; 8 and 9 are level shifters that linearly shift the input; 10, 11, and 1;
2, 13, 14, 15 are constant current sources; 16 is an emitter resistor; 17, 18 are first and second transistors each forming a voltage controlled oscillator 3 having an oscillation section 19; 20, 21 are amplifier stages; 22 , 23 is a phase shift stage, 24 is a vector synthesis stage, 25 is a resonant circuit, 2
6 indicates a DC power supply terminal.

今電源スイツチオフの状態から、電源スイツチ
をオンにし、結合コンデンサ2の電荷がゼロの状
態で、前記電源スイツチオンに伴つて直流電源端
子26の電圧は即座に+VCCに達し、各トランジ
スタ6,7,8,9,17,18に電源が供給さ
れる。このとき第1及び第2の入力トランジスタ
6,7はいずれもPNPトランジスタでベースが
抵抗4,5で接地されているため、前記第1の入
力トランジスタ6,7と、レベルシフタ8,9は
直ちにオンになつて第1のトランジスタ17及び
第2のトランジスタ18の各ベースは即座に所定
の電位になりかつ等しくなる。オフになつている
ので、制御端子1に一端が接続された結合コンデ
ンサ2は仮に大きい容量値に設定した場合でも制
御端子1に接地電位に保たれ、発振部19におけ
るフリーラン周波数に直ちに安定する。例えば
NTSC方式の信号処理をする際の、共振回路25
で発生する4.5MHzに即座に安定する。
Now, when the power switch is turned on from the power switch off state, and the charge on the coupling capacitor 2 is zero, the voltage at the DC power supply terminal 26 immediately reaches +V CC as the power switch is turned on, and each transistor 6, 7, Power is supplied to 8, 9, 17, and 18. At this time, since the first and second input transistors 6 and 7 are both PNP transistors whose bases are grounded through resistors 4 and 5, the first input transistors 6 and 7 and the level shifters 8 and 9 are immediately turned on. Then, the bases of the first transistor 17 and the second transistor 18 immediately reach a predetermined potential and become equal. Since it is turned off, even if the coupling capacitor 2 whose one end is connected to the control terminal 1 is set to a large capacitance value, the control terminal 1 is kept at the ground potential, and the free run frequency in the oscillator 19 is immediately stabilized. . for example
Resonant circuit 25 for NTSC signal processing
It instantly stabilizes to 4.5MHz, which occurs at

従つて本考案回路は、基本的にFM変調器を構
成するVCO3の制御端子側は第1図に示す通り
ゼロバイアス設定にしておき、結合コンデンサ2
の充電時間をゼロにしてVCOをフリーラン周波
数にて安定発振させる。
Therefore, in the circuit of the present invention, the control terminal side of VCO3, which basically constitutes the FM modulator, is set to zero bias as shown in Figure 1, and the coupling capacitor 2 is set to zero bias.
Set the charging time to zero to allow the VCO to oscillate stably at a free-run frequency.

次に前記結合コンデンサ2は制御端子1に加わ
る制御信号が加わつたとき、該制御信号に応じて
第1及び第2の入力トランジスタ17,18を介
して増幅段20,21にその信号が加わり、所定
のFM信号が生成される。
Next, when a control signal is applied to the control terminal 1, the coupling capacitor 2 applies the signal to the amplification stages 20 and 21 via the first and second input transistors 17 and 18 in accordance with the control signal, A predetermined FM signal is generated.

(ト)考案の効果 本考案によれば、先ず電源スイツチオン時従来
のように制御端子に接続された結合コンデンサが
充電される時間は問題となることなく、VCOは
直ちにフリーラン周波数に安定化され、また電源
リツブル変動においても結合コンデンサの充放電
時間が零となる。つまり上記リツプル変動に対し
て電位が一定に保たれフリーラン周波数を安定化
させる。以上の様に、結合コンデンサの容量値を
大きく選ぶことができるので、特に低周波信号で
のFM変調時、周波数特性の向上が図れる利点が
得られ、本考案回路はVTRのRFモジユレータ等
FM変調器に極めて有用である。
(g) Effects of the invention According to the invention, first, when the power is switched on, the time required for charging the coupling capacitor connected to the control terminal as in the conventional case does not become a problem, and the VCO is immediately stabilized to the free-run frequency. , the charging and discharging time of the coupling capacitor becomes zero even when the power supply ripples fluctuate. In other words, the potential is kept constant against the ripple fluctuations, and the free run frequency is stabilized. As described above, since the capacitance value of the coupling capacitor can be selected to be large, it has the advantage of improving frequency characteristics, especially during FM modulation with low frequency signals.
Extremely useful for FM modulators.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案のFM変調回路の基本構成図、
第2図は同回路の一実施例を示す回路図、第3図
は従来の同回路の基本構成図を示す。 主な図番の説明、1……制御端子、2……結合
コンデンサ、3……VCO、4,5……接地用抵
抗、6,7……第1及び第2の入力トランジス
タ、8,9……第2の入力トランジスタ、17…
…第1のトランジスタ、18……レベルシフタ。
Figure 1 is a basic configuration diagram of the FM modulation circuit of the present invention.
FIG. 2 is a circuit diagram showing an embodiment of the same circuit, and FIG. 3 is a conventional basic configuration diagram of the same circuit. Explanation of main figure numbers, 1... Control terminal, 2... Coupling capacitor, 3... VCO, 4, 5... Grounding resistor, 6, 7... First and second input transistor, 8, 9 ...Second input transistor, 17...
...First transistor, 18...Level shifter.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 増幅段、移相段、ベクトル合成段及び共振回路
を有する発振部と、前記発振部の前記増幅段に接
続された差動増幅器と、ベースが抵抗を介して接
地されるとともに該ベースに入力信号源からの信
号が結合コンデンサを介して印加される第1の
PNPトランジスタと、該第1のPNPトランジス
タの出力信号をレベルシフトして、前記差動増幅
器の一方の入力端子に印加する第1のレベルシフ
タと、ベースが抵抗を介して接地される第2の
PNPトランジスタと、該第2のPNPトランジス
タの出力信号をレベルシフトして、前記差動増幅
器の他方の入力端子に印加する第2のレベルシフ
タとから成ることを特徴とするFM変調器の入力
回路。
an oscillation section having an amplification stage, a phase shift stage, a vector synthesis stage, and a resonant circuit, a differential amplifier connected to the amplification stage of the oscillation section, a base of which is grounded via a resistor and an input signal is connected to the base. the first to which the signal from the source is applied via a coupling capacitor;
a PNP transistor, a first level shifter that level-shifts the output signal of the first PNP transistor and applies it to one input terminal of the differential amplifier; and a second level shifter whose base is grounded via a resistor.
An input circuit for an FM modulator, comprising a PNP transistor and a second level shifter that level-shifts the output signal of the second PNP transistor and applies the level-shifted signal to the other input terminal of the differential amplifier.
JP16951384U 1984-11-08 1984-11-08 Expired JPH0317453Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16951384U JPH0317453Y2 (en) 1984-11-08 1984-11-08

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16951384U JPH0317453Y2 (en) 1984-11-08 1984-11-08

Publications (2)

Publication Number Publication Date
JPS6185922U JPS6185922U (en) 1986-06-05
JPH0317453Y2 true JPH0317453Y2 (en) 1991-04-12

Family

ID=30727244

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16951384U Expired JPH0317453Y2 (en) 1984-11-08 1984-11-08

Country Status (1)

Country Link
JP (1) JPH0317453Y2 (en)

Also Published As

Publication number Publication date
JPS6185922U (en) 1986-06-05

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