JPH03171942A - Data transmitting and receiving system - Google Patents
Data transmitting and receiving systemInfo
- Publication number
- JPH03171942A JPH03171942A JP30927689A JP30927689A JPH03171942A JP H03171942 A JPH03171942 A JP H03171942A JP 30927689 A JP30927689 A JP 30927689A JP 30927689 A JP30927689 A JP 30927689A JP H03171942 A JPH03171942 A JP H03171942A
- Authority
- JP
- Japan
- Prior art keywords
- test
- signal
- circuit
- data transmitting
- test control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 22
- 238000000034 method Methods 0.000 claims description 3
- 230000005540 biological transmission Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Landscapes
- Time-Division Multiplex Systems (AREA)
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明は,データ送受信方式に関し,特に複数チャネル
のデータ信号を多重化して送受信するデータ送受信方式
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transmission/reception system, and more particularly to a data transmission/reception system in which data signals of multiple channels are multiplexed and transmitted/received.
[従来の技術]
従来,この種のデータ送受信装置は,各チャネル毎に折
返し試験が可能なように,各チャネル部の受信データを
監視し,試験信号が検出されると試験動作を行っている
。[Prior Art] Conventionally, this type of data transmitting/receiving device monitors the received data of each channel so that loopback tests can be performed for each channel, and performs a test operation when a test signal is detected. .
また多重化された高速リンクの折返し試験のように共通
的部分の制御も同様に行っていた。In addition, common parts such as loopback tests of multiplexed high-speed links were also controlled in the same way.
〔発明が解決しようとする課題コ
しかし,従来の構成では各チャネル部のデータ信号速度
が異なる場合に,高速なチャネルで他の低速チャネルよ
り早く試験信号が検出され,低速チャネルが試験信号を
検出する前に共通部の高速多重化リンクが折返され,こ
れによる影響で受信データ信号に符号誤りが発生し,低
速チャネルの試験信号検出が失敗し,低速チャネル側に
おいて試験状態であることを認識することが遅れるとい
う欠点があった。[Problem to be solved by the invention] However, in the conventional configuration, when the data signal speed of each channel section is different, the test signal is detected in the high-speed channel earlier than the other low-speed channels, and the low-speed channel detects the test signal. The high-speed multiplex link in the common section is looped back before the end of the process, and this causes a code error in the received data signal, causing test signal detection on the low-speed channel to fail, and the low-speed channel side recognizes that it is in a test state. The drawback was that things were delayed.
そこで,本発明の技術的課題は上記欠点に鑑み,全チャ
ネルとも試験状態を認識してから試験を行うデータ送受
信方式を提供することである。SUMMARY OF THE INVENTION In view of the above-mentioned drawbacks, a technical problem of the present invention is to provide a data transmission/reception system that performs a test after recognizing the test status of all channels.
[課題を解決するための手段]
本発明によれば,I数チャネルのデータ信号を多重化し
て送受信し,対向するデータ送受信装置から試験制御信
号を前記チャネル毎に受信するデータ送受信方式におい
て,前記チャネルの全てが検出された後に,折返し試験
を実行することを特徴とするデータ送受信方式が得られ
る。[Means for Solving the Problems] According to the present invention, in a data transmission/reception method in which data signals of I number of channels are multiplexed and transmitted/received, and a test control signal is received for each channel from an opposing data transmission/reception device, A data transmission and reception scheme is obtained which is characterized in that a loopback test is performed after all of the channels have been detected.
本発明によれば,複数チャネルのデータ信号を多重化し
て送受信し.対向するデータ送受信装置から遠隔試験制
御信号をチャネル毎に受信するデータ送受信装置におい
て多重化部と1各チャネルブの遠隔信号検出回路と,こ
れらの検出回路出力信号を入力とする試験制御回路と,
試験制御回路出力信号により多重化された高速リンクを
対向装置側へ折返す折返し回路とにより構成され,全て
の遠隔試験制御信号検出回路出力がONの場合に.折返
し制御回路を動作させることを特徴とするデータ送受信
装置が得られる。According to the present invention, data signals of multiple channels are multiplexed and transmitted/received. A data transmitting/receiving device that receives a remote test control signal for each channel from an opposing data transmitting/receiving device includes a multiplexing unit, a remote signal detection circuit for each channel, and a test control circuit that receives output signals from these detection circuits as input;
It consists of a return circuit that loops back the high-speed link multiplexed by test control circuit output signals to the opposite device side, and when all remote test control signal detection circuit outputs are ON. A data transmitting/receiving device characterized by operating a return control circuit is obtained.
即ち,本発明は,各チャネル毎の試験信号検出回路と.
各試験信号検出回路出力を入力とする試験制御回路と,
該試験制ga回路により制御される折返し回路とを有す
ることを特徴とするデータ送受信装置が得られる。That is, the present invention includes a test signal detection circuit for each channel.
A test control circuit that receives each test signal detection circuit output as input;
A data transmitting/receiving device characterized in that it has a folding circuit controlled by the test-based GA circuit is obtained.
[実施例]
次に,本発明の実施例について図面を参照して説明する
。[Example] Next, an example of the present invention will be described with reference to the drawings.
第1図は本発明の一実施例である。10は折返し回路.
11は多重化部.12は試験信号検出回路である。13
は試験$1御回路である。本実施例では4チャネル多重
化した場合を示している。各チャネルのデータ信号14
〜17は,各々試験信号検出回路12で監視され,デー
タ信号中に試験信号が検出された場合は検出信号18〜
21を試験制御回路13へ出力する。試験制御回路13
は検出信号18〜21の全信号が検出状態となった場合
に,信号22を折返し回路10へ出力する。FIG. 1 shows an embodiment of the present invention. 10 is a folding circuit.
11 is a multiplexing section. 12 is a test signal detection circuit. 13
is the test $1 control circuit. This embodiment shows a case where four channels are multiplexed. Data signal 14 for each channel
~17 are each monitored by the test signal detection circuit 12, and when a test signal is detected in the data signal, the detection signal 18~
21 is output to the test control circuit 13. Test control circuit 13
outputs the signal 22 to the return circuit 10 when all of the detection signals 18 to 21 are in the detection state.
折近し回路10は信号22を受信した場合に,対向する
データ送受信装置(図示せず)に対して折返しループを
構成する。When the folding circuit 10 receives the signal 22, it forms a folding loop with respect to the opposing data transmitting/receiving device (not shown).
第2図は試験状態での対向する両データ送受信装置及び
折返しループの構成(27)を示す。FIG. 2 shows the configuration (27) of both opposing data transmitting/receiving devices and the return loop in a test state.
tjS3図はタイムチャートを示す。tjS3 diagram shows a time chart.
第3図に示すように,時刻Iから各チャネルが同時に試
験信号30〜33の送信を開始した場合は,各チャネル
の速度差によって時刻n, III, IV,■に受信
側で試験信号が検出される。As shown in Figure 3, if each channel starts transmitting test signals 30 to 33 at the same time from time I, the test signals will be detected on the receiving side at times n, III, IV, and ■ due to the speed difference between each channel. be done.
従って,!&も速度が速く,検出時刻の早い,チャネル
Dの検出信号21で折返しを行った場合は,従来は.他
チャネルA−Cにデータ符号誤りが発生し,試験信号検
出が出来ない場合があるが,本実施例によれば時刻Vで
折返しが行われるれので1既に他チャネルでの検出は終
了している為,上記のような問題はない。Therefore,! If & is looped back using the detection signal 21 of channel D, which has a fast speed and an early detection time, conventionally. A data code error may occur in other channels A to C, and test signal detection may not be possible. However, according to this embodiment, since loopback is performed at time V, detection on other channels has already ended. Therefore, there are no problems like the above.
[発明の効果]
以上説明したように本発明は,各チャネル部の試験信号
検出回路出力を試験制御回路に入力し,全チャネルで試
験信号が検出された後.折返しを実行する為各チャネル
の速度差による検出時点の差によるデータ誤りの発生が
なく,全チャネルとも試験状態を認識してから試験が行
うことができるという効果がある。[Effects of the Invention] As explained above, the present invention inputs the test signal detection circuit output of each channel section to the test control circuit, and after the test signal is detected on all channels. Since loopback is performed, data errors do not occur due to differences in detection times due to speed differences between channels, and the test can be performed after recognizing the test status of all channels.
第1図は本発明の一実施例,第2図はシステム構戊図,
第3図はタイムチャートを示す。
lO・・・折返し回路,11・・・多重化部、12・・
・試験信号検出回路,13・・・試験制御回路,14〜
17・・・CHA−Dのデータ信号(受信出力).18
〜21・・・CHA−Dの試験信号検出出力.22・・
・折返し制御信号,25・・・データ送受信装置,26
・・・多重化高速リンク,27・・・多重化高速リンク
の折返し構或,、30〜33・・・CHA−Dの試験信
号.1 −V・・・時刻
■・・・送信開始時刻Figure 1 is an embodiment of the present invention, Figure 2 is a system configuration diagram,
FIG. 3 shows a time chart. lO... Return circuit, 11... Multiplexing unit, 12...
・Test signal detection circuit, 13...Test control circuit, 14~
17...CHA-D data signal (reception output). 18
~21... CHA-D test signal detection output. 22...
・Return control signal, 25...Data transmitting/receiving device, 26
... Multiplexed high-speed link, 27... Folding structure of multiplexed high-speed link, 30-33... CHA-D test signal. 1 -V...Time■...Transmission start time
Claims (1)
対向するデータ送受信装置から試験制御信号を前記チャ
ネル毎に受信するデータ送受信方式において、前記チャ
ネルの全てが検出された後に、折返し試験を実行するこ
とを特徴とするデータ送受信方式。 2)複数チャネルのデータ信号を多重化して送受信し、
対向するデータ送受信装置から遠隔試験制御信号をチャ
ネル毎に受信するデータ送受信装置において多重化部と
、各チャネル部の遠隔信号検出回路と、これらの検出回
路出力信号を入力とする試験制御回路と、試験制御回路
出力信号により多重化された高速リンクを対向装置側へ
折返す折返し回路とにより構成され、全ての遠隔試験制
御信号検出回路出力がONの場合に、折返し制御回路を
動作させることを特徴とするデータ送受信装置。[Claims] 1) multiplexing and transmitting/receiving data signals of multiple channels;
A data transmitting/receiving method in which a test control signal is received for each channel from an opposing data transmitting/receiving device, wherein a return test is executed after all of the channels are detected. 2) Multiplex and transmit/receive data signals of multiple channels,
A multiplexing section in a data transmitting/receiving device that receives a remote test control signal for each channel from an opposing data transmitting/receiving device, a remote signal detection circuit of each channel section, and a test control circuit that receives output signals from these detection circuits as input; It is composed of a return circuit that returns the high-speed link multiplexed by the test control circuit output signal to the opposite device side, and is characterized in that the return control circuit is operated when all remote test control signal detection circuit outputs are ON. data transmitting and receiving device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP30927689A JPH03171942A (en) | 1989-11-30 | 1989-11-30 | Data transmitting and receiving system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP30927689A JPH03171942A (en) | 1989-11-30 | 1989-11-30 | Data transmitting and receiving system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03171942A true JPH03171942A (en) | 1991-07-25 |
Family
ID=17991049
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP30927689A Pending JPH03171942A (en) | 1989-11-30 | 1989-11-30 | Data transmitting and receiving system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03171942A (en) |
-
1989
- 1989-11-30 JP JP30927689A patent/JPH03171942A/en active Pending
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