JPH03171651A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH03171651A
JPH03171651A JP1310264A JP31026489A JPH03171651A JP H03171651 A JPH03171651 A JP H03171651A JP 1310264 A JP1310264 A JP 1310264A JP 31026489 A JP31026489 A JP 31026489A JP H03171651 A JPH03171651 A JP H03171651A
Authority
JP
Japan
Prior art keywords
package
irregularities
metal
resistance
thermal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1310264A
Other languages
Japanese (ja)
Inventor
Hiroyoshi Ohira
大平　廣吉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP1310264A priority Critical patent/JPH03171651A/en
Publication of JPH03171651A publication Critical patent/JPH03171651A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To enable a plastic package to be improved in heat dissipating property and lessened in thermal resistance so as to obtain the package high in resistance to thermal stress and low in high frequency noise by a method wherein irregularities are provided to the resin part of the plastic package, and a metal capable of being provided in one piece with the irregularities is pasted on the front and the rear of the plastic package respectively. CONSTITUTION:A mold is so contrived as to form a package provided with irregularities through a transfer molding method. At this point, the recessed parts are formed as deep as possible to enable a chip to dissipate heat well so far as they do not advsersely affect the chip and bonding wires. Metal which is excellent in thermal conductivity and capable of being provided in one piece with the irregularities is prepared, and it is made to adhere to the irregularities with an adhesive agent of polyimide or the like which is comparatively excellent in thermal conductivity, high in heat resistance, and high in adhesion to the irregularities concerned. By this setup, the package can be made small in thermal resistance.

Description

【発明の詳細な説明】[Detailed description of the invention] 【産業上の利用分野】[Industrial application field]

本発明は、半導体装置、特に、熱抵抗が低く、実装時の
熱ストレスに強い，また．ＩＣから発生する放射ノイズ
を低減する効果を持つプラスチックパッケージに関する
． 〔発明の概要〕 半導体装置において、プラスチックパッケージの表面と
裏面に凹凸をつくり表面積を大きくし、この凹凸と一体
化できる形状の放熱性のよい金属を裏面と表面から張り
付けた構造のパッケージを提供することにより、パッケ
ージの熱抵抗を小さくし、同時に実装時の熱ストレスに
よるパッケージクラックの低減、樹脂応力による機能不
良の低減を図るものである． 〔従来の技術｝ 従来の半導体装置は、基本的には、第３図にような構造
をしており、パッケージ全体が樹脂で形成されていた．The present invention is suitable for semiconductor devices, especially those having low thermal resistance and strong resistance to thermal stress during mounting. This article relates to a plastic package that has the effect of reducing radiation noise generated from ICs. [Summary of the invention] To provide a package for a semiconductor device having a structure in which unevenness is created on the front and back sides of a plastic package to increase the surface area, and a metal with good heat dissipation and a shape that can be integrated with the unevenness is pasted from the back and front sides. This reduces the thermal resistance of the package, and at the same time reduces package cracks caused by thermal stress during mounting, as well as functional defects caused by resin stress. [Prior art] A conventional semiconductor device basically had a structure as shown in Figure 3, and the entire package was made of resin.

【発明が解決しようとする課題】[Problem to be solved by the invention]

しかし、前述の従来技術では、パッケージからの放熱が
パッケージ樹脂からの放熱で律速されるため、熱伝導率
が金属やセラミックに比べ小さな樹脂を用いた従来構造
のパッケージでは、熱抵抗がかさなり高く、高消費電力
ＩＣ用パッケージとしては不適であった． また，高周波用ＩＣパッケージとしても、ＩＣから発生
する高周波の放射を防ぐことができず，外部回路がノイ
ズにより誤動作をするという問題点を有していた． 本発明は、このような問題点を解決するちので、その目
的とするところは、放熱の妨げとなっている樹脂部に、
チップ部のできるだけ近くまで凹凸をつけ、この凹凸部
と一体化できる形状の熱伝導度のよい金属を裏面と表面
から張りつけ、熱放散をよくしパッケージの熱抵抗を下
げるとともに、この金属により実装時の熱ストレスに強
い、高周波ノイズの発生の少ないパッケージを提供する
ことにある．However, in the above-mentioned conventional technology, the rate of heat radiation from the package is determined by the heat radiation from the package resin, so a package with a conventional structure using a resin whose thermal conductivity is lower than that of metal or ceramic has a very high thermal resistance. It was unsuitable as a package for high power consumption IC. Furthermore, even as a high-frequency IC package, it is not possible to prevent the radiation of high-frequency waves generated from the IC, resulting in the problem that external circuits may malfunction due to noise. The present invention aims to solve such problems, and its purpose is to remove
The unevenness is formed as close as possible to the chip area, and a metal with good thermal conductivity that is shaped so that it can be integrated with the unevenness is pasted from the back and front surface to improve heat dissipation and lower the thermal resistance of the package. The objective is to provide a package that is resistant to thermal stress and generates little high-frequency noise.

【課題を解決するための手段〕[Means to solve problems]

本発明の半導体装置はプラスチックパッケージの樹脂部
分に凹凸をつけ、その凹凸と一体化できる金属を裏面と
表面から張りつけることを特徴とするちのである． 【作　用】 本発明の作用を述べれば、樹脂の凹凸部に熱伝導性の高
い金属が埋め込まれた形となっているため、チップから
発生した熱はこの金属を通し、て外界に放熱される．こ
のため、パッケージの熱抵抗をきわめて小さくすること
ができる．また、本発明の構造では、表面と裏面が金属
で覆われているため、パッケージの吸湿をおさえること
ができる．また、赤外綿リフロ一等による全体加熱実装
では、表面の金属が赤外線を反射し、パッケージの温度
上昇を抑える効果と、熱膨張率の小さな金属が樹脂の熱
による変形を抑える効果から、パッケージのクラックを
防止することができる．また，表面と裏面の金属をシー
ルド板として使用することにより、ＩＣから発生する高
周波ノイズの放射を低減することができる．The semiconductor device of the present invention is characterized in that the resin part of the plastic package is made uneven, and a metal that can be integrated with the unevenness is pasted from the back and front surface. [Function] The function of the present invention is that since a highly thermally conductive metal is embedded in the uneven parts of the resin, the heat generated from the chip is radiated to the outside world through this metal. Ru. Therefore, the thermal resistance of the package can be made extremely low. Furthermore, in the structure of the present invention, the front and back surfaces are covered with metal, so moisture absorption of the package can be suppressed. In addition, in overall heating mounting using infrared cotton reflow, etc., the metal on the surface reflects infrared rays and has the effect of suppressing the temperature rise of the package, and the metal with a small coefficient of thermal expansion has the effect of suppressing the deformation of the resin due to heat. can prevent cracks. Furthermore, by using the metal on the front and back sides as shield plates, it is possible to reduce the radiation of high frequency noise generated from the IC.

【実　施　例】【Example】

以下、本発明について実施例に基づき説明する．第１図
は本発明のパッケージの断面図であって、ｌは放熱金属
、２は半導体チップ（ＩＣ）、３はボンデイングワイヤ
ー、４はパッケージ樹脂（エボキシ樹脂）、５はリード
フレームである．次に、本発明の半導体装置の製造方法
について述べる． 先ず、トランスファモールド法を用い、金型を工夫する
ことにより、第２図（ａ）のような凹凸形状のパッケー
ジを形成する．この時の凹部はチップからの放熱を良く
するため，チップやボンディングワイヤーに対して悪い
影響のでない範囲で、できる限り深く、大きくとる． 次に、第２図（ｂ）のように、（ａ）の凹凸部に一体化
できる形状の熱伝導率のよい金属を準備し，（ａ）と（
ｂ）の双方に強い密着性のある、熱伝導性の比較的よい
、耐熱性の高いポリイミド等の接着剤で（ａ）と（ｂ）
を接着する．これら一連の工程は、従来のトランスファ
モールド法に、この金属板の接着工程を追加するだけで
済むという利点を持っている。また、最終のパッケージ
形状が，従来のＪＥＤＥＣ等で定められている半導体装
置と同一になるように形状を設計すれば、従来の半導体
装置と全く同一の方法で使用することができ、効率的で
ある。 ［発明の効果］ 本発明の効果は、パッケージ樹脂に凹凸をつけ、その凹
凸と一体化できる金属をパッケージの裏面と表面から張
りつけることにより、熱抵抗を小さくする事ができる．
加えて、実装時の急激な熱ストレスによるパッケージク
ラックを抑制することができるため、工程不良率の減少
および信頼性の向上に寄与する． また、表面と裏面の金属部をグランドと接続することに
より、ＩＣから発生する高周波ノイズの放射を低減する
ことができる．The present invention will be explained below based on examples. FIG. 1 is a sectional view of the package of the present invention, where l is a heat dissipating metal, 2 is a semiconductor chip (IC), 3 is a bonding wire, 4 is a package resin (epoxy resin), and 5 is a lead frame. Next, a method for manufacturing a semiconductor device according to the present invention will be described. First, by using a transfer molding method and devising a mold, a package with an uneven shape as shown in Fig. 2(a) is formed. In order to improve heat dissipation from the chip, the recess should be made as deep and large as possible without adversely affecting the chip or bonding wire. Next, as shown in Figure 2(b), prepare a metal with good thermal conductivity that can be integrated into the uneven portion of (a), and
(a) and (b) with an adhesive such as polyimide that has strong adhesion, relatively good thermal conductivity, and high heat resistance for both (a) and (b).
Glue. This series of steps has the advantage that it is only necessary to add this metal plate bonding step to the conventional transfer molding method. In addition, if the final package shape is designed to be the same as that of semiconductor devices specified by conventional JEDEC, etc., it can be used in exactly the same way as conventional semiconductor devices, making it more efficient. be. [Effects of the Invention] The effects of the present invention are that the thermal resistance can be reduced by forming unevenness on the package resin and attaching metal that can be integrated with the unevenness from the back and surface of the package.
In addition, it is possible to suppress package cracks caused by sudden thermal stress during mounting, which contributes to reducing process defect rates and improving reliability. Furthermore, by connecting the metal parts on the front and back sides to the ground, it is possible to reduce the radiation of high frequency noise generated from the IC.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明による半導体装置の主要部の断面図． 第２図（ａ）は本発明による半導体装置の、製造工程途
中のトランンスファモールド上がり時の断面図． 第２図（ｂ）は本発明による半導体装置の製造に使用す
る放熱用金属の断面図． 第２図（Ｃ）は本発明による半導体装置の製造に使用す
る放熱用金属の平面図． 第３図は従来の半導体装置の主要部の断面図．ｌ・・・
放熱用金属 ２・・・プラスチックモールド樹脂 （エボキシ樹脂） ３・・・ボンディングワイヤー（金線）４・・・半導体
チップ ５・・・リードフレーム 以 上FIG. 1 is a cross-sectional view of the main parts of a semiconductor device according to the present invention. FIG. 2(a) is a cross-sectional view of the semiconductor device according to the present invention when the transfer mold is removed during the manufacturing process. FIG. 2(b) is a cross-sectional view of a heat dissipating metal used in manufacturing a semiconductor device according to the present invention. FIG. 2(C) is a plan view of a heat dissipating metal used in manufacturing a semiconductor device according to the present invention. Figure 3 is a cross-sectional view of the main parts of a conventional semiconductor device. l...
Heat dissipation metal 2...Plastic mold resin (epoxy resin) 3...Bonding wire (gold wire) 4...Semiconductor chip 5...Lead frame or higher

Claims (1)

【特許請求の範囲】[Claims] プラスチックパッケージの放熱性を高めるため、パッケ
ージの表面と裏面の樹脂部に凹凸をつくり、その凹凸と
一体化できる金属をパッケージの裏面と表面から張り付
けた構造を有することを特徴とする半導体装置。A semiconductor device characterized by having a structure in which, in order to improve the heat dissipation of a plastic package, unevenness is created on the resin part of the front and back surfaces of the package, and metal that can be integrated with the unevenness is pasted from the back and front surfaces of the package.
JP1310264A 1989-11-29 1989-11-29 Semiconductor device Pending JPH03171651A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1310264A JPH03171651A (en) 1989-11-29 1989-11-29 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1310264A JPH03171651A (en) 1989-11-29 1989-11-29 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH03171651A true JPH03171651A (en) 1991-07-25

Family

ID=18003149

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1310264A Pending JPH03171651A (en) 1989-11-29 1989-11-29 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH03171651A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5703398A (en) * 1993-03-17 1997-12-30 Fujitsu Limited Semiconductor integrated circuit device and method of producing the semiconductor integrated circuit device
KR20030082178A (en) * 2002-04-17 2003-10-22 주식회사 칩팩코리아 Tebga package
JP2013258334A (en) * 2012-06-13 2013-12-26 Denso Corp Semiconductor device and manufacturing method of the same
WO2018168591A1 (en) * 2017-03-13 2018-09-20 株式会社村田製作所 Module

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5703398A (en) * 1993-03-17 1997-12-30 Fujitsu Limited Semiconductor integrated circuit device and method of producing the semiconductor integrated circuit device
KR20030082178A (en) * 2002-04-17 2003-10-22 주식회사 칩팩코리아 Tebga package
JP2013258334A (en) * 2012-06-13 2013-12-26 Denso Corp Semiconductor device and manufacturing method of the same
WO2018168591A1 (en) * 2017-03-13 2018-09-20 株式会社村田製作所 Module
US11171067B2 (en) 2017-03-13 2021-11-09 Murata Manufacturing Co., Ltd. Module having a sealing resin layer with radiating member filled depressions

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