JPH03163865A

JPH03163865A - Semiconductor integrated circuit device

Info

Publication number: JPH03163865A
Application number: JP2298235A
Authority: JP
Inventors: Kaoru Shibuya; 薫渋谷; Ichiro Kobayashi; 一郎小林
Original assignee: Toshiba Corp
Current assignee: Toshiba Corp
Priority date: 1990-11-02
Filing date: 1990-11-02
Publication date: 1991-07-15
Anticipated expiration: 2009-06-01
Also published as: JPH0642529B2

Abstract

PURPOSE:To contrive the inhibition of an increase in a chip size, which is accompanied by an increase in the current capacity of a buffer, by a method wherein the buffer transistors of a high-current input butter circuit are arranged nearer a power terminal than the buffer transistors of a low-current input buffer circuit and a power wiring is provided from the power terminal to the individual buffer circuits. CONSTITUTION:High-current input buffer transistors 13 and 14 are arranged nearer a power terminal 23 than low-current input buffer transistors 11 and 12. Accordingly, the dimensions of the transistors 13 and 14 can be made small by an amount that the fluctuation of the voltage of a power wiring 32 becomes small by a shortening of the wiring 32 between the terminal 23 and the high- current buffer transistors 13 and 14 and the wiring 32 can be made thin. Thereby, the inhibition of an increase in a chip size, which is accompanied by an increase in the current of a buffer, is contrived.

Description

【発明の詳細な説明】［発明の技術分野コ本発明は半導体集積回路装置に係り，特にそのバク７７
回路として電流容量が異なる２種類以上のバッファ回路
を有する半導体集積回路装置に関する。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device.
The present invention relates to a semiconductor integrated circuit device having two or more types of buffer circuits having different current capacities.

［発明の技術的背景コ半導体集積回路、たとえばＮチャンネルＭＯＳ型のＬＳ
Ｉ（大規模集積回路）では．　ＬＳＩ外部からの信号を
直接にＬＳＩ内部に収り入れないで，あるいはＬＳＩ内
部からの信号を直接にＬＳＩ外部に収り出さないで、入
力バッファあるいは出力バッフ了を介してＬＳＩ内部と
ＬＳＩ外部との信号のやり収りを行なっている。このよ
う女インターフェースとしてのバッファとこれに付属し
ている回路とをバッファ回路と呼ぶことにすれば．　Ｌ
ＳＩにおける上記パッ７ア回路以外の回鮎を内部ロジッ
クと呼ぶことができる。[Technical Background of the Invention] Semiconductor integrated circuits, such as N-channel MOS type LS
In I (large scale integrated circuit). Signals from outside the LSI are not directly input into the LSI, or signals from inside the LSI are not directly output to the outside of the LSI, but signals are connected between the inside of the LSI and the outside of the LSI via input buffers or output buffers. It is used to exchange and exchange signals. If we call this buffer as a female interface and the circuit attached to it a buffer circuit. L
Circuits other than the above-described passer circuit in the SI can be called internal logic.

このようなＬＳＩにおいて、通常はバッファ回路は外部
に大きな１Ｍ．流を供給してｋり，その電源配線の電圧
変動が大きな値になり，その変動が内部ロジックに大き
な影響を与えることを避けるための配慮から，バッファ
回路と内部ロジックとは電源が別々に供給されている。In such an LSI, the buffer circuit is usually a large 1M. The buffer circuit and internal logic are supplied with separate power supplies in order to avoid large voltage fluctuations in the power supply wiring that would have a large effect on the internal logic. has been done.

第ｌ図は、上述したようＩＬＳＩにおける出力バッファ
部の一部（たとえば電流引込側）を示すものであり，１
１かよびＪ２は通常の電流容量の出カバッファに釦ける
電流引込側のトランジスタ，１３および１４は大電流容
量の出力バッファにおける電流引込側のトランジスタ，
１５〜１８はこれらのトランジスタ１１〜１４を駆動す
るインバータ，１９〜２２は上記トランジスタ１１〜１
４の一端に接続される出力端子（パンド），２３は低電
位ｇｌ！ｌ電源ｖｓ８用の電源端子、２４はバッファ用
電源配線、２５〜２８はその抵抗分，２９は内部ロジッ
ク用電源配線，３０はその抵抗分である。FIG. 1 shows a part of the output buffer section (for example, the current sink side) in the ILSI as described above.
1 and J2 are transistors on the current sink side of a normal current capacity output buffer; 13 and 14 are transistors on the current sink side of a large current capacity output buffer;
15 to 18 are inverters for driving these transistors 11 to 14, and 19 to 22 are inverters for driving the transistors 11 to 1.
The output terminal (Pand) connected to one end of 4, 23, is at low potential gl! A power supply terminal for l power supply vs8, 24 is a buffer power supply wiring, 25 to 28 are its resistance, 29 is an internal logic power supply wiring, and 30 is its resistance.

ここで、電源端子２３から離れて配置された出力バッフ
ァ捷での電源配線２４による電圧降下を小ざ〈するため
に，この配線２４０幅を太〈してその抵抗分を小宮くす
るとか，出力バッファのトランジスタのデメンションを
大きくするような設計が施されている。第２図は．　Ｌ
ＳＩチク７°３ノに釦ける上記出力バッファ部の配置例
を示すものであり、大電流容量のトランジスタ１３．１
４は通常容量のトランジスタ１ｚ．Ｊｚよりも電源端子
２３から離れている。Here, in order to reduce the voltage drop due to the power supply wiring 24 at the output buffer wire located away from the power supply terminal 23, the width of this wiring 240 may be made thicker to reduce its resistance. The design is such that the dimensions of the buffer transistors are increased. Figure 2 is. L
This shows an example of the arrangement of the above output buffer section that can be pressed at 7 degrees 3 points of the SI, and has a large current capacity transistor 13.1.
4 is a normal capacity transistor 1z. It is further away from the power supply terminal 23 than Jz.

［背景技術の問題点」ところで，最近のように発光ダイオード等の駆動のため
に前記出力バッファ３２．３３として特に大電流容量が
必要となった場合，これ捷で以上に電源配線２４の太さ
および出力バッファ３２，３２０トランジスタのデメン
ションを大きくする必要に迫られ、集積回路チップサイ
ズが増大する要因となる。[Problems with the Background Art] By the way, recently, when a particularly large current capacity is required for the output buffers 32 and 33 to drive light emitting diodes, etc., the thickness of the power supply wiring 24 becomes larger than usual. In addition, it is necessary to increase the dimensions of the output buffers 32 and 320 transistors, which causes an increase in the integrated circuit chip size.

［発明の目的］本発明は上記の事情に鑑みてな々れたもので、バッファ
の大電流容量化に伴なうチップサイズの増大を極力少な
くし得ろ半導体集積回路装置を提供するものである。[Object of the Invention] The present invention was developed in view of the above circumstances, and it is an object of the present invention to provide a semiconductor integrated circuit device in which the increase in chip size due to the increase in the current capacity of the buffer can be minimized. .

［発明の概要］すなわち、本発明の半導体集積回路装置は、大電流の入
力バッファトランジスタを小電流の入力バッファトラン
ジスタよりも電源端子の近くに配置している。したがっ
て，電源端子と大電流バッファとの間の電源配線が従来
より短かくなり，これによって電源配線の電圧変動が小
さくなる分だけバッファトランジスタのデメンションを
小σ〈でき，′１た前記電源配糾が従来より細くて済み
，バッファの一層の大電流化に伴々うチップサイズの増
大が極力少なくて済む。[Summary of the Invention] That is, in the semiconductor integrated circuit device of the present invention, a large current input buffer transistor is arranged closer to a power supply terminal than a small current input buffer transistor. Therefore, the power supply wiring between the power supply terminal and the large current buffer is shorter than before, and the dimension of the buffer transistor can be reduced by the amount of voltage fluctuation in the power supply wiring reduced. The buffer can be made thinner than before, and the increase in chip size due to the higher current of the buffer can be minimized.

［発明の実施例コ以下、図面を参照して本発明の一実施例を詳細に説明す
る。第３図はＭＯＳ　型ＬＳＩの出力バッファ部の一部
（たとえば電流引込側）の回路接続を示すもので，ノノ
トよびノ２は通常電流，容量の出カハッファに訃ける電
流引込側のバッファトランジスタ，１３訃よひノ４は上
記通常電流容量よりは大電流容量の出力バッファにおけ
る電流引込側のバッファトランジスタであり，１５〜１
８はこれらのトランジスタ１１〜Ｊ４を駆動するインパ
ータ、１９〜２０は上記トランジスタ１１〜１４の一端
に接続された出力端子（パッド）．２３は低電位側電源
ｖ８Ｂ用の電源端子，３２は上記トランジスタ１１〜１
４と電源端子２３との間のパンファ用電源配線，３３〜
３６はその抵抗分である。[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. Figure 3 shows the circuit connections of a part of the output buffer section (for example, the current sinking side) of a MOS type LSI, and No. 2 and No. 2 are the buffer transistors on the current sinking side, which normally serve as current and capacitance output buffers. 13 is a buffer transistor on the current sink side of the output buffer with a larger current capacity than the normal current capacity, and 15 to 1
8 is an inperter that drives these transistors 11 to J4, and 19 to 20 are output terminals (pads) connected to one ends of the transistors 11 to 14. 23 is a power supply terminal for the low potential side power supply v8B, 32 is the above-mentioned transistor 11-1
4 and the power supply terminal 23, 33~
36 is the resistance.

なお．３７は内部ブロックであって，電源配線−５− ３８を介して上記電源端子２３に接続されており，３９
は上記電源配線３８の抵抗分である。In addition. 37 is an internal block, which is connected to the power supply terminal 23 via power supply wiring -5-38, and 39
is the resistance of the power supply wiring 38.

上記第３図の回路にかいて、大電流のべソファトランジ
スタ１３．１４は通常電流のパツファトランジスタ１１
．１２よりも電源端子２３の近くに配置されている。す
なわち、たとえば第４図に示すように．ＬＳＩチップ４
０上で電源端子２３の周辺（たとえば両側）に大電流の
バツファトランジスタＪ３，Ｊ４が配置され，これより
離れて通常ｔ　流ノバッフ７｝ランジスタノ１，１２が
配置されている。In the circuit shown in FIG.
．． 12 is located closer to the power supply terminal 23. That is, for example, as shown in FIG. LSI chip 4
0, large current buffer transistors J3 and J4 are arranged around (for example, on both sides) of the power supply terminal 23, and normal current buffer transistors 1 and 12 are arranged apart from these.

したがって，上述したＬＳＩによれば、電源配線３２の
うち電源端子２３と大電流のバツファトランジスタ１３
．１４との間の部分の距離が従来よりも短かくなり、こ
れによって電源配線３２の電圧降下が小さくな．！７，
その電圧変動が小さくなる分だけバッファトランジスタ
１３．１４のデメンションを小プ〈することができる。Therefore, according to the above-mentioned LSI, the power supply terminal 23 and the large current buffer transistor 13 of the power supply wiring 32
．． 14 is shorter than before, which reduces the voltage drop in the power supply wiring 32. ! 7,
The dimensions of the buffer transistors 13 and 14 can be reduced by the amount that the voltage fluctuation is reduced.

１た、前述したように大亀流のバッファトランジスタ１
３，Ｊ４が電源端子２３の近くに配置されているので，
一６一これらの間の電源配線の抵抗分による電圧降下が従来よ
りも小さくなり，換言すればこの電源配線の幅を従来よ
りも細くすることができる。すなわち、たとえば発光ダ
イオード笠の駆動のためにバッファトランジスタＪ３，
ｌ４？特に大電流化するに際しても、そのデメンジョン
の増大お−よび上記バッファトランジスタ１３．１４と
■ｓ８用電源端子２３とσ）間の電源配線の幅の増大、
つ１りＬＳ！チップサイズの増大を極力少なくすること
が可能である。1. As mentioned above, Oki style buffer transistor 1
3. Since J4 is located near the power supply terminal 23,
161 The voltage drop due to the resistance of the power supply wiring between these is smaller than before, and in other words, the width of this power supply wiring can be made narrower than before. That is, for example, for driving the light emitting diode shade, the buffer transistors J3,
l4? In particular, when increasing the current, the dimension increases and the width of the power supply wiring between the buffer transistors 13 and 14 and the power supply terminal 23 for s8 and σ) increases.
One LS! It is possible to minimize the increase in chip size.

なお、上記実施例は，　ＬＳＩの出力バッファ部の電流
引込側を示したが．出力パソファ部の電流供給側のトラ
ンジスタと高電位＄１！＋電源ＶＤＤ用電源端子との関
係についても上記と同様に適用でき．′１た入力バッフ
ァ部にも上記に準じて回路接続トよびバッファ回路配置
を行なうことが可能である。Note that the above embodiment shows the current drawing side of the output buffer section of the LSI. Transistor on the current supply side of the output path sofa section and high potential $1! The above can also be applied to the relationship with the + power supply VDD power supply terminal. It is also possible to connect circuits and arrange buffer circuits in the input buffer section '1 in the same manner as described above.

［発明の効果］上述したように、本発明の半導体集積回路装置によれば
、入力バッファと電源端子との配置を合理的に行なうこ
とによって，入力バッファの大電流化に伴なうチップサ
イズの増大を極力少な〈することができる。[Effects of the Invention] As described above, according to the semiconductor integrated circuit device of the present invention, by rationally arranging the input buffer and the power supply terminal, the chip size can be reduced due to the increase in the current of the input buffer. The increase can be kept to a minimum.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の半導体集積回路装置に釦ける出力バッフ
ァ部の一部を示す回路図、第２図は第１図のバッファと
電源端子とのチッゾ上の配置関係を説明するための図，
第３図は本発明に係る半導体集積回路装置の一実施例を
説明するための出カバッファ部の一部を示す回路図、第
４図は第３図のバッファと電源端子とのチップ上の配置
関係を説明するための図である。１１．１２・・・通常電流のバッファトランジスタ，１
３．１４・・・大電流のバッファトランジスタ、１９〜
２０・・・出力端子、２３・・・電流端子，３２・・・
電源配縁。FIG. 1 is a circuit diagram showing a part of an output buffer section that is buttoned in a conventional semiconductor integrated circuit device, and FIG. 2 is a diagram for explaining the arrangement relationship on the chip between the buffer and power supply terminal of FIG. 1.
FIG. 3 is a circuit diagram showing a part of the output buffer section for explaining one embodiment of the semiconductor integrated circuit device according to the present invention, and FIG. 4 is a layout of the buffer shown in FIG. 3 and the power supply terminal on the chip. FIG. 3 is a diagram for explaining the relationship. 11.12...Normal current buffer transistor, 1
3.14...Large current buffer transistor, 19~
20... Output terminal, 23... Current terminal, 32...
Power supply wiring.

Claims

【特許請求の範囲】[Claims]

バッファ回路とその他の内部ロジックとに別別の電源配
線により電源を供給し、上記バッファ回路として電流容
量が異なる２種類以上のバッファ回路を有する半導体集
積回路装置において、大電流の入力バッファ回路のバッ
ファトランジスタを小電流の入力バッファ回路のバッフ
ァトランジスタよりも電源端子に近く配置し、この電源
端子から上記各バッファ回路へ電源配線を施してなるこ
とを特徴とする半導体集積回路装置。In a semiconductor integrated circuit device in which power is supplied to the buffer circuit and other internal logic through separate power supply wiring, and the buffer circuit has two or more types of buffer circuits with different current capacities, the buffer of the large current input buffer circuit A semiconductor integrated circuit device characterized in that a transistor is arranged closer to a power supply terminal than a buffer transistor of a small current input buffer circuit, and power supply wiring is provided from this power supply terminal to each of the above-mentioned buffer circuits.