JPH0316164A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0316164A JPH0316164A JP1290499A JP29049989A JPH0316164A JP H0316164 A JPH0316164 A JP H0316164A JP 1290499 A JP1290499 A JP 1290499A JP 29049989 A JP29049989 A JP 29049989A JP H0316164 A JPH0316164 A JP H0316164A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- potential
- conductor
- low
- low resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 63
- 239000004020 conductor Substances 0.000 claims abstract description 88
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 58
- 238000009792 diffusion process Methods 0.000 claims abstract description 19
- 150000002500 ions Chemical class 0.000 claims abstract description 12
- 238000005468 ion implantation Methods 0.000 claims abstract description 9
- 239000000463 material Substances 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 20
- 230000005672 electromagnetic field Effects 0.000 abstract description 6
- 239000012535 impurity Substances 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 4
- 230000002093 peripheral effect Effects 0.000 abstract description 2
- 229910052782 aluminium Inorganic materials 0.000 description 37
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 37
- 238000010586 diagram Methods 0.000 description 25
- 239000010410 layer Substances 0.000 description 25
- 230000000694 effects Effects 0.000 description 23
- 230000005684 electric field Effects 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 230000000087 stabilizing effect Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 101100521334 Mus musculus Prom1 gene Proteins 0.000 description 1
- BTYUGHWCEFRRRF-UHFFFAOYSA-N [As].[K] Chemical class [As].[K] BTYUGHWCEFRRRF-UHFFFAOYSA-N 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000009191 jumping Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Measuring Instrument Details And Bridges, And Automatic Balancing Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に於ける高精度な低抗素子の構造に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a highly accurate low resistance element in a semiconductor device.
従来、多結晶シリコンで低抗素子、特に高低抗素子を半
導体基板上に形成した構造図を第３図に示す。半導体基
板３の上に酸化膜である絶縁膜９をはさみ多結晶シリコ
ン２が形成され、コンタクト５、７を介してアルミニウ
ム電極線４、６と接続されている。そして多結晶シリコ
ン２の上部には絶縁膜１０があり、その上部はアルミニ
ウム配線による信号線又は何も信号線がなく酸化保護膜
があるのみであった。FIG. 3 shows a structural diagram of a conventional structure in which a low resistance element, particularly a high resistance element, is formed on a semiconductor substrate using polycrystalline silicon. Polycrystalline silicon 2 is formed on a semiconductor substrate 3 with an insulating film 9, which is an oxide film, interposed therebetween, and is connected to aluminum electrode lines 4 and 6 via contacts 5 and 7. There was an insulating film 10 on top of the polycrystalline silicon 2, and on the top there was a signal line made of aluminum wiring or no signal line at all, only an oxidized protective film.
さらに、従来低濃度の拡散層又はイオン打ち込みによる
拡散層で形成される低抗素子を半導体基板上に形成した
構造図を第４図に示す。半導体基板１３の表面部に形成
された拡散抵抗１２はコンタクト１５、１７を介してア
ルミニウム電極線１４、１６と接続されている。そして
拡散抵抗の上部には酸化膜である絶縁膜があり、その上
部は多結晶シリコンやアルミニウムによる他の信号配線
が、又は何も信号配線がなく酸化保護膜があるのみであ
った。Further, FIG. 4 shows a structural diagram in which a low resistance element, which is conventionally formed by a low concentration diffusion layer or a diffusion layer formed by ion implantation, is formed on a semiconductor substrate. Diffused resistor 12 formed on the surface of semiconductor substrate 13 is connected to aluminum electrode lines 14 and 16 via contacts 15 and 17. There is an insulating film which is an oxide film on top of the diffused resistor, and on top of that there is another signal wiring made of polycrystalline silicon or aluminum, or there is no signal wiring at all, only an oxide protective film.
しかし、第４図に示す従来の構造では、低抗素子の拡散
面と酸化膜の界面に蓄積した電荷や低抗素子上を通過す
る信号配線からの電界のために低抗素子表面に空乏層を
生ずる。この空乏層は低抗素子の抵抗値を上昇させる方
向に働く。この空乏層の厚みが低抗素子の拡散の深さに
対して無視できない水準になると、低抗素子の値を大き
く変動させることになる。イオン打ち込みで形成される
１μ以下の拡散深さでシート抵抗６〜９ ＫΩ／口以上
の低抗素子では、この現象が顕著で、抵抗値が数％から
数１０％変動することがあった。However, in the conventional structure shown in Figure 4, there is a depletion layer on the surface of the low resistance element due to charges accumulated at the interface between the diffusion surface of the low resistance element and the oxide film and an electric field from the signal wiring passing over the low resistance element. will occur. This depletion layer works to increase the resistance value of the low resistance element. When the thickness of this depletion layer reaches a level that cannot be ignored with respect to the diffusion depth of the low resistance element, the value of the low resistance element will vary greatly. This phenomenon is noticeable in low-resistance elements formed by ion implantation with a diffusion depth of 1 μm or less and a sheet resistance of 6 to 9 KΩ/hole or more, and the resistance value sometimes fluctuates from several percent to several tens of percent.
また同様に、第３図に示すような構造に高抵抗多結晶シ
リコンを使用した場合、酸化膜で保護されているだけの
ため、不純物イオンが多結晶シリコン上に進入した場合
、その電界により、多結晶シリコンの抵抗値が大きく変
動することがあった。Similarly, when high-resistance polycrystalline silicon is used in the structure shown in Figure 3, it is only protected by an oxide film, so when impurity ions enter the polycrystalline silicon, the electric field causes The resistance value of polycrystalline silicon sometimes fluctuated greatly.
又半導体素子は特性上、光に対してエネルギー準位が変
化する為、半導体装置に可視光、赤外線、紫外線等が照
射されると、抵抗値が変化してしまうという問題点も有
していた。Additionally, due to the characteristics of semiconductor devices, the energy level changes in response to light, so when a semiconductor device is irradiated with visible light, infrared rays, ultraviolet rays, etc., the resistance value changes. .
本発明の半導体装置の構或は、低濃度拡散あるいは、イ
オン打込みで形成される拡散抵抗もしくは多結晶シリコ
ンで形成される低抗素子の少なくとも一個を低抵抗導体
で覆い、この低抵抗導体は電源に対して、一定電位に保
たれていることを特徴とする。In the structure of the semiconductor device of the present invention, at least one of the diffused resistors formed by low concentration diffusion or ion implantation or the low resistance elements formed of polycrystalline silicon is covered with a low resistance conductor, and the low resistance conductor is connected to the power source. It is characterized by being kept at a constant potential.
本発明の上記構成によれば、低濃度拡散あるいはイオン
打込みでｔＭ或される抵抗、又は高抵抗多結晶シリコン
の少なくとも上方を一定電位に接続された低抗素子より
低抵抗の導体で低抗素子の平面面積の半分以上を覆うこ
とにより、抵抗値の変動の原因となる、不純物イオンや
近接信号線からのｔｔｓｔａ界を遮断するので、低濃度
拡散の抵抗、多結晶シリコンが抵抗値を安定に保つこと
ができるのである。According to the above configuration of the present invention, a low resistance element is formed using a conductor having a lower resistance than a low resistance element which is connected to a constant potential at least above the resistance which is reduced by tM by low concentration diffusion or ion implantation, or the high resistance polycrystalline silicon. By covering more than half of the plane area of the resistor, it blocks the ttsta field from impurity ions and nearby signal lines that cause resistance fluctuations, so the low-concentration diffused resistor and polycrystalline silicon stabilize the resistance value. It is possible to maintain it.
又、光が照射されることによる抵抗値の変動も防止する
ことができる。Further, fluctuations in resistance value due to irradiation with light can also be prevented.
本発明の実施例を図面に基づいて説明する。第１図は本
発明の基本構成となる多桔晶シリコンによる低抗素子の
構造図である。２は多結晶シリコンを用いた低抗素子で
、その両端はコンタクト５、７を経由して電極４、６へ
引き出されている。電極４、６の材料はアルミニウムで
ある。そして多桔晶シリコン２の上部に酸化膜をはさみ
、低抵抗導体１を形成し、一定電位（低電源電位ｖｓｓ
ｓ、又は高電源電位ＶＤＤ、その中間電位でもよい）を
与えておく。尚、本発明に於ける酸化膜とは絶縁膜を意
図する。Embodiments of the present invention will be described based on the drawings. FIG. 1 is a structural diagram of a low resistance element made of polycrystalline silicon, which is the basic structure of the present invention. 2 is a low resistance element using polycrystalline silicon, and both ends thereof are led out to electrodes 4 and 6 via contacts 5 and 7. The material of the electrodes 4 and 6 is aluminum. Then, an oxide film is sandwiched on top of the polycrystalline silicon 2 to form a low resistance conductor 1, and a constant potential (low power supply potential vss
s, or a high power supply potential VDD, or an intermediate potential thereof). Note that the oxide film in the present invention is intended to be an insulating film.
この様な構造の低抗素子は次の様な利点がある。A low resistance element with such a structure has the following advantages.
まず低抵抗導体１の上部に配置される信号線、及び外界
からのノイズが低抗素子へ飛び込むのを防止することが
できる。つまり低抗素子の周囲に存在する浮遊容量、／
Ｖ遊インダクタンス等から伝わる電気・磁気ノイズは、
低抵抗導体の静電しやへい効果により取り除かれる。よ
って低抗素子は、半導体装置の動作中でもノイズにより
電流一電圧特性（即ち抵抗値）が変化することなく、安
定した精度の高い素子として使われる。First, it is possible to prevent noise from the signal line disposed above the low resistance conductor 1 and the outside world from jumping into the low resistance element. In other words, the stray capacitance that exists around the low resistance element, /
Electrical/magnetic noise transmitted from V free inductance etc.
removed by the electrostatic shielding effect of low-resistance conductors. Therefore, the low resistance element can be used as a stable and highly accurate element without changing its current-voltage characteristics (ie, resistance value) due to noise even during operation of the semiconductor device.
次に、製造工程中及び完或後に低抗素子へ外部から入り
込む＋イオン、一イオンの進入を防止することができる
。つまり低抵抗導体の電位より＋側に帯電しているイオ
ンは反発させ低抗素子から遠ざけ、一側に帯電している
イオンは低抵抗導体へ引きよせる。すると、半導体装置
の電源をいれている間は、低抗素子近傍のイオン分布は
一定となり、外部イオンによる電界影響を防ぐことがで
きる。Next, it is possible to prevent positive ions and negative ions from entering the low resistance element from the outside during and after the manufacturing process. In other words, ions that are charged to the positive side of the potential of the low-resistance conductor are repelled and away from the low-resistance element, while ions that are charged to one side are attracted to the low-resistance conductor. Then, while the semiconductor device is powered on, the ion distribution in the vicinity of the low resistance element becomes constant, and it is possible to prevent the influence of the electric field due to external ions.
よって経年変化により抵抗値が変動することを防止する
ことが可能となる。Therefore, it is possible to prevent the resistance value from changing due to aging.
さらに低抵抗導体は、外部から低抗素子へ照射される光
を遮断することが可能である。高抵抗多粘晶シリコン抵
抗は半導体である為、可視光、赤外線、紫外線等の光エ
ネルギーにより、電子エネルギーが遷移し、結果的に低
抗素子としての特性が変化してしまう。そこで低抵抗導
体という物理的保護材で覆うことにより上記の様な問題
点はなくなり安定した低抗素子となる。Furthermore, the low-resistance conductor can block light irradiated from the outside to the low-resistance element. Since a high-resistance multiviscosity silicon resistor is a semiconductor, its electronic energy changes due to light energy such as visible light, infrared rays, and ultraviolet rays, resulting in changes in its characteristics as a low-resistance element. Therefore, by covering it with a physical protective material such as a low resistance conductor, the above-mentioned problems can be eliminated and a stable low resistance element can be obtained.
以上、外界からの影響で低抗素子特性が変動することを
防止する利点をあげてきたが、反対に低抗素子自体から
発生するノイズ、電界・磁界を周囲へおよぼさないとい
う利点もある。とくに高速で動作する回路の場合、低抗
素子を流れる電荷も急激に変動する為、熱雑音を大きく
なり、この低抗素子から放出される不要幅射は無視でき
なくなり、この様は場合、有効である。Above, we have mentioned the advantage of preventing the characteristics of the low resistance element from changing due to the influence of the outside world, but on the other hand, there is also the advantage of preventing the noise, electric field, and magnetic field generated from the low resistance element itself from being spread to the surrounding area. . Particularly in the case of circuits that operate at high speeds, the charge flowing through the low-resistance element also fluctuates rapidly, increasing thermal noise and making it impossible to ignore unnecessary radiation emitted from the low-resistance element. It is.
抵抗の材料としては、Ｐ型多結晶シリコン、Ｎ型多結晶
シリコンの他にイオン打ち込みしないか、イオン打ち込
み量を少なくした高抵抗の多結晶シリコン（ハイレジと
呼ぶ）、又はシリコンに限らず他の半導体、及び半導体
一金属化合物においても、本発明は同じ効果を持つ。In addition to P-type polycrystalline silicon and N-type polycrystalline silicon, resistor materials include high-resistance polycrystalline silicon with no ion implantation or with a reduced amount of ion implantation (called high resistance), or other materials other than silicon. The present invention has the same effect on semiconductors and semiconductor-metallic compounds.
低抵抗導体の材質としては、アルミニウム●タングステ
ン・モリブデンはどの金属が一般的であるが、多結晶シ
リコンでも効果はある。さらにカリウムひ素系の化合物
・超電導材料でも可能である。Common metals for low resistance conductors include aluminum, tungsten, and molybdenum, but polycrystalline silicon is also effective. Furthermore, potassium arsenic compounds and superconducting materials are also possible.
本発明は構造が簡単である為、応用範囲が極めて広い。Since the present invention has a simple structure, it has an extremely wide range of applications.
その中から低抗素子の構造に関する応用例に焦点を絞り
、実施例をあげてゆく。Among them, we will focus on application examples related to the structure of low resistance elements and give examples.
第５図は半導体基板表面に形成された選択的酸化膜（以
下ＬＯＣＯＳと呼ぶ）上に本発明の多結晶シリコン抵抗
を形成した図である。基板５５上にＬＯＣＯＳ５３を形
成し、その上に酸化１１９！５２を介して多結晶シリコ
ン抵抗５０を形成する。さらに酸化１１１５６をはさみ
アルミニウムの導体５１で抵抗５０を覆い、アルミニウ
ム導体５１には電源ＶＳＳ５４を接続しておく。ＬＯＣ
ＯＳの上部に低抗素子を形成することの利点は、ＬＯＣ
ＯＳ膜が厚い為、多結晶シリコンの真下に寄生トランジ
スタができにくい、基板との距離が遠くなる為、低抗素
子と基板の間の浮遊容量が少なくなる。抵抗直下のビン
ホールによりリークが防止しやすい等があげられる。第
５図は低抵抗導体で覆うことにより、低抗素子としての
安定性、高猜度性、信頼性がさらに高まる。FIG. 5 is a diagram showing a polycrystalline silicon resistor of the present invention formed on a selective oxide film (hereinafter referred to as LOCOS) formed on the surface of a semiconductor substrate. A LOCOS 53 is formed on a substrate 55, and a polycrystalline silicon resistor 50 is formed thereon through oxidation 119!52. Further, the resistor 50 is covered with an aluminum conductor 51 sandwiching oxide 11156, and a power supply VSS 54 is connected to the aluminum conductor 51. LOC
The advantage of forming a low resistance element on top of the OS is that the LOC
Because the OS film is thick, it is difficult to form a parasitic transistor directly under the polycrystalline silicon, and because the distance from the substrate is long, the stray capacitance between the low resistance element and the substrate is reduced. The bottle hole directly under the resistor makes it easy to prevent leaks. FIG. 5 shows that by covering with a low-resistance conductor, stability, high precision, and reliability as a low-resistance element are further improved.
第６図はＬＯＣＯＳの直下に高濃度拡散領域を設けた応
用例の図である。トランジスタの耐圧を上げる為にＬＯ
ＣＯＳの下に高濃度拡散領域（ストッパー）を設ける。FIG. 6 is a diagram of an application example in which a high concentration diffusion region is provided directly under the LOCOS. LO to increase the withstand voltage of the transistor
A high concentration diffusion region (stopper) is provided below the COS.
第６図はＰチャンネル領域などで、濃いＮ″″ストッパ
ー６５を設け、基板６６よりＶＤＤ電位を与える。ＬＯ
ＣＯＳ６４の上に多結晶シリコン抵抗６０を形成し、そ
の上部をアルミニウム導体６１で覆い、その電位をＶＤ
Ｄ６７とする。この構成にすると抵抗６０はＶＤＤに保
たれるアルミニウム導体６１とＮ“ストッパー６５によ
って上下からシールドされる。よって低抗素子としての
特性も安定しかつトランジスタの耐圧も上がるという二
重の効果がある。Ｎチャンネル領域では、ＬＯＣＯＳ下
のＰ−ウェルにＰ１ストッパーを設け、このＰ＋ストッ
パー及びアルミニウム導体にｖＳＳを与えれば全く同じ
効果がｍられる。In FIG. 6, a thick N″″ stopper 65 is provided in the P channel region, and a VDD potential is applied from the substrate 66. L.O.
A polycrystalline silicon resistor 60 is formed on the COS 64, its upper part is covered with an aluminum conductor 61, and its potential is set to VD.
Let it be D67. With this configuration, the resistor 60 is shielded from above and below by the aluminum conductor 61 maintained at VDD and the N'' stopper 65.Therefore, it has the double effect of stabilizing its characteristics as a low resistance element and increasing the withstand voltage of the transistor. In the N-channel region, exactly the same effect can be achieved by providing a P1 stopper in the P-well below the LOCOS and applying vSS to this P+ stopper and the aluminum conductor.
第７図（ａ）は、抵抗と同じ材料て抵抗周辺をシールド
した実施同の平面図で、第７図（ｂ）はＡ−Ｂ線の断面
図である。本発明のシールド効果をより高めるには、低
抗素子と同じ高さ（層）にもシールド材を形成すること
が望ましい。そこで、多結晶シリコン低抗素子７０の周
囲に多結晶シリコン７７を配置し、それらを全て覆うＶ
ＳＳに接続されたアルミニウム導体７５を形成し、アル
ミニウム導体７５と多結晶シリコン７７はできる限りコ
ンタクト７６、７８を設ける。こうすることにより多結
晶シリコン７０の抵抗値は下がり、低抵抗導体に対して
シールド効果を発揮する。図中７３、７４は、コンタク
ト７１、７２を介して多桔晶シリコン７０に接続される
アルミニウム導体７５を同層のアルミニウム電極線であ
る。FIG. 7(a) is a plan view of the same structure in which the periphery of the resistor is shielded using the same material as the resistor, and FIG. 7(b) is a sectional view taken along line AB. In order to further enhance the shielding effect of the present invention, it is desirable to form the shield material at the same height (layer) as the low resistance element. Therefore, polycrystalline silicon 77 is placed around the polycrystalline silicon low resistance element 70, and V
An aluminum conductor 75 connected to SS is formed, and contacts 76 and 78 are provided between the aluminum conductor 75 and the polycrystalline silicon 77 as much as possible. By doing so, the resistance value of the polycrystalline silicon 70 is lowered, and a shielding effect is exhibited for the low resistance conductor. In the figure, reference numerals 73 and 74 indicate aluminum electrode lines in the same layer as the aluminum conductor 75 connected to the polycrystalline silicon 70 via contacts 71 and 72.
第８図は低抗素子の下層にシールド層を形成した構造図
である。半導体基板８３の上に酸化膜８６をはさみ、導
体８２を形成し、電位をＶＳＳ８５とする。この導体８
２は通常第１多結晶シリコンが用いられる。そして酸化
膜をはさみ、第２多結晶シリコンによる低抗素子８０が
形成され、さらに酸化膜をはさみ、ＶＳＳ８４へ電位を
とられたアルミニウム導体８１が低抗素子８０の上部を
覆う。この構造にすれば、低抗素子８０をその上下層か
らシールドする為、安定した低抗素子が得られるという
効果は高い。ここで第１多結晶シリコンはアルミニウム
より高抵抗であるため第１多結晶シリコンとｖＳＳ電源
を接続する為のコンタクトを多くとる程、前記効果が大
きくなることはいうまでもない。特に導体が多結晶シリ
コンの場合、低抗素子を挾んで対向する多結晶シリコン
の両端部の２個所に少なくとも電源コンタクトを配置す
る等して、多結晶シリコン導体の各部分の電位をできる
だけ均一にするようにすれば、低抗素子に対する効果は
より一層向上する。FIG. 8 is a structural diagram in which a shield layer is formed below a low resistance element. An oxide film 86 is sandwiched over a semiconductor substrate 83, a conductor 82 is formed, and the potential is set to VSS85. This conductor 8
2 is usually made of first polycrystalline silicon. A low-resistance element 80 made of second polycrystalline silicon is formed with the oxide film sandwiched therebetween, and an aluminum conductor 81 , which is connected to the potential VSS 84 , covers the upper part of the low-resistance element 80 , sandwiching the oxide film therebetween. With this structure, since the low resistance element 80 is shielded from its upper and lower layers, a stable low resistance element can be obtained, which is highly effective. Here, since the first polycrystalline silicon has a higher resistance than aluminum, it goes without saying that the more contacts for connecting the first polycrystalline silicon and the vSS power supply, the greater the above effect becomes. In particular, if the conductor is polycrystalline silicon, the potential of each part of the polycrystalline silicon conductor should be made as uniform as possible by placing at least two power contacts at both ends of the polycrystalline silicon, which face each other with a low resistance element in between. If this is done, the effect on the low resistance element will be further improved.
第９図（ａ）は第１図の構造に於いて、低抵抗導体の電
位をＶＤＤ９０にとった低抗素子の構造図である。シー
ルド効果という点からするとＶＳＳでもＶＤＤでも変わ
りない。FIG. 9(a) is a structural diagram of a low resistance element having the structure shown in FIG. 1, but with the potential of the low resistance conductor set to VDD90. From the point of view of shielding effectiveness, there is no difference between VSS and VDD.
第９図（ｂ）は同じく低抵抗導体への印加電位をトラン
ジスタの出力電圧から取り出してＶＤＤ，ＶＳＳの中間
電位とする場合の一側図である。ＭＯＳトランジスタ９
１、９２、９３、９４のトランジスタ駆動能力を各々β
，，、β，２、β、，、βＮ２、トランジスタしきい値
を各々ｖＴＰ１、ＶＴＰ２、ＶＴＮＩ 、ＶＴＮ２とす
ると信号９６の電位はｖｏｏ−ｖ２”ＶＴＰ２ −ｖ
ＴＰ，となる。よって出力電圧は、ＶＤＤを基中とする
と、
Ｖｏｌｔ↑ 一ｖ２
シールド効果を上げるためには、中間電位の出力インピ
ーダンスを低くする必要があるので、第９図（ｂ）では
、ｖ２電位のボルテージフロアとして差動対を利用し、
出力９７を得ている。Similarly, FIG. 9(b) is a side view when the potential applied to the low resistance conductor is extracted from the output voltage of the transistor and set to an intermediate potential between VDD and VSS. MOS transistor 9
1, 92, 93, and 94 are β
,,,β,2,β,,,βN2,If the transistor threshold values are vTP1, VTP2, VTNI, and VTN2, respectively, the potential of the signal 96 is voo-v2''VTP2-v
TP, becomes. Therefore, when the output voltage is based on VDD, Volt↑ - v2 In order to increase the shielding effect, it is necessary to lower the output impedance at the intermediate potential, so in Fig. 9(b), the voltage floor of the v2 potential is Using a differential pair as
An output of 97 is obtained.
さらにシールドされる低抗素子の温度特性に合わせて、
シールド導体の電位を変化させてやれば、シールド低抗
素子を変動させる原因の一つである空乏層の効果を補償
することができる。例えば第９図（ｂ）において、トラ
ンジスタ９４のゲート入力を直接ボルテージフォロアの
十端子に人力すれば、Ｐ型のシールドされる低抗素子の
空乏層効果を補償することができる。Furthermore, according to the temperature characteristics of the low resistance element to be shielded,
By changing the potential of the shield conductor, it is possible to compensate for the effect of the depletion layer, which is one of the causes of fluctuations in the shield low resistance element. For example, in FIG. 9(b), if the gate input of the transistor 94 is directly connected to the voltage follower terminal, the depletion layer effect of the P-type shielded low resistance element can be compensated for.
第１０図は中間タップ付低抗素子の応用回路図である。FIG. 10 is an application circuit diagram of a low resistance element with an intermediate tap.
抵抗を２分割して、その中間点からの出力オペアンプ１
０７を通して取り出す回路で、正確に２分割された低抗
素子へ本発明を適用している。Divide the resistor into two and output operational amplifier 1 from the midpoint.
The present invention is applied to a low-resistance element that is accurately divided into two in the circuit taken out through 07.
ＶＤＤ１００とＶＳＳ１０５にコンタクト１０２、１０
４を介して接続された多結晶シリコン抵抗１０１には、
その構造上の中間点にコンタクト１０３が設けられ、コ
ンタクトから取り出す信号１０６の電位はＶＤＤ／２に
なるようにしてある。Contacts 102 and 10 to VDD100 and VSS105
The polycrystalline silicon resistor 101 connected through 4 has a
A contact 103 is provided at a midpoint in the structure, and the potential of a signal 106 taken out from the contact is set to VDD/2.
この多結晶シリコン抵抗１０１の上部をｖＳＳへ接続さ
れたアルミニウム導体１０９で覆うことにより、抵抗値
が周囲のノイズや電磁界からシールドされ、部分的に抵
抗値が変動してしまうのを防ｄ二する。よって出力Ｖｏ
ｌ０ｇには正確にＶＤＤ／２が出力される。By covering the upper part of this polycrystalline silicon resistor 101 with an aluminum conductor 109 connected to vSS, the resistance value is shielded from surrounding noise and electromagnetic fields, and partial fluctuations in the resistance value are prevented. do. Therefore, the output Vo
Accurately VDD/2 is output to l0g.
第１１図は第１０図と目的は同じで、２本の低抗素子を
用いる場合の応用回路図である。ＶＤＤ１１０とｖＳＳ
１１１の間に直列接続された２本の多結晶シリコン抵抗
１１４と１１５があり、その２本をつなぐ信号１１６は
オペアンプ１１７へ人力され、信号１１６の電位がその
まま出力電圧Ｖｏｌｌ８となって出力される。FIG. 11 has the same purpose as FIG. 10, and is an applied circuit diagram when two low resistance elements are used. VDD110 and vSS
There are two polycrystalline silicon resistors 114 and 115 connected in series between 111, and a signal 116 connecting the two is input to an operational amplifier 117, and the potential of signal 116 is output as is as output voltage Vol8. .
２
とする為には、抵抗１１５と１１６の構造を全く同じに
しておき、かつ周囲からのノイズ、電磁界による影響を
防ぐ為、抵抗１１５と１１６の上層アルミニウム導体１
１３と１１２で覆い、同一の電位１１１を与えておく。2, the resistors 115 and 116 have exactly the same structure, and in order to prevent the influence of noise and electromagnetic fields from the surroundings, the upper layer aluminum conductor 1 of the resistors 115 and 116 is
13 and 112, and apply the same potential 111.
こうすることによりＶ。には安定した電圧が出力される
。By doing this, V. A stable voltage is output.
この構成による抵抗分割は極めて応用範囲が広く、３本
、４本を直列接続しておけば、ＶＤＤ／３、ＶＤＤ／４
も簡単に得られる。Resistor division with this configuration has an extremely wide range of applications, and if three or four resistors are connected in series, VDD/3, VDD/4
can also be obtained easily.
又、スタンダードセル方式による半導体集積装置内のレ
イアウト侍、予め低抗素子とそれを覆うアルミニウム等
の導体を１つのセルとして登録しておけば、簡単に自動
配置、配線処理が可能である。Furthermore, if a low resistance element and a conductor such as aluminum covering it are registered in advance as one cell in the layout of a semiconductor integrated device using the standard cell method, automatic placement and wiring processing can be easily performed.
以上、多結晶ポリシリコン抵抗を用いた本発明の構造で
は、アルミニウム配線１番の場合を例にあげて来たが、
もちろん２層、３層配線の半導体装置でも応用できる。Above, in the structure of the present invention using a polycrystalline polysilicon resistor, the case of aluminum wiring No. 1 has been given as an example.
Of course, it can also be applied to semiconductor devices with two-layer or three-layer wiring.
第１２図はアルミ２層以上の構造図である。基板１２１
の上に酸化膜１２２をはさみ多結晶シリコン抵抗１２０
があり、電極１２４、１２５を通して低抗素子として動
作する。電極１２４、１２５は第１アルミニウム配線層
である。さらに酸化ＩｌｌＩ１２３、１２６をはさんで
、第２アルミニウム配線層１２７があり、多結晶シリコ
ン抵抗１２０の上部を覆っており、かつＶＳＳ電位を与
えられている。この場合、低抗素子１２０とシールド材
１２７の距離が、アルミニウム１層配線の時より離れる
為、多少シールドの効果は減るが、低抗素子のコンタク
トをさけてシールド材のパターン設計をしなくて済むの
で、その分、設計は容易となる。FIG. 12 is a structural diagram of two or more layers of aluminum. Substrate 121
A polycrystalline silicon resistor 120 with an oxide film 122 sandwiched thereon.
It operates as a low resistance element through electrodes 124 and 125. Electrodes 124 and 125 are first aluminum wiring layers. Further, there is a second aluminum interconnection layer 127 sandwiching the oxidized IllI 123 and 126, covering the upper part of the polycrystalline silicon resistor 120, and applying the VSS potential. In this case, the distance between the low resistance element 120 and the shielding material 127 is greater than that in the case of single-layer aluminum wiring, so the shielding effect is somewhat reduced, but the pattern of the shielding material must be designed to avoid contact with the low resistance element. Therefore, the design becomes easier.
これまでの実施例は多結晶シリコンを抵抗素材として使
う場合であったが、半導体基板に埋め込まれた拡散抵抗
の場合でも、本発明のシールド効果により抵抗の安定化
という技術は応用できる。Although the embodiments described so far have used polycrystalline silicon as the resistance material, the technique of stabilizing the resistance by the shielding effect of the present invention can also be applied to the case of a diffused resistance embedded in a semiconductor substrate.
第２図は本発明を拡散抵抗へ応用した時の基本構造図で
ある。拡散抵抗１２の両端にコンタクト１５、１７を設
け、アルミニウム配線１４、１６を電極とする。そして
拡散抵抗の上部を酸化膜をはさんでアルミニウム導体１
１で覆い、ｖｓｓｑ醒１８を与えておく。この構造によ
りアルミニウム導体１１はシールド材となり、外界から
の電磁波ノイズや光、イオン、よごれを電気的かつ物理
的に遮蔽するので、拡散抵抗の安定化、高精度化の効果
がある。FIG. 2 is a basic structural diagram when the present invention is applied to a diffused resistor. Contacts 15 and 17 are provided at both ends of the diffused resistor 12, and aluminum interconnections 14 and 16 are used as electrodes. Then, connect the aluminum conductor 1 to the top of the diffused resistor with an oxide film in between.
Cover with 1 and give vssq 18. With this structure, the aluminum conductor 11 serves as a shielding material and electrically and physically shields electromagnetic noise, light, ions, and dirt from the outside world, thereby stabilizing the diffusion resistance and improving precision.
拡散抵抗の材質としてはＮ−ＪＪ板中に形成するＰ−ウ
エル抵抗、Ｐ−基板中に形成するウエル抵抗などの低濃
度拡散抵抗や、イオン打ち込みで形成するＰ＋抵抗、Ｎ
４抵抗などの高濃度拡散抵抗などに本発明は適用できる
。The materials for the diffused resistors include low-concentration diffused resistors such as P-well resistors formed in N-JJ boards, well resistors formed in P- substrates, P+ resistors formed by ion implantation, and N
The present invention can be applied to high concentration diffused resistors such as 4 resistors.
又低抵抗導体の材質としては、アルミニウムや多結晶シ
リコンの他、金属一半導体化合物、超電導物質などが適
用できる。Further, as the material of the low resistance conductor, in addition to aluminum and polycrystalline silicon, metal-semiconductor compounds, superconducting substances, etc. can be used.
拡散抵抗とシールド材料の組み合わせも多くのものが可
能て、その中から抵抗の構造に黒点を絞り実施例をあげ
てゆく。Many combinations of diffused resistors and shielding materials are possible, and we will focus on the resistor structure and give examples.
第１３図は拡散抵抗の周囲を同じ拡散材料で覆った場合
の構造図である。第１３図（ａ）は平面図、第１３図（
ｂ）はＡ−Ｂ線の断面図である。FIG. 13 is a structural diagram when the periphery of the diffused resistor is covered with the same diffusion material. Figure 13(a) is a plan view, Figure 13(a) is a plan view;
b) is a sectional view taken along line AB.
拡散抵抗１３０が半導体基板１３９の浅い部分形成され
ており、その周１１１（ｔＪＩｉ方向）に同し拡散材？
．１ １ ３ ７を形成し、拡散抵抗１３０の上部を酸
化膜をはさんで覆うアルミニウム導体１３５は拡散材料
１３７とコンタクと１３６、１３８を介して接続され、
さらに電源ｖＳＳへ電位を与えられる。The diffused resistor 130 is formed in a shallow part of the semiconductor substrate 139, and the same diffused material is formed around the periphery 111 (tJIi direction).
．． 1 1 3 7 and covers the upper part of the diffused resistor 130 with an oxide film in between, the aluminum conductor 135 is connected to the diffused material 137 through contacts 136 and 138,
Furthermore, a potential is applied to the power supply vSS.
この構造により周囲のトランジスタのソース・ドレイン
・又は拡散抵抗からの電磁界ノイズを遮蔽する効果が高
まる。図中１３３、１３４は拡散抵抗１３０ヘコンタク
ト１３１、１３２を介して接続される１３５と同じ層の
アルミニウム電極線である。This structure increases the effect of shielding electromagnetic field noise from the source/drain of surrounding transistors or diffused resistance. In the figure, 133 and 134 are aluminum electrode lines in the same layer as 135, which are connected to the diffused resistor 130 via contacts 131 and 132.
第１４図は拡散抵抗の下層部にシールド導体を形成した
場合の構造図である。ｐ−基板１４３にＮ“埋め込み層
１４２があり、１４４、１４５は高不純物濃度のＮ型エ
ビタキシャル層で、コンタクト１４６によりＶＤＤへ電
位をとられている。FIG. 14 is a structural diagram when a shield conductor is formed in the lower layer of the diffused resistor. There is an N" buried layer 142 in the p-substrate 143, and 144 and 145 are N-type epitaxial layers with high impurity concentration, and the potential is taken to VDD by a contact 146.
１４０はＰ＋拡散抵抗で、酸化膜１４７をはさみ、の上
部をアルミニウム導体１４１で覆われており、アルミ導
体１４１の電位もＶＤＤとなっている。Reference numeral 140 denotes a P+ diffused resistor, which has an oxide film 147 sandwiched therebetween and whose upper part is covered with an aluminum conductor 141, and the potential of the aluminum conductor 141 is also VDD.
この構造の拡散低抗素子は、上下・左右からシールドさ
れる為、抵抗としての安定性、精度が極めて高い。The diffused low resistance element with this structure is shielded from the top, bottom, left and right, so it has extremely high stability and accuracy as a resistor.
この様に第１３図、第１４図の実施例では低抗素子の横
方向及び下方向に対するシールド効果がある為、半導体
集積装置に光やα線が照射された時に発生する電流路近
くのトランジスタのスイッチングによる基板電流の影響
を防ぐという大きな効果も有している。In this way, in the embodiments shown in FIGS. 13 and 14, since the low resistance element has a shielding effect in the lateral and downward directions, the transistors near the current path generated when the semiconductor integrated device is irradiated with light or alpha rays. It also has the great effect of preventing the effects of substrate current due to switching.
第１５図（ａ）は拡散抵抗の周囲をストッパーで囲んだ
場合の平面図で、第１５図（ｂ）はそのＡ−Ｂ線の断面
図である。Ｎ一基板で形成したｐ−ウエル１５９表面に
作られたＮ型拡散抵抗１５０の周囲にＰゝストッパー１
５７を形成し、コンタクト１５６、１５８によりアルミ
ニウム導体１５５からｖＳＳ電位を与える。この構造に
よれば、周囲からの電磁ノイズをシールドして防止する
他、ラッチアップ防止効果もある。FIG. 15(a) is a plan view when the diffused resistor is surrounded by a stopper, and FIG. 15(b) is a sectional view taken along the line A-B. A P-stopper 1 is placed around the N-type diffused resistor 150 formed on the surface of the P-well 159 formed of the N-substrate.
57, and contacts 156, 158 provide a vSS potential from aluminum conductor 155. This structure not only shields and prevents electromagnetic noise from the surroundings, but also has the effect of preventing latch-up.
この反転型半導体の場合、Ｎ一基板の上にＰ型拡散抵抗
を形成し、その周囲をＮゝストッパーで囲い、Ｎ＋スト
ッパー及び拡散抵抗２のアルミニウム導体にはＶＤＤを
与えることにより、やはり電磁ノイズシールド及びラッ
チアップ防止という効果がある。尚、図中、１５３、１
５４はアルミニウム導体と同層のアルミニウム電極線で
あり、コンタクト１５１、１５２を介して抵抗１５０に
接続される。In the case of this inverted semiconductor, a P-type diffused resistor is formed on the N-substrate, surrounded by an N-stopper, and VDD is applied to the N+ stopper and the aluminum conductor of the diffused resistor 2, which also prevents electromagnetic noise. It has the effect of shielding and preventing latch-up. In addition, in the figure, 153, 1
Reference numeral 54 denotes an aluminum electrode wire in the same layer as the aluminum conductor, and is connected to the resistor 150 via contacts 151 and 152.
これまで述べて来た拡散抵抗の周囲を一定電位を与えら
れた導体で覆うということによる静電遮蔽効果は、多結
晶シリコン抵抗の場合と同様前記一定電位の電源として
、ＶＳＳＳＶＤＤ，又はその中間電αでもかまわない。The electrostatic shielding effect of covering the diffused resistor with a conductor given a constant potential as described above can be achieved by using VSSSVDD or its intermediate voltage as the constant potential power source, as in the case of polycrystalline silicon resistors. α is also fine.
また、拡散抵抗に中間タップを設け、１本の拡散低抗素
子を分圧して使用する場合も、その周囲を一定電位に接
続された導体で覆うことにより、低抗素子の安定性が高
まるという効果がある。Furthermore, even when a diffused resistor is provided with an intermediate tap and a single diffused low-resistance element is used as a voltage divider, the stability of the low-resistance element is improved by surrounding it with a conductor connected to a constant potential. effective.
さらに複数の拡散低抗素子を用いる場合も前述と同様、
本発明が適用できる。Furthermore, when using multiple diffused low resistance elements, as described above,
The present invention is applicable.
第１６図は、本発明のシールド抵抗が高周波回路のディ
レイラインとして使えることを示す等価回路である。抵
抗１６０〜１６３の周囲は一定電位の導体で囲んである
ので、コンデンサ１６４〜１６７は常に安定な容量値を
得ることができ、またシールドされているので、抵抗値
の安定性も良い。信号はｖｉ側の抵抗端子から人力し、
出力にｖｏｕ７側の抵抗端子から取り出す。FIG. 16 is an equivalent circuit showing that the shield resistor of the present invention can be used as a delay line in a high frequency circuit. Since the resistors 160 to 163 are surrounded by a conductor having a constant potential, the capacitors 164 to 167 can always obtain a stable capacitance value, and since they are shielded, the stability of the resistance value is also good. The signal is input manually from the resistance terminal on the vi side,
Take out the output from the resistor terminal on the vou7 side.
以上述べてきた様に、本発明はその応用範囲が極めて広
い。As described above, the present invention has an extremely wide range of applications.
回路技術の中で最も基本的な受動素子である低抗素子の
精度を上げるということは、あらゆる電子回路の中で使
われる。特に抵抗の絶対値の精度が必要な発振回路、Ａ
／Ｄ変換回路、センサー回路、及び複数の低抗素子の相
対的な値（抵抗比）の猜度が必要なＤ／Ａ変換回路、電
圧検出回路、発振停止検出回路、さらに高抵抗としてで
きる限りリーク電流を抑止が必要なスタチックＲＡＭ，
ＥＰＲＯＭＳＦ２ ＰＲＯＭなどの電子デバイスを半導
体集積装置上に形成する場合、本発明は極めて利用しや
すいものである。Improving the accuracy of low resistance elements, which are the most basic passive elements in circuit technology, is used in all electronic circuits. Oscillation circuits that especially require precision in the absolute value of resistance, A
/D conversion circuits, sensor circuits, D/A conversion circuits that require precision in the relative values (resistance ratios) of multiple low resistance elements, voltage detection circuits, oscillation stop detection circuits, and leakage as much as possible with high resistance. Static RAM that requires current suppression,
The present invention is extremely easy to use when forming electronic devices such as EPROMSF2 PROMs on semiconductor integrated devices.
さらに本発明の低抗素子をシールド導体で覆うという技
術は、容量、トランジスタ、等の周囲をシールド導体で
覆うということにも応川可能で、容量、トランジスタの
安定性を上げることができる。Furthermore, the technique of covering the low resistance element of the present invention with a shield conductor can also be applied to covering the periphery of a capacitor, transistor, etc. with a shield conductor, and the stability of the capacitor or transistor can be improved.
本発明は、既存の製造工程を用いて、低抗素子の周辺構
造パターンを少し付加するだけという簡単な横或で、低
抗素子としての安定性、情度が向上する為、その応用範
囲が極めて広い。The present invention improves the stability and performance of a low resistance element by simply adding a small amount of peripheral structure pattern to the low resistance element using the existing manufacturing process, so its range of application is wide. Extremely spacious.
低抗素子の安定性、精度が向上するとは、低抗素子とし
ての絶対値、あるいは複数の低抗素子を用いた時の相対
抵抗比に関して、周囲の電磁界ノイズの影響を受けにく
くなるということである。Improving the stability and accuracy of a low resistance element means that the absolute value of the low resistance element, or the relative resistance ratio when multiple low resistance elements are used, is less susceptible to the effects of surrounding electromagnetic field noise. It is.
また低抗素子の表面（一般には酸化膜）１＠位がフロー
ティングにならない様にする為、イオン等の影響を受け
にくくなり、抵抗値の経年変動を防止できる。Furthermore, since the surface (generally an oxide film) of the low resistance element is prevented from floating, it is less susceptible to the effects of ions, etc., and changes in resistance value over time can be prevented.
さらに光により低抗素子特性が変動することが防止でき
る。Furthermore, it is possible to prevent the characteristics of the low resistance element from changing due to light.
そして低抗素子自体から発生する電磁界ノイズを軽減す
ることができる。In addition, electromagnetic field noise generated from the low resistance element itself can be reduced.
また低濃度拡散により精度の良い高低抗素子が実現でき
る為、必要面積が少なくなり、結果的に半導体集積装置
を高集積化できる。Furthermore, since a highly accurate high-low resistance element can be realized by low-concentration diffusion, the required area is reduced, and as a result, a semiconductor integrated device can be highly integrated.
第１図は本発明の多結晶シリコンによる低抗素子の構造
図。
第２図は本発明の拡散低抗素子の構造図。
第３図は従来の多結晶シリコンによる低抗素子の構造図
。
第４図は従来の拡散低抗素子の構造図。
第５図はＬＯＣＯＳ上に形成した本発明の多結晶シリコ
ン抵抗の構造図。
第６図はＬＯＣＯＳ下にストッパーを設けた時の本発明
の多結晶シリコン抵抗の構造図。
第７図（ａ）は、周辺を低抗素子と同じ材料で囲んだ本
発明の多結晶シリコン抵抗の平面図、第７．図（ｂ）は
その断面図。
第８図は低抗素子の上下層を導体で覆った本発明の多結
晶シリコン抵抗の構造図。
第９図（ａ）は低抗素子を覆う導体の電位をＶＤＤにし
た、本発明の多結晶シリコン抵抗の構造図、第９図（ｂ
）は導体の電位をトランジスタの出力とした時の一回路
例を示す図。
第１０図は中間タップで出力電圧を抵抗分割する時の本
発明による低抗素子の応用回路図。
第１１図は、複数の低抗素子で出力電圧を抵抗分割する
時の本発明による低抗素子の応用回路図。
第１２図は二層金属配線による本発明の多結晶ボリシリ
コン抵抗の断面図。
第１３図（ａ）周辺を抵抗と同じ材料で覆った本発明に
よる拡散抵抗の平面図、第１３図（ｂ）はその断面図。
第１４図は抵抗の上下層をシールド導体で覆った本発明
の拡散低抗素子の断面図。
第１５図（ａ）は周辺をストッパーで囲った本発明の拡
散低抗素子の平面図、第１５図（ｂ）はその断面図。
第１６図はシールド導体で覆われた本発明の低抗素子を
高周波回路のディレイラインとして使用した場合の等価
回路図。
５ ３ ◆ ●
・ ＬＯＣＯＳ
６ ５ ・
●・ストッパー
以 上FIG. 1 is a structural diagram of a low resistance element made of polycrystalline silicon according to the present invention. FIG. 2 is a structural diagram of the diffused low resistance element of the present invention. Figure 3 is a structural diagram of a conventional low resistance element made of polycrystalline silicon. Figure 4 is a structural diagram of a conventional diffused low resistance element. FIG. 5 is a structural diagram of a polycrystalline silicon resistor of the present invention formed on LOCOS. FIG. 6 is a structural diagram of the polycrystalline silicon resistor of the present invention when a stopper is provided below the LOCOS. FIG. 7(a) is a plan view of a polycrystalline silicon resistor of the present invention whose periphery is surrounded by the same material as the low resistance element. Figure (b) is a cross-sectional view. FIG. 8 is a structural diagram of a polycrystalline silicon resistor of the present invention in which the upper and lower layers of a low resistance element are covered with conductors. FIG. 9(a) is a structural diagram of the polycrystalline silicon resistor of the present invention in which the potential of the conductor covering the low resistance element is set to VDD, and FIG. 9(b)
) is a diagram showing an example of a circuit when the potential of a conductor is used as the output of a transistor. FIG. 10 is an application circuit diagram of the low resistance element according to the present invention when resistively dividing the output voltage by an intermediate tap. FIG. 11 is an application circuit diagram of the low resistance element according to the present invention when the output voltage is resistance-divided by a plurality of low resistance elements. FIG. 12 is a cross-sectional view of the polycrystalline polysilicon resistor of the present invention with two-layer metal wiring. FIG. 13(a) is a plan view of a diffused resistor according to the present invention whose periphery is covered with the same material as the resistor, and FIG. 13(b) is a cross-sectional view thereof. FIG. 14 is a sectional view of a diffused low resistance element of the present invention in which the upper and lower layers of a resistor are covered with shield conductors. FIG. 15(a) is a plan view of a diffused low resistance element of the present invention surrounded by a stopper, and FIG. 15(b) is a sectional view thereof. FIG. 16 is an equivalent circuit diagram when the low resistance element of the present invention covered with a shield conductor is used as a delay line of a high frequency circuit. 5 3 ◆ ● ・ LOCOS 6 5 ・ ●・Stopper or more
Claims (30)
右少なくとも１辺を低抵抗導体で覆い、前記低抵抗導体
は電源に対して一定電位に保たれていることを特徴とす
る半導体装置。(1) A semiconductor device characterized in that a resistive element made of polycrystalline silicon is covered with a low-resistance conductor on at least one of the upper, lower, left and right sides, and the low-resistance conductor is maintained at a constant potential with respect to a power source.
ＣＯＳ）の上部に前記多結晶シリコンを形成したことを
特徴とする請求項１記載の半導体装置。(2) Selective oxide film (hereinafter referred to as LO) formed on the semiconductor substrate
2. The semiconductor device according to claim 1, wherein the polycrystalline silicon is formed on top of a COS.
濃度拡散領域を設け一定の電位を与えたことを特徴とす
る請求項２記載の半導体装置。(3) The semiconductor device according to claim 2, wherein a high concentration diffusion region is provided under the LOCOS formed on the semiconductor substrate and a constant potential is applied thereto.
の層に前記導体を形成し、前記導体を一定電位に保つこ
とを特徴とする請求項１記載の半導体装置。(4) The semiconductor device according to claim 1, wherein the conductor is formed in the same layer as the resistance element formed of polycrystalline silicon, and the conductor is maintained at a constant potential.
を前記低抵抗導体で覆い、前記低抵抗導体を一定電位に
保つことを特徴とする請求項１記載の半導体装置。(5) The semiconductor device according to claim 1, wherein an upper part of the resistance element made of polycrystalline silicon is covered with the low resistance conductor, and the low resistance conductor is maintained at a constant potential.
を前記低抵抗導体で覆い、前記低抵抗導体を一定電位に
保つことを特徴とする請求項１記載の半導体装置。(6) The semiconductor device according to claim 1, wherein a lower part of the resistance element formed of polycrystalline silicon is covered with the low resistance conductor, and the low resistance conductor is maintained at a constant potential.
ＤＤ）としたことを特徴とする請求項１記載の半導体装
置。(7) The potential of the low resistance conductor is set to the high potential of the semiconductor device (V
2. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device (DD).
ＳＳ）としたことを特徴とする請求項１記載の半導体装
置。(8) The potential of the low resistance conductor is set to the low potential of the semiconductor device (V
2. The semiconductor device according to claim 1, wherein the semiconductor device is SS).
電位の中間電位とすることを特徴とする請求項１記載の
半導体装置。(9) The semiconductor device according to claim 1, wherein the potential of the low resistance conductor is set to an intermediate potential between a high potential and a low potential of the semiconductor device.
同一又は大きくし、前記抵抗素子の上部又は下部へ形成
したことを特徴とする請求項１記載の半導体装置。(10) The semiconductor device according to claim 1, wherein the outer periphery of the low resistance conductor is the same as or larger than the outer periphery of the resistance element, and is formed above or below the resistance element.
除く領域について、その上部又は下部を前記低抵抗導体
で覆うことを特徴とした請求項１記載の半導体装置。(11) The semiconductor device according to claim 1, wherein an upper or lower portion of a region other than a contact portion located at both ends of the resistor element is covered with the low-resistance conductor.
ＶＤＤ又はＶＳＳ又は中間電位）として動作させ、前記
低抵抗導体の電位を前記定電源電位としたことを特徴と
する請求項１記載の半導体装置。(12) Connect at least one end of the resistive element to a constant power supply potential (
2. The semiconductor device according to claim 1, wherein the semiconductor device is operated at a voltage of VDD, VSS, or an intermediate potential, and the potential of the low resistance conductor is set as the constant power supply potential.
微量にした高抵抗多結晶シリコンとしたことを特徴とす
る請求項１記載の半導体装置。(13) The semiconductor device according to claim 1, wherein the material of the resistance element is high-resistance polycrystalline silicon into which a small amount of ions are implanted.
）を複数設け、複数の抵抗素子として使用して、この複
数の抵抗素子の上部又は下部を共通の一定電位を持つ前
記低抵抗導体で覆うことを特徴とする請求項１記載の半
導体装置。(14) Providing a plurality of intermediate taps (contacts) on one resistor element, using it as a plurality of resistor elements, and covering the upper or lower part of the plurality of resistor elements with the low-resistance conductor having a common constant potential. The semiconductor device according to claim 1, characterized in that:
接して配置し、この複数の抵抗素子の上部又は下部を共
通の電位を持つ前記低抵抗導体で覆うことを特徴とする
請求項１記載の半導体装置。(15) A plurality of the resistance elements are formed of the same material, are arranged adjacent to each other, and upper or lower parts of the plurality of resistance elements are covered with the low resistance conductor having a common potential. 1. The semiconductor device according to 1.
辺を低抵抗導体で覆い、この低抵抗導体は電源に対して
一定に保たれていることを特徴とする半導体装置。(16) A semiconductor device characterized in that at least one side of a resistance element formed of a diffused resistor is covered with a low resistance conductor, and the low resistance conductor is kept constant with respect to a power source.
低抗素子と同一材料の前記導体を配置し、この導体に一
定電位を与えたことを特徴とする請求項１６記載の半導
体装置。(17) The semiconductor device according to claim 16, wherein the conductor made of the same material as the low resistance element is arranged along at least one side of the resistance element, and a constant potential is applied to the conductor.
度の拡散領域を設け、この拡散領域に一定の電圧を与え
ことを特徴とする請求項１６記載の半導体装置。(18) The semiconductor device according to claim 16, characterized in that a highly doped diffusion region is provided along at least one side of the resistance element, and a constant voltage is applied to the diffusion region.
この低抵抗導体に一定電位を与えたことを特徴とする請
求項１６記載の半導体装置。(19) covering the upper part of the resistance element with the low resistance conductor;
17. The semiconductor device according to claim 16, wherein a constant potential is applied to the low resistance conductor.
この低抵抗導体に一定電位を与えたことを特徴とする請
求項１６記載の半導体装置。(20) covering a lower part of the resistance element with the low resistance conductor;
17. The semiconductor device according to claim 16, wherein a constant potential is applied to the low resistance conductor.
たことを特徴とする請求項１６記載の半導体装置。(21) The semiconductor device according to claim 16, wherein the potential of the low resistance conductor is set to a high potential (VDD).
たことを特徴とする請求項１６記載の半導体装置。(22) The semiconductor device according to claim 16, wherein the potential of the low resistance conductor is set to a low potential (VSS).
電位とすることを特徴とする請求項１６記載の半導体装
置。(23) The semiconductor device according to claim 16, wherein the potential of the low resistance conductor is set to an intermediate potential between a high potential and a low potential.
同一又は大きくして、前記抵抗素子の上部又は下部へ形
成したことを特徴とする請求項１６記載の半導体装置。(24) The semiconductor device according to claim 16, wherein the outer periphery of the low resistance conductor is the same as or larger than the outer periphery of the resistance element, and is formed above or below the resistance element.
除く領域について、その上部又は下部へ前記低抵抗導体
を形成したことを特徴とする請求項１６記載の半導体装
置。(25) The semiconductor device according to claim 16, wherein the low resistance conductor is formed above or below a region other than a contact portion located at both ends of the resistance element.
ＶＤＤ又はＶＳＳ又は中間電位）として使用し、前記低
抵抗導体の電位を前記定電源電位としたことを特徴とす
る請求項１６記載の半導体装置。(26) Connect at least one end of the resistance element to a constant power supply potential (
17. The semiconductor device according to claim 16, wherein the potential of the low resistance conductor is used as the constant power supply potential.
）を複数設け、複数の抵抗素子として使用して、この複
数の抵抗素子の上部又は下部へ共通の一定電位を持つ前
記低抵抗導体を形成することを特徴とする請求項１６記
載の半導体装置。(27) One resistor element is provided with a plurality of intermediate taps (contacts) and used as a plurality of resistor elements, and the low resistance conductor having a common constant potential is formed above or below the plurality of resistor elements. 17. The semiconductor device according to claim 16.
して配置し、この複数の抵抗素子の上部又は下部が共通
の一定電位を持つ前記低抵抗導体を形成することを特徴
とする請求項１６記載の半導体装置。(28) A claim characterized in that a plurality of the resistance elements are formed of the same material and arranged adjacent to each other, and the upper or lower parts of the plurality of resistance elements form the low resistance conductor having a common constant potential. 17. The semiconductor device according to item 16.
特徴とする請求項１６記載の半導体装置。(29) The semiconductor device according to claim 16, wherein the diffused resistor is formed by low concentration diffusion.
を特徴とする請求項１６記載の半導体装置。(30) The semiconductor device according to claim 16, wherein the diffused resistor is formed by ion implantation.
Priority Applications (8)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9301741A GB2262187A (en) | 1988-11-22 | 1989-11-21 | Semiconductor resistors |
| PCT/JP1989/001180 WO1990005995A1 (en) | 1988-11-22 | 1989-11-21 | Semiconductor device |
| GB9015141A GB2232530B (en) | 1988-11-22 | 1989-11-21 | A high precision semiconductor resistor device |
| KR1019900701560A KR900702572A (en) | 1988-11-22 | 1990-07-20 | Semiconductor device |
| US07/965,545 US5428242A (en) | 1988-11-22 | 1992-10-23 | Semiconductor devices with shielding for resistance elements |
| GB9301742A GB2262188B (en) | 1988-11-22 | 1993-01-29 | A high precision semiconductor resistor device |
| HK105997A HK105997A (en) | 1988-11-22 | 1997-06-26 | A high precision semiconductor resistor device |
| HK120897A HK120897A (en) | 1988-11-22 | 1997-06-26 | A high precision semiconductor resistor device |
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29508388 | 1988-11-22 | ||
| JP63-295083 | 1988-11-22 | ||
| JP8109489 | 1989-03-31 | ||
| JP1-81094 | 1989-03-31 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0316164A true JPH0316164A (en) | 1991-01-24 |
| JP2864576B2 JP2864576B2 (en) | 1999-03-03 |
Family
ID=26422135
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1290499A Expired - Lifetime JP2864576B2 (en) | 1988-11-22 | 1989-11-08 | Semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2864576B2 (en) |
| KR (1) | KR900702572A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5903033A (en) * | 1996-11-29 | 1999-05-11 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device including resistance element with superior noise immunity |
| JP2004273685A (en) * | 2003-03-07 | 2004-09-30 | Taiyo Yuden Co Ltd | High frequency module |
| JP2006049581A (en) * | 2004-08-04 | 2006-02-16 | Seiko Instruments Inc | Resistance circuit |
| JP2006269573A (en) * | 2005-03-23 | 2006-10-05 | Seiko Instruments Inc | Semiconductor device |
| JP2007085901A (en) * | 2005-09-22 | 2007-04-05 | Yazaki Corp | Voltage-dividing circuit |
| US7439146B1 (en) * | 2000-08-30 | 2008-10-21 | Agere Systems Inc. | Field plated resistor with enhanced routing area thereover |
| KR100880506B1 (en) * | 2002-03-19 | 2009-01-28 | 후지쯔 마이크로일렉트로닉스 가부시키가이샤 | Shield structure for semiconductor integrated circuit |
| WO2016056212A1 (en) * | 2014-10-07 | 2016-04-14 | 株式会社デンソー | Semiconductor device and manufacturing method therefor |
| JP2016076692A (en) * | 2014-10-07 | 2016-05-12 | 株式会社デンソー | Semiconductor device and method of manufacturing the same |
-
1989
- 1989-11-08 JP JP1290499A patent/JP2864576B2/en not_active Expired - Lifetime
-
1990
- 1990-07-20 KR KR1019900701560A patent/KR900702572A/en not_active Application Discontinuation
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5903033A (en) * | 1996-11-29 | 1999-05-11 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device including resistance element with superior noise immunity |
| KR100286782B1 (en) * | 1996-11-29 | 2001-04-16 | 다니구찌 이찌로오, 기타오카 다카시 | Semiconductor device including resistance element with superior noise immunity |
| US7439146B1 (en) * | 2000-08-30 | 2008-10-21 | Agere Systems Inc. | Field plated resistor with enhanced routing area thereover |
| KR100880506B1 (en) * | 2002-03-19 | 2009-01-28 | 후지쯔 마이크로일렉트로닉스 가부시키가이샤 | Shield structure for semiconductor integrated circuit |
| JP2004273685A (en) * | 2003-03-07 | 2004-09-30 | Taiyo Yuden Co Ltd | High frequency module |
| JP2006049581A (en) * | 2004-08-04 | 2006-02-16 | Seiko Instruments Inc | Resistance circuit |
| JP4723827B2 (en) * | 2004-08-04 | 2011-07-13 | セイコーインスツル株式会社 | Resistance circuit |
| JP2006269573A (en) * | 2005-03-23 | 2006-10-05 | Seiko Instruments Inc | Semiconductor device |
| JP2007085901A (en) * | 2005-09-22 | 2007-04-05 | Yazaki Corp | Voltage-dividing circuit |
| WO2016056212A1 (en) * | 2014-10-07 | 2016-04-14 | 株式会社デンソー | Semiconductor device and manufacturing method therefor |
| JP2016076692A (en) * | 2014-10-07 | 2016-05-12 | 株式会社デンソー | Semiconductor device and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2864576B2 (en) | 1999-03-03 |
| KR900702572A (en) | 1990-12-07 |
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