JPH03154337A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03154337A JPH03154337A JP1292346A JP29234689A JPH03154337A JP H03154337 A JPH03154337 A JP H03154337A JP 1292346 A JP1292346 A JP 1292346A JP 29234689 A JP29234689 A JP 29234689A JP H03154337 A JPH03154337 A JP H03154337A
- Authority
- JP
- Japan
- Prior art keywords
- etching
- hole
- film
- insulating film
- aspect ratio
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 238000005530 etching Methods 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 230000008021 deposition Effects 0.000 claims description 3
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 5
- 238000001039 wet etching Methods 0.000 abstract description 3
- 238000004380 ashing Methods 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 10
- 239000003990 capacitor Substances 0.000 description 6
- 150000004767 nitrides Chemical class 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000010419 fine particle Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の製造方法に係り、特にアスペク
ト比（高さ７幅）の大きい孔部分の絶縁膜のエツチング
に好適なエツチング方法に関する６〔従来の技術〕
ＬＳＩの高集積化に伴い、ＤＲＡＭでは電荷蓄積量増大
のため溝型キャパシタ等の立体的な携造をもつセルが用
いられる。この溝型キャパシタにおいては、プレート電
極と溝側面の半導体基板を絶縁する。サヤ（鞘）型絶縁
膜を形成する必要がある。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to an etching method suitable for etching an insulating film in a hole portion having a large aspect ratio (height 7 width). 6 [Prior Art] As LSIs become more highly integrated, cells with three-dimensional structures such as trench-type capacitors are used in DRAMs to increase the amount of charge storage. In this trench type capacitor, the plate electrode and the semiconductor substrate on the side surface of the trench are insulated. It is necessary to form a shell-type insulating film.
従来の技術としては１例えば特開昭６２−７９６５９に
記載のように、まず、窒化Ｓｉ膜をマスクとして、異方
性シリコンエッチにより深孔を開け５次に熱酸化法によ
り孔内を酸化し、異方性酸化Ｓｉ模膜ドライエツチング
法用いて孔底の酸化Ｓｉ膜を除去している。この方法を
第２図に示す。この方法では、基板１上に深孔を開ける
ときのマスクとして用いた窒化Ｓｉ膜４が孔底以外の酸
化５ｉＩｌＩ２のエツチングを抑制するストッパとなっ
ており、孔底の酸化Ｓｉ膜のみのエツチングが可能にな
っている。As a conventional technique, 1, for example, as described in JP-A-62-79659, a deep hole is first made by anisotropic silicon etching using a Si nitride film as a mask, and 5, the inside of the hole is oxidized by a thermal oxidation method. The Si oxide film at the bottom of the hole was removed using an anisotropic Si oxide mock film dry etching method. This method is illustrated in FIG. In this method, the Si nitride film 4 used as a mask when drilling a deep hole on the substrate 1 acts as a stopper to suppress etching of the 5iIlI2 oxide other than at the bottom of the hole, so that only the Si oxide film at the bottom of the hole is etched. It is now possible.
上記従来技術においては、孔底のエツチングと同時に進
行する表面でのエツチングを抑制するための［（ストッ
パ）が必要となるため、異種の膜の堆積及び除去工程が
必要であり、工程がはん雑となる。また、従来のドライ
エツチング法を用いると一般に、アスペクト比の大きい
微細なパターンでのエツチング速度は、広いパターンと
比較して遅くなる傾向があるので、寸法の微細化に伴い
ストッパは厚くしなければならないという問題が生じる
可能性もあった。In the above conventional technology, a stopper is required to suppress etching on the surface that progresses at the same time as etching on the bottom of the hole, so a process of depositing and removing a different type of film is required, and the process is complicated. It becomes sloppy. Additionally, when using conventional dry etching methods, the etching speed for fine patterns with a large aspect ratio tends to be slower than for wide patterns, so the stopper must be made thicker as the dimensions become finer. There was also the possibility that a problem would arise.
本発明の目的は、基板表面の絶縁膜をエツチングするこ
となく、アスペクト比の大きい孔部もしくは溝の底の絶
縁膜のみを選択的にエツチングする方法を提供すること
にある。An object of the present invention is to provide a method for selectively etching only the insulating film at the bottom of a hole or trench having a large aspect ratio, without etching the insulating film on the surface of the substrate.
上記目的は、基板表面などのアスペクト比の小さいパタ
ーンのみにＣＨ系被被膜堆積させてエツチングを抑制し
、深孔底部などのアスペクト比の大きいパターンの絶縁
膜のみを選択的にエツチングさせることで達成される。The above objective is achieved by suppressing etching by depositing a CH-based film only on patterns with a small aspect ratio, such as the substrate surface, and selectively etching only the insulating film on patterns with a large aspect ratio, such as the bottom of a deep hole. be done.
〔作用〕
アスペクト比の大きいパターンを被覆した絶縁膜をエツ
チングする場合、エツチングガスとしてＨを多く含むフ
レオン系ガス、あるいはＨをあまり含まないフレオンガ
スとＨｚガスの混合ガスを用いることにより、アスペク
ト比の大きいパターン底部以外の絶縁膜表面をＨＣ系堆
積膜で被覆でき、このＣＨＨ堆積膜で被覆されていない
、アスペクト比の大きいパターン底部の絶縁膜のみを選
択的にエツチングすることができる。[Operation] When etching an insulating film covering a pattern with a large aspect ratio, the aspect ratio can be improved by using a Freon gas containing a large amount of H as the etching gas, or a mixed gas of Freon gas and Hz gas containing little H. The surface of the insulating film other than the bottom of the large pattern can be covered with the HC deposited film, and only the insulating film at the bottom of the pattern with a large aspect ratio, which is not covered with the CHH deposited film, can be selectively etched.
〈実施例１〉 以下に本発明の一実施例を、第１図を用いて説明する。 <Example 1> An embodiment of the present invention will be described below with reference to FIG.
まず、半導体基板１にレジストあるいはＳ ｉ Ｏｚを
マスクとして、周知のＲＩＥ （反応性イオンエツチン
グ）により深孔を開け、その後マスク材料を、レジスト
は周知のプラズマアッシングで。First, a deep hole is made in the semiconductor substrate 1 by the well-known RIE (reactive ion etching) using a resist or SiOz as a mask, and then a mask material is applied and the resist is formed by the well-known plasma ashing.
５ｉＯｚは周知のＨＦ溶液によりウェットエツチングで
除去して、第１図（ａ）のように構造を得る。5iOz is removed by wet etching using a well-known HF solution to obtain the structure shown in FIG. 1(a).
次に第１図（ｂ）の如く１周知のＣＶＤ （化学気相成
長法）により酸化Ｓｉ膜２を堆積する。ここで、堆積す
る膜は、窒化Ｓｉでもよい。Next, as shown in FIG. 1(b), a Si oxide film 2 is deposited by a well-known CVD (chemical vapor deposition method). Here, the deposited film may be Si nitride.
次に、平行平板型ＲＩＥ装置を用い、ＣＨｚ Ｆ ｚガ
スをエツチングガスとして後述の条件範囲でエツチング
を行なうと第１図（ｃ）の如く、アスペクト比（孔の深
さ／孔径）の大きい微細な孔底の酸化Ｓｉ膜のみがエツ
チングされ、それ以外の膜はほとんどエツチングされな
い。Next, when etching is performed using a parallel plate type RIE device and using CHz Fz gas as an etching gas under the conditions described below, fine particles with a large aspect ratio (hole depth/hole diameter) are formed as shown in Figure 1(c). Only the Si oxide film at the bottom of the hole is etched, and the other films are hardly etched.
このような現象は、孔のアスペクト比、エツチングガス
種、ガス圧力、ＲＦパワー等の加工条件に応じて生じる
ものである１本発明においては、直径２０ａ１の平行平
板電極をもつ枚葉式ＲＩ Ｅ装置を用いてエツチングを
行なった。ＲＦパワー２００Ｗ、周波数１３．５６ＭＨ
ｚ 、ガス圧力５０ ｍＴｏｒｒ、ガス流量１０５Ｃ
Ｃ：Ｍの条件で、アスペクト比２以上の孔の底のエツチ
ングのみが進行るるようになり、第１図に示すようなエ
ツチングが可能となる。Such a phenomenon occurs depending on the processing conditions such as the aspect ratio of the hole, the type of etching gas, the gas pressure, and the RF power.1 In the present invention, a single-wafer type RI E having parallel plate electrodes with a diameter of 20a1 is used. Etching was performed using the device. RF power 200W, frequency 13.56MH
z, gas pressure 50 mTorr, gas flow rate 105C
Under the conditions of C:M, etching only proceeds at the bottom of holes with an aspect ratio of 2 or more, and etching as shown in FIG. 1 becomes possible.
また、安定して孔の底のみを完全に且つ選択的にエツチ
ングするには孔のアスペクト比は２以上としておくこと
が好ましい、ここで、本発明を用いた場合、アスペクト
比２以下の孔もしくは溝上の絶縁膜はエツチングされな
いが、実際に本発明を用いる微細パターンでは、孔もし
くは溝の寸法は一定であり、アスペクト比は全て２以上
となるため問題はない。In addition, in order to stably and completely and selectively etch only the bottom of the hole, it is preferable that the aspect ratio of the hole is 2 or more. Although the insulating film on the grooves is not etched, there is no problem because in actual fine patterns using the present invention, the dimensions of the holes or grooves are constant and the aspect ratios are all 2 or more.
ここで、エツチングガスとしては、ＣＨａ Ｆ 。Here, the etching gas is CHaF.
Ｃｚ Ｈａ Ｆ ｘ等のＨを多く含むフレオン系ガス単
独。Freon-based gas containing a lot of H such as Cz Ha F x alone.
あるいはＣＦａを始めとするフレオンガスにＨ２あるい
はＣＨ４等のＨを多く含むガスを添加してもよい。Alternatively, a gas containing a large amount of H such as H2 or CH4 may be added to Freon gas such as CFa.
このようなエツチングは１次のようなメカニズムによる
と考えられる。Such etching is thought to be due to a first-order mechanism.
酸化Ｓｉ膜のエツチングにＣＨｚＦｚＨスを用いると、
酸化Ｓｉ膜表面にはＣＨ系の膜の堆積も同時に進行し、
エツチング速度が低下する。しかし、アスペクト比の大
きい深孔には堆積粒子ガ進入しにくいため、ＣＨ系の膜
は堆積せず、エツチングだけが進行する。ここで、ＣＨ
系膜の堆積がより起こりやすい条件でエツチングを行な
えば、アスペクト比の大きい孔底の酸化Ｓｉ膜のみがエ
ッチングされるようになる。従って、ガス流量を多くす
る。Ｈｘ混合比を大きくする。イオン方向性が悪くなら
ない範囲（１０〜５００ ｍＴｏｒｒ）でガス圧を高く
する等、高アスペクト比の孔底を被覆しない範囲で多量
の堆積物が生じる条件を用いることが望ましい。When CHzFzH gas is used for etching the Si oxide film,
At the same time, a CH-based film also progresses on the surface of the Si oxide film.
Etching speed decreases. However, since it is difficult for deposited particles to enter deep holes with a large aspect ratio, a CH-based film is not deposited and only etching progresses. Here, CH
If etching is performed under conditions where the deposition of the system film is more likely to occur, only the Si oxide film at the bottom of the hole having a large aspect ratio will be etched. Therefore, increase the gas flow rate. Increase the Hx mixing ratio. It is desirable to use conditions that produce a large amount of deposits without covering the bottom of a hole with a high aspect ratio, such as increasing the gas pressure within a range that does not deteriorate ion directionality (10 to 500 mTorr).
〈実施例２〉
本発明の第２の実施例について第３図を用いて説明する
。<Example 2> A second example of the present invention will be described using FIG. 3.
まず、第３図（ａ）の如く、酸化Ｓｉ膜上にレジストマ
スクパターン５を形成し、第３図（ｂ）の如く周知のＲ
Ｉ 、Ｅにより一層目酸化Ｓｉ膜６をエツチングし、レ
ジストパターンを除去する。ここで、−層目酸化Ｓｉ膜
６は５窒化Ｓｉ膜等、他の絶縁膜でもよい。次に、第３
図（ｂ）の如く、周知のＣＶＤにより二層目酸化Ｓｉ膜
７を堆積する。ここで、二層目酸化Ｓｉ膜７は窒化Ｓｉ
膜等、他の絶縁膜でもよい６次に、第３図（ｄ）の如く
。First, as shown in FIG. 3(a), a resist mask pattern 5 is formed on the Si oxide film, and as shown in FIG. 3(b), a well-known R
The first layer Si oxide film 6 is etched using I and E, and the resist pattern is removed. Here, the -th layer Si oxide film 6 may be another insulating film such as a pentanitride Si film. Next, the third
As shown in Figure (b), a second layer Si oxide film 7 is deposited by well-known CVD. Here, the second layer Si oxide film 7 is made of Si nitride.
The 6th order may be any other insulating film, such as a film, as shown in FIG. 3(d).
実施例１で示した条件よりＲＦパワーを上げた条件（３
００〜６００Ｗ）でエツチングを行なえば、−層［１酸
化Ｓ ｉ Ｉｌｌ ６を削ることなく、パターン上部が
テーパー状で、かつ、レジストマスク５により得られた
パターンより微細なパターンが得られる。すなわち、本
発明を用いることにより、光リングラフィでは得にくい
０．３μｍ以下の微細なパターンでも、ＥＢ（電子１り
リソグラフィ等を用いずに、従来の簡便な方法だけで
得ることができる。Conditions where the RF power was increased from the conditions shown in Example 1 (3
00 to 600 W), a pattern with a tapered upper part and a finer pattern than the pattern obtained with the resist mask 5 can be obtained without cutting the -layer [monooxide Si Ill 6]. That is, by using the present invention, even fine patterns of 0.3 μm or less, which are difficult to obtain with photophosphorography, can be obtained using conventional simple methods without using EB (electron lithography) or the like.
また１本実施例で得られたパターンは、パターン上部が
テーパ状となっており、ＡＱ、Ｗ等の配線材料の被覆特
性（カバレジ）がよく、かつ微細であるため、コンタク
トホールとして用いることができる。また第二Ｍ目酸化
シリコン膜は第−層酸化シリコン表面上に残るので、層
間絶縁膜を厚くする効果もある。なお、エツチング時に
付着した堆積物３はＯｚプラズマを用いたアッシャで容
易に除去できる（第３図（ｅ））ので、ウェハ汚染等の
問題はない。In addition, the pattern obtained in this example has a tapered upper part, has good coverage of wiring materials such as AQ and W, and is fine, so it can be used as a contact hole. can. Furthermore, since the second M-th silicon oxide film remains on the surface of the first silicon oxide layer, it also has the effect of increasing the thickness of the interlayer insulating film. Incidentally, since the deposit 3 attached during etching can be easily removed by an asher using Oz plasma (FIG. 3(e)), there is no problem such as wafer contamination.
〈実施例３〉 本発明の第３の実施例を第４図を用いて説明する。<Example 3> A third embodiment of the present invention will be described using FIG. 4.
まず、第４図（ａ）のような構造を、実施例１で示した
条件及び方法で形成する。次に、第４図（ｂ）の如く、
温度８００℃で、ＨＣｎ ＋ＳｉＣＱ ｚＨｚを、デポ
ジション用のガスとしてＳｉ基板が露出しているところ
に選択的にＳｉをエピタキシアル成長させる。本発明に
よれば、アスペクト比の大きいパターンの底部の絶縁膜
のみをエツチングできるので、アスペクト比の大きい孔
、もしくは溝の底部のみ、Ｓｉ基板を露出させることが
できる。First, a structure as shown in FIG. 4(a) is formed under the conditions and method shown in Example 1. Next, as shown in Figure 4(b),
At a temperature of 800° C., HCn + SiCQ zHz is used as a deposition gas to selectively epitaxially grow Si on exposed portions of the Si substrate. According to the present invention, only the insulating film at the bottom of a pattern with a large aspect ratio can be etched, so that only the bottom of a hole or groove with a large aspect ratio can be exposed.
これにより、上記エピタキシアル成長を行なえば。This allows the epitaxial growth described above to be performed.
孔もしくは溝をＳｉで埋め込むことができる。The holes or grooves can be filled with Si.
次に、フッ酸水溶液でウェットエツチングを行ない、第
４図（ｃ）のような構造とすれば、孔もしくは溝部分を
アイソレーション領域１０となり、基板表面はアクティ
ブ領域９となる。ここで、孔もしくは溝側壁の絶縁膜の
みをアイソレーションとして、Ｓｉエピタキシアル成長
領域１１もアクティブ領域として用いてもよい。これに
より、微細なアイソレーションが可能となる。Next, wet etching is performed using an aqueous hydrofluoric acid solution to form a structure as shown in FIG. 4(c), with the hole or groove portion becoming the isolation region 10 and the substrate surface becoming the active region 9. Here, only the insulating film on the side wall of the hole or trench may be used as isolation, and the Si epitaxial growth region 11 may also be used as the active region. This enables fine isolation.
〈実施例４〉
最後に、本発明の第４の実施例を、第５図を用いて説明
する。<Embodiment 4> Finally, a fourth embodiment of the present invention will be described using FIG. 5.
まず、実施例１で示した条件および方法で、第５図（ａ
）のような構造を形成する０次に、−層目多結晶Ｓｉ膜
１２，５〜１５ｎｍの薄い酸化Ｓｉ膜１４．二層目多結
晶Ｓｉ膜１３を公知のＣＶＤ法により堆積し、第５図（
ｂ）のような構造にすれば、−層目多結晶Ｓｉ膜１２と
二層目多結晶Ｓｉ膜１３の間に電荷を？＃積するキャパ
シタとなる。このようなキャパシタはサヤ状絶縁膜によ
り周囲と絶縁されているので、高密度に形成してもキャ
パシタ間のリーク電流を発生することがなく、大規模Ｄ
ＲＡＭ用の記憶電荷蓄積用キャパシタとして有効である
。First, under the conditions and method shown in Example 1, FIG.
) to form a structure such as 0-th order, -th layer polycrystalline Si film 12, 5-15 nm thin oxidized Si film 14. A second-layer polycrystalline Si film 13 is deposited by a known CVD method, as shown in FIG.
If the structure is as shown in b), how much charge will be generated between the -th layer polycrystalline Si film 12 and the second layer polycrystalline Si film 13? # Becomes a multiplication capacitor. Since such capacitors are insulated from the surroundings by a shell-shaped insulating film, leakage current between capacitors does not occur even when formed at high density, and large-scale D
It is effective as a storage charge storage capacitor for RAM.
［発明の効果〕
本発明によれば、ストッパとなる膜を設けなくても、ア
スペクト比の大きなパターン底部の絶縁膜のみを選択的
にエツチングし、それ以外の絶縁膜はエツチングされな
いので、工程の簡略化が可能となる。[Effects of the Invention] According to the present invention, only the insulating film at the bottom of the pattern with a large aspect ratio is selectively etched without providing a film to serve as a stopper, and the other insulating films are not etched. Simplification becomes possible.
また１本発明は、アスペクト比の大きいところに対して
有効であるので、今後、寸法が微細化し、溝や孔部のア
スペクト比が増大すると思われる将来のＶＬＳＩの製造
方法として有効である。Furthermore, since the present invention is effective for areas with large aspect ratios, it is effective as a method for manufacturing VLSIs in the future, where dimensions are expected to become finer and the aspect ratios of grooves and holes will increase.
第１図および第３図乃至第５図は１本発明の実施例の加
工工程を示す断面図、第２図は従来技術の加工工程を示
す断面図である。
１・・・半導体基板、２・・・酸化Ｓｉ膜、３・・・Ｃ
Ｈ系堆積膜、４・・・窒化Ｓｉ膜、５・・・ホトレジス
ト。
（α）
ＶＪ ｌ 図
（２）
拓
挙
回
（２）
χ
（（１＞FIG. 1 and FIGS. 3 to 5 are cross-sectional views showing the processing steps of an embodiment of the present invention, and FIG. 2 is a cross-sectional view showing the processing steps of the prior art. 1... Semiconductor substrate, 2... Si oxide film, 3... C
H-based deposited film, 4... Si nitride film, 5... Photoresist. (α) VJ l Figure (2) Takukyo times (2) χ ((1>
Claims (1)
絶縁膜を形成する工程と、被膜堆積を伴うエッチングに
より溝あるいは孔の底の絶縁膜のみを選択的にエッチン
グ方法を有することを特徴とする半導体装置の製造方法
。 ２、特許請求の範囲第１項記載の方法において、エッチ
ングガスとしてＣＨ＿２Ｆ＿２、Ｃ＿２Ｈ＿２Ｆ＿４、
ＣＦ＿４＋Ｈ＿２等のＨを含有するフッ化炭素ガスを用
いることを特徴とする半導体装置の製造方法。[Claims] 1. Forming a groove or hole on a semiconductor substrate;
1. A method of manufacturing a semiconductor device, comprising a step of forming an insulating film, and a method of selectively etching only the insulating film at the bottom of a trench or hole by etching accompanied by film deposition. 2. In the method according to claim 1, CH_2F_2, C_2H_2F_4,
A method for manufacturing a semiconductor device, characterized in that a fluorocarbon gas containing H, such as CF_4+H_2, is used.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1292346A JPH03154337A (en) | 1989-11-13 | 1989-11-13 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1292346A JPH03154337A (en) | 1989-11-13 | 1989-11-13 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03154337A true JPH03154337A (en) | 1991-07-02 |
Family
ID=17780613
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1292346A Pending JPH03154337A (en) | 1989-11-13 | 1989-11-13 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03154337A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111816559A (en) * | 2014-06-18 | 2020-10-23 | 乔治洛德方法研究和开发液化空气有限公司 | Chemistry for TSV/MEMS/power device etching |
-
1989
- 1989-11-13 JP JP1292346A patent/JPH03154337A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111816559A (en) * | 2014-06-18 | 2020-10-23 | 乔治洛德方法研究和开发液化空气有限公司 | Chemistry for TSV/MEMS/power device etching |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100801771B1 (en) | Method of reducing rie lag for deep trench silicon etching | |
| US5838055A (en) | Trench sidewall patterned by vapor phase etching | |
| US5876879A (en) | Oxide layer patterned by vapor phase etching | |
| US6074951A (en) | Vapor phase etching of oxide masked by resist or masking material | |
| JPS5928983B2 (en) | Method of forming buried insulation isolation region | |
| JP2009076661A (en) | Method for manufacturing semiconductor device | |
| JPS6365625A (en) | Etching | |
| JP2001068462A (en) | Plasma etching method using selective polymer deposition md method of forming contact holes using the same | |
| JPH04127433A (en) | Formation of semiconductor element isolation region | |
| JPH05121379A (en) | Method of manufacturing semiconductor device | |
| JPH11186225A (en) | Formation of tapered contact hole, formation of tapered polysilicon plug and taepred polysilicon plug | |
| JP2720785B2 (en) | Method for manufacturing semiconductor device | |
| EP0050972B1 (en) | Method of manufacturing a semiconductor device with an interconnection electrode layer | |
| US6548345B2 (en) | Method of fabricating trench for SOI merged logic DRAM | |
| JPS6038832A (en) | Semiconductor device and manufacture thereof | |
| US6291353B1 (en) | Lateral patterning | |
| JPH03154337A (en) | Manufacture of semiconductor device | |
| US6673695B1 (en) | STI scheme to prevent fox recess during pre-CMP HF dip | |
| US6107206A (en) | Method for etching shallow trenches in a semiconductor body | |
| JP2002033381A (en) | Formation method of element isolation insulating film and manufacturing method of semiconductor device | |
| JPH11243080A (en) | Etching method of semiconductor substrate | |
| CN105244309B (en) | Inhibit the method for fleet plough groove isolation structure depth load effect | |
| JPH0661190A (en) | Dry etching method | |
| JPH0353521A (en) | Manufacture of semiconductor device | |
| JPH0422021B2 (en) |