JPH0314907B2 - - Google Patents

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Publication number
JPH0314907B2
JPH0314907B2 JP56123278A JP12327881A JPH0314907B2 JP H0314907 B2 JPH0314907 B2 JP H0314907B2 JP 56123278 A JP56123278 A JP 56123278A JP 12327881 A JP12327881 A JP 12327881A JP H0314907 B2 JPH0314907 B2 JP H0314907B2
Authority
JP
Japan
Prior art keywords
substrate electrode
sputtering
electrode
substrate
magnetic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56123278A
Other languages
Japanese (ja)
Other versions
JPS5825475A (en
Inventor
Nobuyuki Hayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP12327881A priority Critical patent/JPS5825475A/en
Publication of JPS5825475A publication Critical patent/JPS5825475A/en
Publication of JPH0314907B2 publication Critical patent/JPH0314907B2/ja
Granted legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/34Gas-filled discharge tubes operating with cathodic sputtering
    • H01J37/3402Gas-filled discharge tubes operating with cathodic sputtering using supplementary magnetic fields
    • H01J37/3405Magnetron sputtering
    • H01J37/3408Planar magnetron sputtering

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Physical Vapour Deposition (AREA)

Description

【発明の詳細な説明】 本発明は基板上に物質を付着するスパツタ装置
特に絶縁物及び磁性体のスパツタを主目的とする
逆スパツタ機構及びバイアススパツタ機構を有す
るスパツタ装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sputtering apparatus for depositing a substance onto a substrate, particularly to a sputtering apparatus having a reverse sputtering mechanism and a bias sputtering mechanism, the main purpose of which is sputtering of insulating and magnetic materials.

スパツタ装置は、半導体の成膜プロセスにはか
かせない重要な役割をはたす様になつた。特に絶
縁物に代表される高融点材料は蒸着や気相成長
(Chemical Vapor Deposition)等のプロセスに
よつて得られるものより優れた特性のものを基板
材上に付着させることができる。又、半導体の成
膜プロセスではないが、磁性体のスパツタにもそ
の特性や膜の再現性が良好な点で、広く利用され
ている。
Sputtering equipment has come to play an essential role in the semiconductor film forming process. In particular, high melting point materials such as insulators can be deposited on substrates with properties superior to those obtained by processes such as vapor deposition and chemical vapor deposition. Furthermore, although it is not a semiconductor film forming process, it is widely used for sputtering magnetic materials because of its good characteristics and film reproducibility.

さらに、当技術分野では公知の如く、逆スパツ
タ機構の導入により、膜を基板材に付着させる前
に、基板電極に高圧電力を印加し、基板材の表面
をイオン衝撃によりクリーニングする、いわゆる
逆スパツタを行うことによつて、その後に付着さ
せる膜との付着強度を増すことができる。又、通
常のスパツタと同時に逆スパツタを重畳するバイ
アススパツタ法は、膜の形成中にリスパツタリン
グ現象を積極的に利用して、スパツタした薄膜の
プレーナ化を計る手段として、あるいは、既に基
板材上に形成された膜の段差の部分への絶縁物の
回り込みをうながす手段として、さらには特に、
磁性体のスパツタで膜の形成中に取り込まれ磁気
特性劣化のもとになりやすい、酸素、水素あるい
は水酸基等の除去を行うための手法として知られ
ている。このバイアススパツタ法は、絶縁物をス
パツタすることを主目的とするスパツタ装置では
高周波電圧を、導電物質をスパツタする装置では
直流又は高周波電圧を基板電極に加えることによ
つて実現される。ここで、リスパツタリング現象
とは、基板電極に発生する負の電圧により、形成
中の薄膜に対し、正イオン衝撃を行い、これによ
る再放出現象を行わせることを言う。
Furthermore, as is known in the art, by introducing a reverse sputtering mechanism, a so-called reverse sputtering mechanism is introduced, in which high voltage power is applied to the substrate electrode and the surface of the substrate material is cleaned by ion bombardment before the film is attached to the substrate material. By performing this, the adhesion strength with the film to be attached afterwards can be increased. In addition, the bias sputtering method, in which reverse sputtering is superimposed at the same time as normal sputtering, actively utilizes the resputtering phenomenon during film formation to planarize the sputtered thin film, or it has already been used as a method to planarize the sputtered thin film. In particular, as a means to encourage the insulating material to wrap around the stepped portion of the film formed on the plate material,
It is known as a method for removing oxygen, hydrogen, hydroxyl groups, etc. that are likely to be taken in during film formation by magnetic material sputtering and cause deterioration of magnetic properties. This bias sputtering method is realized by applying a high frequency voltage to a substrate electrode in a sputtering device whose main purpose is to sputter an insulating material, and by applying a direct current or high frequency voltage to a substrate electrode in a device sputtering a conductive material. Here, the resputtering phenomenon refers to a positive ion bombardment applied to the thin film being formed by a negative voltage generated at the substrate electrode, thereby causing a re-emission phenomenon.

以上述べたバイアススパツタ法を実現する例と
して、1971年9月発行IBM Technical
Disclosure Bulletin第14巻4号第1032頁に記載
されたスパツタ装置が知られており絶縁薄膜のプ
レーナ化に使用されて来た。しかしながら、この
方法は一つの高周波電圧を基板電極及びターゲツ
ト電極に5つの可変リアクタンスを介して印加す
る必要があるため、非常に複雑である。しかもこ
れには熟練した技術者による取扱が必要であり、
結局、大規模な半導体素子等の生産プロセスには
不向きであつた。又、他の公知のバイアススパツ
タ法を実現する例として、IBM Journal of
Research and Development 1970年、第14巻2
号、第172乃至175頁に記載されたJ.S.Logan氏に
よる論文「Control of RF Sputtered Film
Properties through Substrate Tuning」に示さ
れた同調陽極システムがある。この装置はチヤン
バとは絶縁された基板電極と基準電位部(普通接
地部)間にインダクタンスLとキヤパシタンスC
による共振回路が設けてあり、この共振回路の調
整で、基板電極を通る高周波電流を、従つて基板
からのリスパツタ量を制御することができる。し
かし、基板電極を流れる高周波電流に制限がある
ためリスパツタ量は限定され薄膜のプレーナ化ま
では不可能であつた。又、高流高圧電源によるス
パツタ装置には適用不可能であつた。
As an example of realizing the bias sputtering method described above, the IBM Technical
The sputtering apparatus described in Disclosure Bulletin Vol. 14, No. 4, p. 1032 is known and has been used to planarize insulating thin films. However, this method is very complicated because it requires applying one high frequency voltage to the substrate electrode and the target electrode through five variable reactances. Moreover, this requires handling by a skilled technician.
In the end, it was not suitable for large-scale production processes such as semiconductor devices. Also, as an example of realizing another known bias sputtering method, see the IBM Journal of
Research and Development 1970, Volume 14 2
JSLogan's paper “Control of RF Sputtered Film” published in No. 172-175.
There is a tuned anode system shown in ``Properties through Substrate Tuning''. This device has an inductance L and a capacitance C between the substrate electrode, which is insulated from the chamber, and the reference potential section (ordinary ground section).
A resonant circuit is provided, and by adjusting this resonant circuit, it is possible to control the high frequency current passing through the substrate electrode and, therefore, the amount of respatter from the substrate. However, since there is a limit to the high frequency current flowing through the substrate electrode, the amount of resputtering is limited, and it has been impossible to planarize the thin film. Further, it was not applicable to a sputtering device using a high-current, high-voltage power source.

さらに、バイアススパツタ法を実現する、他の
公知例として、高周波電源及び直流高圧電源のい
ずれにも適用できる、二電源システムがある。こ
れは、ターゲツト電極と基板電極に、それぞれ独
立した2個の高周波又は直流の高圧電源を接続し
一方の電源で膜形成用のスパツタ現象を、他の電
源でリスパツタ現象をおこさせるものである。し
かしながら、このシステムには二つの高圧電源を
必要とするため、装置全体が高価になり、又、そ
れぞれの電源が相手側電源の負荷となるため電源
自体に負担がかかり、回路的な工夫が必要であつ
た。
Further, as another known example of realizing the bias sputter method, there is a dual power supply system that can be applied to both a high frequency power supply and a DC high voltage power supply. In this method, two independent high frequency or direct current high voltage power supplies are connected to the target electrode and the substrate electrode, and one power source causes the sputtering phenomenon for film formation, and the other power source causes the resputtering phenomenon. However, since this system requires two high-voltage power supplies, the entire device is expensive, and each power supply acts as a load on the other power supply, placing a burden on the power supply itself, requiring circuit improvements. It was hot.

一方、磁性体のスパツタでは基板材上に付着し
た磁性体薄膜に、磁気異方性を付与するため、外
部より磁界を印加する必要がある。この外部から
の磁界方向は、スパツタ装置にプラズマ収束用と
している付属している永久磁石(又は、プラズマ
収束用コイル)の磁界方向と必ずしも一致するも
のではなく、従つて、この磁気異方性を付与する
ための外部磁界はプラズマ収束を低減させる原因
となつていた。
On the other hand, in the case of sputtering a magnetic material, it is necessary to apply a magnetic field from the outside in order to impart magnetic anisotropy to a magnetic thin film deposited on a substrate material. The direction of this external magnetic field does not necessarily match the direction of the magnetic field of the permanent magnet (or plasma focusing coil) attached to the sputtering device for plasma focusing, and therefore this magnetic anisotropy is The external magnetic field applied was a cause of reduced plasma convergence.

本発明の目的は、前記従来の欠点を解決し、述
スパツタ法、バイアススパツタ法の効果を高め、
さらに磁性体に磁気異方性を付与することの可能
なスパツタ装置を提供することである。本願発明
のスパツタ装置は、内部が減圧状態を保持しうる
チヤンバと、前記チヤンバ内のターゲツト電極お
よび基板電極と、これらの電極間にプラズマをつ
くる高圧電源とを含むスパッタ装置において、前
記基板電極を前記プラズマに対し負の電位にバイ
アスする手段を備え、かつ前記基板電極表面に対
して、略平行に磁束が分布するように、前記基板
電極内に永久磁石を配置したことを特徴とする。
The purpose of the present invention is to solve the above-mentioned conventional drawbacks, improve the effects of the sputtering method and bias sputtering method, and
Another object of the present invention is to provide a sputtering device capable of imparting magnetic anisotropy to a magnetic material. The sputtering apparatus of the present invention includes a chamber capable of maintaining a reduced pressure state inside, a target electrode and a substrate electrode in the chamber, and a high-voltage power supply that generates plasma between these electrodes. The present invention is characterized in that it includes means for biasing the plasma to a negative potential, and that a permanent magnet is disposed within the substrate electrode so that magnetic flux is distributed approximately parallel to the surface of the substrate electrode.

以下、本発明について、実施例を示す図面を参
照して説明する。第1図は本発明を採用した高周
波スパツタ装置を示す。この装置は先に述べた
Logan氏のバイアススパツタ法、即ち同調陽極シ
ステムに本発明を用いた実施例である。Logan氏
が発表したシステムは、基板電極と接地部間に接
続されたインダクタンスとコンデンサの直列同調
回路を含み、この回路は共振点(ゼロリアクタン
ス)を介して容量性リアクタンスから誘導性リア
クタンスまで変化し得る。更に、この回路は、基
板電極と接地部間の浮遊容量に並列に同調させる
こともできるので、基板電極と接地部間の正味の
リアクタンスはゼロから非常に大きい誘導性、又
は、容量性まで変化せしめることができる。この
システムでは前記の回路を容量性から誘導性まで
変化させることにより、基板電極とスパツタ中の
チヤンバ内部に発生するプラズマの導電性領域と
の間のインピータンスが制御され、よつて基板電
極に誘起させる電圧、及びターゲツト電圧に対す
る位相を制御することができる。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to drawings showing embodiments. FIG. 1 shows a high frequency sputtering device employing the present invention. This device was mentioned earlier
This is an example of using the present invention in Logan's bias sputtering method, ie, a tuned anode system. The system presented by Logan includes a series tuned circuit of an inductance and a capacitor connected between a substrate electrode and ground, and the circuit changes from capacitive reactance to inductive reactance through a resonance point (zero reactance). obtain. Additionally, this circuit can be tuned in parallel to the stray capacitance between the substrate electrode and ground, so the net reactance between the substrate electrode and ground varies from zero to very large inductive or capacitive You can force it. In this system, by changing the circuit from capacitive to inductive, the impedance between the substrate electrode and the conductive region of the plasma generated inside the chamber during sputtering is controlled, thus reducing the induced voltage at the substrate electrode. The voltage applied and the phase relative to the target voltage can be controlled.

第1図に示す本発明によるスパツタ装置は低圧
チヤンバ1を含み、それは基準電位2に、即ちこ
の場合接地電位に接続されている。チヤンバは金
属台板3を含み、チヤンバ内が真空に保たれるよ
う気密構造となつている。チヤンバ1は例えばス
テンレス又はアルミニウム合金で作られている。
アルゴン等の適当なガスが入口(図示せず)から
導入され、真空ポンプ及び圧力調整器(図示せ
ず)によつて低圧に保たれ、チヤンバ1内にター
ゲツト電極4が配置され、その上にスパツタされ
る材料、例えば、絶縁物としてSiO2、Al2O3、磁
性体としてNiFe合金等のターゲツト5が取付け
られている。ターゲツト電極4を取巻くように、
それと電気的に絶縁され基準電位に接続されたチ
ヤンバ1と同電位の導電性極間シールド6が設け
られている。ターゲツト電極4及びターゲツト5
に近接対抗して、基板電極7と、この基板電極7
を取り囲むように基板シールド8が設けられ、基
板電極7の上には、試料となる基板材9(例え
ば、フエライト、セラミツク、Siウエフアー等)
が配置される。基板電極7は絶縁支持部材10
に、ターゲツト電極4は絶縁支持部材11にそれ
ぞれ取付けられている。ターゲツト電極4及び基
板電極7には、それぞれ冷却水パイプ12及び1
3を通して冷却水が盾環し、プラズマ放電によ
る、ターゲツト電極4、ターゲツト5及び基板電
極7更には基板材9の温度上昇を防ぐようになつ
ている。
The sputtering device according to the invention shown in FIG. 1 includes a low-pressure chamber 1, which is connected to a reference potential 2, ie in this case to ground potential. The chamber includes a metal base plate 3 and has an airtight structure so that the inside of the chamber is kept in a vacuum. The chamber 1 is made of stainless steel or aluminum alloy, for example.
A suitable gas, such as argon, is introduced through an inlet (not shown) and maintained at low pressure by a vacuum pump and pressure regulator (not shown), and a target electrode 4 is placed within the chamber 1, above which the target electrode 4 is placed. A target 5 of material to be sputtered, for example, SiO 2 or Al 2 O 3 as an insulator and NiFe alloy as a magnetic material, is attached. As if surrounding the target electrode 4,
A conductive interelectrode shield 6 having the same potential as the chamber 1 is provided, which is electrically insulated from the chamber 1 and connected to a reference potential. Target electrode 4 and target 5
Closely opposing the substrate electrode 7 and the substrate electrode 7
A substrate shield 8 is provided to surround the substrate electrode 7, and a substrate material 9 to be a sample (for example, ferrite, ceramic, Si wafer, etc.) is placed on the substrate electrode 7.
is placed. The substrate electrode 7 is an insulating support member 10
In addition, the target electrodes 4 are each attached to an insulating support member 11. Cooling water pipes 12 and 1 are connected to the target electrode 4 and the substrate electrode 7, respectively.
Cooling water circulates through the target electrode 3 to prevent the temperature of the target electrode 4, the target 5, the substrate electrode 7, and the substrate material 9 from rising due to plasma discharge.

基準電位点2即ち接地点と、ターゲツト電極4
との間に高周波(例えば、13.56メガヘルツ)発
生器14がマツチングボツクス15を直列に介し
て接続されている。マツチングボツクス15はイ
ンダクタンス及びコンデンサから成る回路網で
(詳細は図示せず)そのインピーダンスが可変で
きるようになつており、スパツタ作業中の高周波
発生器14からの電力をターゲツト電極4に効率
よく伝送する役割をもつ。基板電極7は高周波イ
ンダクタンス16及び可変コンデンサ17が直列
に接続された基板電極同調回路18を通して接地
点2に接続されている。基板電極同調回路18は
スパツタ作業中の基板電極7の電位を制御する。
即ち基板電極7と接地点2間の可変高周波インピ
ーダンスは、それを通して流れる高周波電流によ
り高周波電位を発生するが、これは結果として、
ターゲツト5から飛来し、基板材9の表面に付着
した薄膜に負の直流バイアス電位を誘起する。従
つて、基板材9の表面に付着した膜に対して、正
イオン衝撃による再放出現象が発生する。
A reference potential point 2 or ground point and a target electrode 4
A high frequency (for example, 13.56 MHz) generator 14 is connected in series between the two and a matching box 15. The matching box 15 is a circuit network consisting of an inductance and a capacitor (details not shown) whose impedance can be varied, and efficiently transmits power from the high frequency generator 14 to the target electrode 4 during sputtering work. It has a role to play. The substrate electrode 7 is connected to the ground point 2 through a substrate electrode tuning circuit 18 in which a high frequency inductance 16 and a variable capacitor 17 are connected in series. The substrate electrode tuning circuit 18 controls the potential of the substrate electrode 7 during the sputtering operation.
That is, the variable high-frequency impedance between the substrate electrode 7 and the ground point 2 generates a high-frequency potential due to the high-frequency current flowing through it, which results in
It flies from the target 5 and induces a negative DC bias potential on the thin film attached to the surface of the substrate material 9. Therefore, a re-emission phenomenon occurs on the film attached to the surface of the substrate material 9 due to positive ion bombardment.

上に記載したことは薄膜形成工程を含む技術に
通じた業者にとつて周知である。しかし既に述べ
たように、従来の装置では、リスパツタの量は限
定され、実用に供しないものであつた。これは、
基板電極を通る充分な高周波電流が得られる前に
システムが不安定になるからである。この不安定
点では、チヤンバ側壁近辺のプラズマ濃度が増加
し、それに応じてプラズマから側壁へのインピー
ダンスが減ずる。これは高周波電流のチヤンバ側
壁への転換を意味し、従つて基板電極に流入する
高周波電流が減ずる。
What has been described above is well known to those skilled in the art involving thin film formation processes. However, as already mentioned, the amount of respatter produced by conventional devices is limited and is not practical. this is,
This is because the system becomes unstable before sufficient high frequency current is obtained through the substrate electrode. At this point of instability, the plasma concentration near the chamber sidewall increases and the impedance from the plasma to the sidewall decreases accordingly. This means that the high frequency current is diverted to the chamber sidewalls, thus reducing the high frequency current flowing into the substrate electrode.

本発明によるスパツタ装置では、基板電極7が
中心部永久磁石20と外周部永久磁石19及び高
透磁率材料21(例えば、パーマロイ)とで磁気
回路を形成し、中心部永久磁石20のN極(又は
S極)から外周部永久磁石19のS極(又はN
極)へ向けて、放射状に磁束23が分布する。中
心部永久磁石20と外周部永久磁石19は非磁性
金属(例えば、銅、アルミニウム)で作られた基
板台24及び基板電極枠25とで固定されてお
り、かつチヤンバ内が真空に保たれるよう気密構
造となつている。基板台24と基板電極枠25の
内部22は、冷却水パイプ13を通つて来た冷却
水が盾環している。
In the sputtering apparatus according to the present invention, the substrate electrode 7 forms a magnetic circuit with the center permanent magnet 20, the outer peripheral permanent magnet 19, and the high magnetic permeability material 21 (for example, permalloy), and the N pole of the center permanent magnet 20 ( or S pole) to the S pole (or N
The magnetic flux 23 is distributed radially toward the pole. The center permanent magnet 20 and the outer peripheral permanent magnet 19 are fixed with a substrate stand 24 and a substrate electrode frame 25 made of non-magnetic metal (e.g., copper, aluminum), and the inside of the chamber is kept in a vacuum. It has an airtight structure. The interior 22 of the substrate stand 24 and the substrate electrode frame 25 is surrounded by cooling water that has passed through the cooling water pipe 13.

この様な構成を取ることによつて、基板電極7
とターゲツト電極4の間に発生するプラズマは磁
束23によつて、基板電極7の表面近傍のみに閉
じ込められるため、基板電極7に誘起される負の
バイアス電位を高めてもシステムが不安定になら
ず、かつ基板材9の近傍に高濃度の正イオン及び
電子が分布するため、基板材9に形成中の薄膜に
衝突する正イオン量が増加し、従つてリエミツシ
ヨン量が増加することになり、効率が大きく増大
した。
By adopting such a configuration, the substrate electrode 7
The plasma generated between the target electrode 4 and the target electrode 4 is confined only near the surface of the substrate electrode 7 by the magnetic flux 23, so even if the negative bias potential induced in the substrate electrode 7 is increased, the system will not become unstable. Moreover, since a high concentration of positive ions and electrons are distributed near the substrate material 9, the amount of positive ions colliding with the thin film being formed on the substrate material 9 increases, and therefore the amount of remission increases. Efficiency has increased significantly.

従来、本発明と類似した構造をもつ平行平板マ
グネトロンスパツタ装置が存在するが、マグネト
ロンスパツタ装置はプラズマをターゲツト電極表
面に放射状磁界で収束させ、スパツタ効率を改善
する目的のもので本発明とは全く目的を異にする
ものである。又、前記平行平板マグネトロンスパ
ツタ装置でも、本発明と同様なバイアススパツタ
法を用いて、リスパツタ効率を高めることができ
る。しかし、一般にマグネトロンスパツタを含め
たスパツタ装置はターゲツト電極と基板電極との
距離を任意に変えられる構造を有するため、前記
距離によつて大きくリスパツタ量が変化してしま
うものである。本発明ではプラズマは基板電極表
面に閉じ込められるため、この様な問題はなく、
ターゲツト電極と基板電極との距離によらず、再
現性よくバイアススパツタを行うことができる。
Conventionally, parallel plate magnetron sputtering devices exist that have a structure similar to that of the present invention, but the purpose of the magnetron sputtering device is to converge plasma onto the target electrode surface using a radial magnetic field and improve sputtering efficiency. have completely different purposes. Furthermore, in the parallel plate magnetron sputtering device, the resputtering efficiency can be improved by using the same bias sputtering method as in the present invention. However, since sputtering apparatuses including magnetron sputtering generally have a structure in which the distance between the target electrode and the substrate electrode can be arbitrarily changed, the amount of resputtering varies greatly depending on the distance. In the present invention, the plasma is confined to the surface of the substrate electrode, so there is no such problem.
Bias sputtering can be performed with good reproducibility regardless of the distance between the target electrode and the substrate electrode.

又、本発明の他の目的である、磁性体のスパツ
タにおける磁気異方性の付与に関して、第2図及
び第3図を用いて説明する。第2図は従来タイプ
の典型的スパツタ装置の断面図である。従来タイ
プのスパツタ装置では、チヤンバ1の外部に設置
された永久磁石26による磁界27によつて、プ
ラズマをターゲツト電極4と基板電極7との間に
収束させていた。この磁界27は基板電極7の表
面に垂直な磁界28と平行な磁界29に分解され
従来磁性体のスパツタでは、この平行な磁界29
を利用して形成中の薄膜磁性体に面内磁気異方性
を付与していた。しかし、かかる構造では、平行
な磁界29は、基板電極中心部と外周部では、そ
の大きさが違い、基板電極全面で磁気特性の均一
な磁性薄膜を得るのが困難であつた。又前述の様
に、ターゲツト電極4と基板電極7との距離は一
般に、任意に変えられる構造になつており、この
距離によつて、基板電極表面の平行な磁界29は
大きく変化し、再現性がなかつた。又、この問題
を解決するため、更に外部から永久磁石又は電磁
石等の手段により基板電極表面と平行な磁界を印
加する方法も取られていた。しかし、この方法で
は、プラズマ収束用磁界27の分布が乱され、均
一な磁気特性の磁性薄膜を得るどころか、スパツ
タ効率さえも大きく低下してしまうものである。
又、磁気特性を改善するためのバイアススパツタ
法を適用しても均一な特性を得るのは困難であつ
た。
Further, another object of the present invention, which is to impart magnetic anisotropy to sputters of magnetic material, will be explained with reference to FIGS. 2 and 3. FIG. 2 is a cross-sectional view of a typical sputtering device of the prior art type. In the conventional sputtering apparatus, plasma is focused between the target electrode 4 and the substrate electrode 7 by a magnetic field 27 generated by a permanent magnet 26 installed outside the chamber 1. This magnetic field 27 is decomposed into a magnetic field 28 perpendicular to the surface of the substrate electrode 7 and a parallel magnetic field 29. In the conventional magnetic sputter, this parallel magnetic field 29
was used to impart in-plane magnetic anisotropy to the thin film magnetic material being formed. However, in such a structure, the parallel magnetic field 29 has a different magnitude between the center and the outer periphery of the substrate electrode, making it difficult to obtain a magnetic thin film with uniform magnetic properties over the entire surface of the substrate electrode. Furthermore, as mentioned above, the distance between the target electrode 4 and the substrate electrode 7 is generally configured to be arbitrarily changed, and depending on this distance, the parallel magnetic field 29 on the surface of the substrate electrode changes greatly, which improves reproducibility. I was bored. In order to solve this problem, a method has also been taken in which a magnetic field parallel to the surface of the substrate electrode is applied from the outside using means such as a permanent magnet or an electromagnet. However, in this method, the distribution of the plasma focusing magnetic field 27 is disturbed, and instead of obtaining a magnetic thin film with uniform magnetic properties, even the sputtering efficiency is significantly reduced.
Further, even if a bias sputtering method for improving magnetic properties is applied, it is difficult to obtain uniform properties.

本発明では、第3図に示す基板電極7内の磁石
配置、即ち外周部永久磁石19及び中心部永久磁
石20により、基板電極7の表面の中心部から外
周部へ放射状の磁束23はほぼ均一に基板材9に
加えられるため、前述の磁性体のスパツタ(バイ
アススパツタ法を含む)では、形成中の磁性薄膜
に均一な磁気異方性を与えることが可能となつ
た。
In the present invention, due to the magnet arrangement in the substrate electrode 7 shown in FIG. 3, that is, the outer peripheral permanent magnet 19 and the center permanent magnet 20, the radial magnetic flux 23 from the center to the outer peripheral portion of the surface of the substrate electrode 7 is almost uniform. Since the magnetic material is added to the substrate material 9 at the same time, it has become possible to impart uniform magnetic anisotropy to the magnetic thin film being formed in the above-described magnetic material sputtering (including the bias sputtering method).

以上述べた、バイアススパツタ法は同調陽極シ
ステムに限らず他の公知のバイアス印加法を用い
ても可能であることは明らかである。
It is clear that the bias sputtering method described above is possible not only by using the tuned anode system but also by using other known bias application methods.

一方、逆スパツタ法でも、基板電極とターゲツ
ト電極間に発生するプラズマは基板電極表面近傍
に収束するため、基板材表面のクリーニング効果
を大きく改善できた。
On the other hand, even in the reverse sputtering method, the plasma generated between the substrate electrode and the target electrode converges near the surface of the substrate electrode, so that the cleaning effect on the surface of the substrate material can be greatly improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明によるスパツタ装置の実施例を
示す概略的な断面図、第2図は従来タイプのスパ
ツタ装置を示す概略的な断面図、第3図は本発明
の基板電極の磁石配置と磁束分布を示す平面図で
ある。 1はチヤンバ、4はターゲツト電極、5はター
ゲツト、7は基板電極、19は外周部永久磁石、
20は中心部永久磁石である。
FIG. 1 is a schematic sectional view showing an embodiment of the sputtering device according to the present invention, FIG. 2 is a schematic sectional view showing a conventional type sputtering device, and FIG. 3 is a schematic sectional view showing the magnet arrangement of the substrate electrode of the present invention. FIG. 3 is a plan view showing magnetic flux distribution. 1 is a chamber, 4 is a target electrode, 5 is a target, 7 is a substrate electrode, 19 is an outer peripheral permanent magnet,
20 is a central permanent magnet.

Claims (1)

【特許請求の範囲】[Claims] 1 内部が減圧状態を保持しうるチヤンバと、前
記チヤンバ内のターゲツト電極および基板電極
と、これらの電極間にプラズマをつくる高圧電源
とを含むスパツタ装置において、前記基板電極を
前記プラズマに対し負の電位にバイアスする手段
を備え、かつ前記基板電極表面に対して、略平行
に磁束が分布するように、前記基板電極内に永久
磁石を配置したことを特徴とするスパツタ装置。
1. A sputtering apparatus including a chamber capable of maintaining a reduced pressure state inside, a target electrode and a substrate electrode in the chamber, and a high-voltage power source that generates plasma between these electrodes, in which the substrate electrode is placed in a negative state with respect to the plasma. What is claimed is: 1. A sputtering apparatus comprising: a means for biasing a potential; and a permanent magnet disposed within the substrate electrode so that magnetic flux is distributed approximately parallel to the surface of the substrate electrode.
JP12327881A 1981-08-05 1981-08-05 Sputtering device Granted JPS5825475A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12327881A JPS5825475A (en) 1981-08-05 1981-08-05 Sputtering device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12327881A JPS5825475A (en) 1981-08-05 1981-08-05 Sputtering device

Publications (2)

Publication Number Publication Date
JPS5825475A JPS5825475A (en) 1983-02-15
JPH0314907B2 true JPH0314907B2 (en) 1991-02-27

Family

ID=14856602

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12327881A Granted JPS5825475A (en) 1981-08-05 1981-08-05 Sputtering device

Country Status (1)

Country Link
JP (1) JPS5825475A (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59170270A (en) * 1983-03-15 1984-09-26 Toshiba Corp Apparatus for forming film
JPS60136230A (en) * 1983-12-24 1985-07-19 Ulvac Corp Device for shaping substrate surface
JPS6187868A (en) * 1984-10-05 1986-05-06 Nippon Telegr & Teleph Corp <Ntt> Method and device for forming thin film
JPS61137326A (en) * 1984-12-10 1986-06-25 Ulvac Corp Substrate surface shaping apparatus
JPS62107064A (en) * 1985-11-05 1987-05-18 Anelva Corp Bias sputtering apparatus
JPS63265493A (en) * 1987-04-23 1988-11-01 Fujitsu Ltd Multilayer ceramic board
US4812217A (en) * 1987-04-27 1989-03-14 American Telephone And Telegraph Company, At&T Bell Laboratories Method and apparatus for feeding and coating articles in a controlled atmosphere
JP2000315598A (en) * 1999-03-03 2000-11-14 Anelva Corp Plasma processing device
EP1292752A1 (en) * 2000-06-19 2003-03-19 Nippon Sheet Glass Co., Ltd. Vehicle window glass holder
US6677711B2 (en) * 2001-06-07 2004-01-13 Lam Research Corporation Plasma processor method and apparatus
JP4643387B2 (en) * 2005-08-10 2011-03-02 シャープ株式会社 Plasma processing equipment
JP4876641B2 (en) * 2006-03-09 2012-02-15 東京エレクトロン株式会社 Plasma processing equipment

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57207177A (en) * 1981-06-17 1982-12-18 Hitachi Ltd Dc sputtering device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57207177A (en) * 1981-06-17 1982-12-18 Hitachi Ltd Dc sputtering device

Also Published As

Publication number Publication date
JPS5825475A (en) 1983-02-15

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