JPH03139882A - Manufacture of semiconductor storage device - Google Patents
Manufacture of semiconductor storage deviceInfo
- Publication number
- JPH03139882A JPH03139882A JP1277049A JP27704989A JPH03139882A JP H03139882 A JPH03139882 A JP H03139882A JP 1277049 A JP1277049 A JP 1277049A JP 27704989 A JP27704989 A JP 27704989A JP H03139882 A JPH03139882 A JP H03139882A
- Authority
- JP
- Japan
- Prior art keywords
- film
- polysilicon
- polysilicon film
- melting point
- high melting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000003860 storage Methods 0.000 title claims abstract description 10
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 44
- 229920005591 polysilicon Polymers 0.000 claims abstract description 44
- 238000000034 method Methods 0.000 claims abstract description 16
- 239000003990 capacitor Substances 0.000 claims abstract description 15
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims abstract description 14
- 239000011229 interlayer Substances 0.000 claims abstract description 8
- 238000002844 melting Methods 0.000 claims abstract description 8
- 230000008018 melting Effects 0.000 claims abstract description 8
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 8
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 4
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 claims 1
- 238000000926 separation method Methods 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 abstract description 9
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 4
- 239000013078 crystal Substances 0.000 abstract description 2
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 abstract 2
- 229910019213 POCl3 Inorganic materials 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 20
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 3
- 230000014759 maintenance of location Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 2
- 210000000988 bone and bone Anatomy 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体記憶装置、特にダイナミックランダム
アクセス メモリ （ＤＲＡＭ）のメモリセルの製造方
法に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to semiconductor memory devices, particularly dynamic random
The present invention relates to a method of manufacturing a memory cell of an access memory (DRAM).
従来、この種のメモリセルについて、第２図を参照して
述べる。尚、第２図はメモリセルの断面図を示す。A conventional memory cell of this type will be described with reference to FIG. Incidentally, FIG. 2 shows a cross-sectional view of the memory cell.
即ち、図面において、２１はｐ型シリコン基板であり、
この基板２１の非能動領域上には、素子分離用のフィー
ルド酸化膜２２が形成され、能動領域上には、ゲート酸
化膜２３が形成されている。That is, in the drawing, 21 is a p-type silicon substrate,
A field oxide film 22 for element isolation is formed on the non-active region of the substrate 21, and a gate oxide film 23 is formed on the active region.
又、これらフィールド酸化膜２２上及びゲート酸化Ｈ，
２３上には、第１ポリシリコンから成るワード１２４が
個別に形成され、ゲート酸化膜２３上のワード線２４の
両側方における基板２１表面部には、ｎ゛拡散層２５ａ
、２５ｂが形成されている。Moreover, on these field oxide films 22 and gate oxide H,
Words 124 made of first polysilicon are individually formed on the gate oxide film 23, and n diffusion layers 25a are formed on the surface of the substrate 21 on both sides of the word line 24 on the gate oxide film 23.
, 25b are formed.
更に、ワード線２４を含む基板２１上には、第１層間絶
縁膜２６が堆積され、上記ワード線２４上及びワード線
２４間上における上記第１層間絶縁膜２６上には、蓄積
電極となる第２ポリシリコン層２７が形成され、この第
２ポリシリコン層２７の表面には、キャパシタ絶縁膜２
８が被着されている。そして、このキャパシタ絶縁膜２
８上には、セルプレート電極となる第３ポリシリコン層
２９が形成されている。更に、これら構成素子上には、
第２層間絶縁膜３０、ビット線となるＡＩ膜３１及びこ
の＾ｌ膜３１を保護する保護膜３２が順次形成されてい
る。又、上記第１層間絶縁膜２６には、ｎ゛拡散Ｊｉ２
５ａと第２ポリシリコン層２７とを接続する第１コンタ
クトホール３３が開孔されると共に、上記第２層間絶縁
膜３０には、ｎ゛拡散層２５ｂと＾ｌ膜３１とを接続す
る第２コンタクトホール３４が開孔されている。Further, a first interlayer insulating film 26 is deposited on the substrate 21 including the word line 24, and a storage electrode is formed on the first interlayer insulating film 26 on the word line 24 and between the word lines 24. A second polysilicon layer 27 is formed, and a capacitor insulating film 2 is formed on the surface of the second polysilicon layer 27.
8 is coated. Then, this capacitor insulating film 2
A third polysilicon layer 29 is formed on top of the third polysilicon layer 29 to serve as a cell plate electrode. Furthermore, on these components,
A second interlayer insulating film 30, an AI film 31 serving as a bit line, and a protective film 32 for protecting this ^l film 31 are formed in this order. Further, in the first interlayer insulating film 26, n゛diffused Ji2
5a and the second polysilicon layer 27, and a second contact hole 33 is formed in the second interlayer insulating film 30 to connect the n' diffusion layer 25b and the ^l film 31. A contact hole 34 is opened.
斯くして、かかるメモリセルでは、１つの記憶保持用の
キャパシタと１つの選択用ＭＯＳトランジスタから構成
されて層り、メモリの高集積化、即ちセルサイズの縮小
化に対し、記憶保持時間を保持し、α線によるソフトエ
ラーに耐性を持たせるため、選択用トランジスタ上及び
素子骨ＲＳＪＩ域上に、ストレージキャパシタを形成し
た、所謂スタック型とし、充分なキャパシタ容量を確保
していた。In this way, such a memory cell is composed of one memory retention capacitor and one selection MOS transistor, and is layered to maintain memory retention time even as memory becomes highly integrated, that is, cell size decreases. However, in order to provide resistance to soft errors caused by alpha rays, a so-called stack type was used in which a storage capacitor was formed on the selection transistor and on the element bone RSJI region to ensure sufficient capacitor capacity.
然し乍ら、上述した従来メモリセルにおいては、より高
集積度のメモリ素子を形成する場合、キャパシタ面積が
減少し、メモリ保持時間やα線の耐性に対して充分なキ
ャパシタ容量を得ることができないという問題点があっ
た。However, in the conventional memory cell described above, when forming a memory element with a higher degree of integration, the capacitor area decreases, and there is a problem that it is not possible to obtain a sufficient capacitor capacity for memory retention time and resistance to alpha rays. There was a point.
本発明の目的は、上述した問題点に鑑み、セルサイズが
縮小化しても充分なキャパシタ容量が得られる半導体記
憶装置の製造方法を提供するものである。SUMMARY OF THE INVENTION In view of the above-mentioned problems, an object of the present invention is to provide a method for manufacturing a semiconductor memory device that can obtain sufficient capacitor capacity even when the cell size is reduced.
本発明は上述の目的を達成するため、半導体基板上に形
成された選択用ＭＯＳトランジスタ及び素子骨＃領域上
に、ストレージキャパシタを積層したスタック型メモリ
セルを有する半導体記憶装置の製造方法において、上記
ＭＯＳトランジスタ上及び上記素子分離領域上に、眉間
絶縁膜を介して高融点金属シリサイド膜を形成する工程
と、上記高融点金属シリサイド膜上に、高ｆ４濃度のポ
リシリコン膜を形成する工程と、上記ポリシリコン膜を
、加熱した燐酸液でエツチングし、上記ポリシリコン膜
の表面に凹凸を形成する工程とを含むものである。In order to achieve the above-mentioned object, the present invention provides a method for manufacturing a semiconductor memory device having a stacked memory cell in which a storage capacitor is stacked on a selection MOS transistor and an element bone region formed on a semiconductor substrate. forming a high melting point metal silicide film on the MOS transistor and the element isolation region via a glabellar insulating film; forming a high f4 concentration polysilicon film on the high melting point metal silicide film; The method includes a step of etching the polysilicon film with a heated phosphoric acid solution to form irregularities on the surface of the polysilicon film.
本発明においては、高ｆ４濃度のポリシリコン膜を加熱
した燐酸液でエツチングし、ポリシリコン膜の表面に凹
凸を形成するので、ポリシリコン膜の実効的な表面積が
増大し、ストレージキャパシタのキャパシタ容量が増大
する。又、ポリシリコン膜のウェットエツチングに際し
て、高融点金属シリサイド膜がエツチングストッパーと
して作用すると共に、凹凸形成によるポリシリコン膜の
断線を防止する。In the present invention, a polysilicon film with a high F4 concentration is etched with a heated phosphoric acid solution to form irregularities on the surface of the polysilicon film, thereby increasing the effective surface area of the polysilicon film and increasing the capacitance of the storage capacitor. increases. Furthermore, during wet etching of the polysilicon film, the high melting point metal silicide film acts as an etching stopper and prevents disconnection of the polysilicon film due to the formation of irregularities.
本発明ＤＲＡＭのメモリセルの製造方法における一実施
例を第１図に基づいて説明する。尚、第１図は工程断面
図を示す。An embodiment of the method for manufacturing a DRAM memory cell according to the present invention will be described with reference to FIG. Incidentally, FIG. 1 shows a cross-sectional view of the process.
先ず、ｐ型半導体基板ｌ上に、ＬＯＣＯ３法により素子
分離を行なうためのフィールド酸化膜２を形成する。そ
の後、８００〜１０００℃で乾燥若しくは水蒸気酸化を
行なうことにより、１００〜３００人厚程度のゲート酸
化膜３を、基板１の能動領域上に形成する０次に、減圧
ＣＶＤ法等により、メモリセル形成予定令頁域上に、第
１ポリシリコン層を１０００〜３０００人厚程度デポジ
ションした後、この第１ポリシリコン層に、ｐｏｃｌｚ
をソースとする熱拡散により、燐（Ｐ）をＩＱ”ａｍ−
”程度の濃度にドーピングする。その後、通常のホトリ
ソグラフィ技術を用いて、レジスト（図示略す）をパタ
ーニングし、このパターン化されたレジストをマスクと
して、上記第１ポリシリコン層をエツチングし、フィー
ルド酸化１１！２上及びゲート酸化ｌｌｌ３上に、夫々
位置するメモリセルのワード線４を形成する（第１図ａ
）。First, a field oxide film 2 for element isolation is formed on a p-type semiconductor substrate l by the LOCO3 method. Thereafter, a gate oxide film 3 with a thickness of about 100 to 300 layers is formed on the active region of the substrate 1 by drying or steam oxidation at 800 to 1000°C. After depositing a first polysilicon layer with a thickness of about 1,000 to 3,000 layers on the planned page area, poclz is applied to the first polysilicon layer.
By thermal diffusion using the source, phosphorus (P) is
After that, a resist (not shown) is patterned using ordinary photolithography technology, and using this patterned resist as a mask, the first polysilicon layer is etched and field oxidized. 11!2 and on the gate oxide lll3, the word lines 4 of the memory cells located respectively are formed (see FIG. 1a).
).
次いで、上記ワード線４及びフィールド酸化膜２をマス
クとして、砒素（Ａｓ）をイオン注入し、更にアニール
処理することで、基ｖｉ１表面部に、濃度がＩＱ”ａｍ
−３程度のｎ９拡散層５ａ、５ｂを形成する。その後、
常圧ＣＶＤ法等により、全面に、第１の層間絶縁膜であ
るシリコン酸化膜６を、１０００〜３０００人厚程度堆
積し、通常のホトリソグラフィ技術により、パターン化
したレジスト（図示略す）をマスクとするドライエツチ
ング技術により、上記シリコン酸化１Ｉ１６のｎ゛拡散
層５ａの所定部分上を開孔し、コンタクトホール７を形
成する（第１図ｂ）。Next, using the word line 4 and the field oxide film 2 as masks, arsenic (As) is ion-implanted and further annealed so that the concentration is IQ"am on the surface of the base vi1.
N9 diffusion layers 5a and 5b of about -3 are formed. after that,
A silicon oxide film 6, which is a first interlayer insulating film, is deposited to a thickness of about 1,000 to 3,000 layers over the entire surface by atmospheric pressure CVD, etc., and then a patterned resist (not shown) is masked by ordinary photolithography. Using a dry etching technique, a contact hole 7 is formed on a predetermined portion of the silicon oxide 1I16 diffusion layer 5a (FIG. 1b).
続いて、全面に、スパッタ法又は減圧ＣＶＤ法により、
メモリセルの蓄積ノードとなる高融点金属シリサイド膜
、例えばＷＳｉｘ （Ｘ ＝２．０〜３．０）膜８を１
０００〜２０００人厚程度形成する。その後、上記ＷＳ
ｉｘ膜８上に、減圧ＣＶＤ法により、第２ポリシリコン
１ｌ１９を５００〜１５００人厚形成し、この第２ポリ
シリコン膜９に、ＰＯＣＺ３をソースとする熱拡散によ
り、燐をＩＱ”ＣＩＡ−’程度の濃度にドーピングする
（第１図Ｃ）。Subsequently, the entire surface is coated by sputtering or low pressure CVD.
A high melting point metal silicide film, for example, a WSix (X = 2.0 to 3.0) film 8, which becomes a storage node of a memory cell, is
Form approximately 000 to 2000 people thick. After that, the above WS
A second polysilicon film 1l19 with a thickness of 500 to 1,500 layers is formed on the ix film 8 by low pressure CVD, and phosphorus is added to the second polysilicon film 9 by thermal diffusion using POCZ3 as a source. Doping is carried out to a certain concentration (FIG. 1C).
次いで、上記第２ポリシリコン膜９を、１７０℃程度に
加熱した燐酸液に約１０〜２０分間浸漬する。これによ
り、第２ポリシリコン膜９のグレイン境界、即ち結晶粒
界でのポリシリコンが特にエツチングされ、第２ポリシ
リコン膜９の表面に凹凸が形成される。このとき、充分
な凹凸を形成するためには、第２ポリシリコン膜９の燐
濃度を少な（とも６ ｘｌＯｚｏ、、−、以上必要とす
る。又、燐酸液による浸漬時間を長くとる程凹凸の差は
大きくなる。そして、この場合、例えば凹部のポリシリ
コンが全てエツチング除去されても下地の−Ｓｉｘ膜８
がエツチングのストッパーとして作用し、而も−Ｓｉｘ
膜８により第２ポリシリコンｌ！９は結線され、凹凸に
よる断線は生じない、続いて、通常のホトリソグラフィ
技術によりバターニングしたレジスト（図示略す）をマ
スクとするドライエツチング技術を用いて、第２ポリシ
リコン膜９及びＷＳｉｘ膜８をパターニングし、ワード
線４上及びワード線４間上に位置するメモリセルの蓄積
電極を形成する。その後、減圧ＣＶＤ法等により、全面
に、キャパシタ絶縁膜となる５ｉＪ４膜１０を５０〜１
００人厚程度形成し、更に、８００〜９００℃の水蒸気
雰囲気中で、約３０〜６０分間上記Ｓｉ、Ｎ４膜１０を
酸化し、ＳｉＪ、膜１０の耐圧を向上させるための酸化
膜１１をｌＯ〜２０人厚形成する。その後、上記酸化膜
ｌｌ上に、減圧ＣＶＤ法により、第３ポリシリコン膜１
２を２０００〜３０００人厚形成し、この第３ポリシリ
コン膜１２に、ｐｏｃＢをソースとする熱拡散により、
燐を４×１０ｔ０〜６Ｘ１０”ａｍ−”の濃度にドーピ
ングする（第１図ｄ）
しかる後、ホトリソグラフィ技術及びドライエツチング
技術を用いて、上記第３ポリシリコン膜１２をバターニ
ングし、上記蓄積電極を被うセルプレート電極とし、Ｄ
ＲＡＭメモリセルのキャパシタが形成される。しかる後
、常圧ＣＶＤ法により、全面に、ＢＰＳＧ等から成る第
２の眉間絶縁膜１３を６０００〜８０００人厚程度堆積
した後、９００℃程度の熱処理を施すことにより、上記
第２の眉間絶縁膜１３を平滑化する。そして、ｎ゛拡散
層５ｂの部分上の第２の眉間絶縁膜１３をエツチング除
去し、コンタクトホール１４を開孔する。その後、スパ
ッタ法により、全面に、＾！膜１５を約１００００ 人
厚堆積し、これをパターニングしてビット線とする。更
に、このビット線の表面に、保護膜（図示略す）を被着
し、ＤＲＡＭメモリセルが完成する（第１図ｅ）ｅ
〔発明の効果〕
以上説明したように本発明によれば、ポリシリコン膜の
表面に凹凸を形成するので、ポリシリコン膜の実効的な
表面積が増大し、ストレージキャパシタの容量が増大す
る。従って、より高集積度なメモリセルが得られる等の
効果により上述した課題を解決し得る。Next, the second polysilicon film 9 is immersed in a phosphoric acid solution heated to about 170° C. for about 10 to 20 minutes. As a result, the polysilicon at the grain boundaries, that is, the crystal grain boundaries, of the second polysilicon film 9 is particularly etched, and irregularities are formed on the surface of the second polysilicon film 9. At this time, in order to form sufficient unevenness, the phosphorus concentration of the second polysilicon film 9 needs to be small (more than 6 x lOzo, -). Also, the longer the immersion time in the phosphoric acid solution, the more uneven the unevenness becomes. In this case, for example, even if all the polysilicon in the concave portion is etched away, the underlying −Six film 8
acts as an etching stopper, and -Six
The film 8 allows the second polysilicon l! 9 is connected, and no disconnection occurs due to unevenness. Next, the second polysilicon film 9 and the WSix film 8 are etched using a dry etching technique using a patterned resist (not shown) as a mask, which has been patterned by ordinary photolithography. is patterned to form storage electrodes of memory cells located on the word lines 4 and between the word lines 4. Thereafter, a 5iJ4 film 10, which will become a capacitor insulating film, is deposited on the entire surface using a low pressure CVD method or the like.
The Si, N4 film 10 is further oxidized for about 30 to 60 minutes in a steam atmosphere at 800 to 900°C to form an oxide film 11 to improve the withstand voltage of the SiJ film 10. ~20 people thick. Thereafter, a third polysilicon film 1 is formed on the oxide film 11 by low pressure CVD.
2 is formed to a thickness of 2,000 to 3,000 layers, and this third polysilicon film 12 is heated by thermal diffusion using pocB as a source.
The third polysilicon film 12 is doped with phosphorus to a concentration of 4x10t0 to 6x10"am-" (FIG. 1d). The third polysilicon film 12 is then buttered using photolithography and dry etching techniques to eliminate the accumulation. As a cell plate electrode covering the electrode, D
A capacitor for a RAM memory cell is formed. Thereafter, a second glabellar insulating film 13 made of BPSG or the like is deposited on the entire surface to a thickness of about 6,000 to 8,000 by atmospheric pressure CVD, and then heat-treated at about 900°C to form the second glabellar insulating film 13. The membrane 13 is smoothed. Then, the second glabellar insulating film 13 on the n' diffusion layer 5b is removed by etching, and a contact hole 14 is opened. After that, use sputtering method to coat the entire surface! A film 15 is deposited to a thickness of about 10,000 layers and patterned to form a bit line. Furthermore, a protective film (not shown) is deposited on the surface of this bit line, and the DRAM memory cell is completed (Fig. 1 e). [Effects of the Invention] As explained above, according to the present invention, Since irregularities are formed on the surface of the silicon film, the effective surface area of the polysilicon film increases, and the capacitance of the storage capacitor increases. Therefore, the above-mentioned problems can be solved with effects such as the ability to obtain memory cells with a higher degree of integration.
第１図は本発明方法の実施例における工程断面図、第２
図は従来メモリセルの断面図である。
ｌ・・・ｐ型半導体基板、２・・・フィールド酸化膜、
３・・・ゲート酸化膜、４・・・ワード線、５ａ、５ｂ
・・・ｎ゛拡散層、６・・・シリコン酸化膜、７・・・
コンタクトホール、８・・・−５ｉｘ膜、９・・・第２
ポリシリコン膜、１０・・・ＳｉＪｇ膜、１１・・・酸
化膜、１２・・・第３ポリシリコン膜。
λζ９−９月方３七０工程図
第１図
イ減〕政×８リセルの断面図
第２図Fig. 1 is a process cross-sectional view in an embodiment of the method of the present invention, Fig.
The figure is a cross-sectional view of a conventional memory cell. l...p-type semiconductor substrate, 2... field oxide film,
3... Gate oxide film, 4... Word line, 5a, 5b
...n゛diffusion layer, 6...silicon oxide film, 7...
Contact hole, 8...-5ix film, 9... second
Polysilicon film, 10... SiJg film, 11... Oxide film, 12... Third polysilicon film. λζ9-September 370 Process diagram Figure 1 A reduction] Sectional diagram of x8 resel Figure 2
Claims (1)
び素子分離領域上に、ストレージキャパシタを積層した
スタック型メモリセルを有する半導体記憶装置の製造方
法において、 上記ＭＯＳトランジスタ上及び上記素子分離領域上に、
層間絶縁膜を介して高融点金属シリサイド膜を形成する
工程と、 上記高融点金属シリサイド膜上に、高燐濃度のポリシリ
コン膜を形成する工程と、 上記ポリシリコン膜を、加熱した燐酸液でエッチングし
、上記ポリシリコン膜の表面に凹凸を形成する工程とを
含むことを特徴とする半導体記憶装置の製造方法。[Scope of Claims] A method for manufacturing a semiconductor memory device having a stacked memory cell in which a storage capacitor is stacked on a selection MOS transistor and an element isolation region formed on a semiconductor substrate, comprising: on the MOS transistor and on the element; On the separation area,
forming a high melting point metal silicide film via an interlayer insulating film; forming a polysilicon film with a high phosphorous concentration on the high melting point metal silicide film; and forming the polysilicon film with a heated phosphoric acid solution. A method for manufacturing a semiconductor memory device, comprising the step of etching to form irregularities on the surface of the polysilicon film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1277049A JPH03139882A (en) | 1989-10-26 | 1989-10-26 | Manufacture of semiconductor storage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1277049A JPH03139882A (en) | 1989-10-26 | 1989-10-26 | Manufacture of semiconductor storage device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03139882A true JPH03139882A (en) | 1991-06-14 |
Family
ID=17578075
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1277049A Pending JPH03139882A (en) | 1989-10-26 | 1989-10-26 | Manufacture of semiconductor storage device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03139882A (en) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06163853A (en) * | 1992-02-28 | 1994-06-10 | Samsung Electron Co Ltd | Manufacture of capacitor of semiconductor device |
| JPH06244378A (en) * | 1993-02-03 | 1994-09-02 | Ind Technol Res Inst | Process for manufacturing high-capacity storage node |
| US5372962A (en) * | 1992-01-31 | 1994-12-13 | Nec Corporation | Method of making a semiconductor integrated circuit device having a capacitor with a porous surface of an electrode |
| JPH0738062A (en) * | 1993-07-22 | 1995-02-07 | Nec Corp | Manufacture of semiconductor device |
| JPH0774320A (en) * | 1993-08-31 | 1995-03-17 | Nec Corp | Manufacture of semiconductor device |
| US5445986A (en) * | 1993-09-03 | 1995-08-29 | Nec Corporation | Method of forming a roughened surface capacitor with two etching steps |
| US5597760A (en) * | 1995-01-25 | 1997-01-28 | Nec Corporation | Process of fabricating semiconductor device having capacitor increased in capacitance by roughening surface of accumulating electrode |
| US5656529A (en) * | 1995-05-11 | 1997-08-12 | Nec Corporation | Method for manufacturing highly-integrated capacitor |
| JPH09232543A (en) * | 1996-02-28 | 1997-09-05 | Nec Corp | Manufacture of semiconductor device |
| US5700710A (en) * | 1994-11-11 | 1997-12-23 | Nec Corporation | Process of fabricating capacitor having waved rough surface of accumulating electrode |
| US5811333A (en) * | 1995-01-13 | 1998-09-22 | Nec Corporation | Method of roughening a polysilicon layer of a random crystal structure included in a semiconductor device |
| KR100227174B1 (en) * | 1996-02-21 | 1999-10-15 | 다니구찌 이찌로오, 기타오카 다카시 | Semiconductor memory device and fabricating method thereof |
| DE112011100144T5 (en) | 2010-11-24 | 2012-09-20 | France Bed Co., Ltd | Wheelchair equipped with brake |
-
1989
- 1989-10-26 JP JP1277049A patent/JPH03139882A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5372962A (en) * | 1992-01-31 | 1994-12-13 | Nec Corporation | Method of making a semiconductor integrated circuit device having a capacitor with a porous surface of an electrode |
| JPH06163853A (en) * | 1992-02-28 | 1994-06-10 | Samsung Electron Co Ltd | Manufacture of capacitor of semiconductor device |
| JPH06244378A (en) * | 1993-02-03 | 1994-09-02 | Ind Technol Res Inst | Process for manufacturing high-capacity storage node |
| JPH0738062A (en) * | 1993-07-22 | 1995-02-07 | Nec Corp | Manufacture of semiconductor device |
| JPH0774320A (en) * | 1993-08-31 | 1995-03-17 | Nec Corp | Manufacture of semiconductor device |
| US5445986A (en) * | 1993-09-03 | 1995-08-29 | Nec Corporation | Method of forming a roughened surface capacitor with two etching steps |
| US5700710A (en) * | 1994-11-11 | 1997-12-23 | Nec Corporation | Process of fabricating capacitor having waved rough surface of accumulating electrode |
| US5811333A (en) * | 1995-01-13 | 1998-09-22 | Nec Corporation | Method of roughening a polysilicon layer of a random crystal structure included in a semiconductor device |
| US5597760A (en) * | 1995-01-25 | 1997-01-28 | Nec Corporation | Process of fabricating semiconductor device having capacitor increased in capacitance by roughening surface of accumulating electrode |
| US5656529A (en) * | 1995-05-11 | 1997-08-12 | Nec Corporation | Method for manufacturing highly-integrated capacitor |
| KR100227174B1 (en) * | 1996-02-21 | 1999-10-15 | 다니구찌 이찌로오, 기타오카 다카시 | Semiconductor memory device and fabricating method thereof |
| JPH09232543A (en) * | 1996-02-28 | 1997-09-05 | Nec Corp | Manufacture of semiconductor device |
| DE112011100144T5 (en) | 2010-11-24 | 2012-09-20 | France Bed Co., Ltd | Wheelchair equipped with brake |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5330928A (en) | Method for fabricating stacked capacitors with increased capacitance in a DRAM cell | |
| JP2761685B2 (en) | Method for manufacturing semiconductor device | |
| JP3172321B2 (en) | Method for manufacturing semiconductor memory device | |
| JPH0653412A (en) | Semiconductor memory device and fabrication thereof | |
| JP2839076B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH03139882A (en) | Manufacture of semiconductor storage device | |
| JPH04274359A (en) | Dynamic random acess memory | |
| JPS5856268B2 (en) | Manufacturing method of semiconductor device | |
| JPH0279462A (en) | Semiconductor memory | |
| JPH11111857A (en) | Formation of capacity part in semiconductor device, and formation of capacity and gate parts in the semiconductor device | |
| JP3075620B2 (en) | Method for manufacturing semiconductor device | |
| JPH02129956A (en) | Manufacture of semiconductor memory device | |
| JPH01290256A (en) | Dynamic type semiconductor memory and manufacture thereof | |
| JPH0344068A (en) | Manufacture of semiconductor device | |
| JPS6138867B2 (en) | ||
| JP3317736B2 (en) | Semiconductor device and manufacturing method thereof | |
| KR970011749B1 (en) | A method for fabricating dram cells | |
| JPS62124765A (en) | Semiconductor device | |
| JPH0888330A (en) | Semiconductor device and manufacture thereof | |
| JPH05110020A (en) | Semiconductor device | |
| JP3213442B2 (en) | Semiconductor memory device and method of manufacturing the same | |
| JPH01120862A (en) | Manufacture of semiconductor memory device | |
| JPH01290255A (en) | Semiconductor memory and manufacture thereof | |
| JPH04139761A (en) | Manufacture of semiconductor memory device | |
| JPH03224264A (en) | Manufacture of semiconductor integrated circuit device |