JPH03129858A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH03129858A JPH03129858A JP26959889A JP26959889A JPH03129858A JP H03129858 A JPH03129858 A JP H03129858A JP 26959889 A JP26959889 A JP 26959889A JP 26959889 A JP26959889 A JP 26959889A JP H03129858 A JPH03129858 A JP H03129858A
- Authority
- JP
- Japan
- Prior art keywords
- base
- semiconductor chip
- integrated circuit
- cap
- recess
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 40
- 230000000903 blocking effect Effects 0.000 abstract 1
- 239000000919 ceramic Substances 0.000 description 5
- 239000005394 sealing glass Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000006060 molten glass Substances 0.000 description 1
- 229920005668 polycarbonate resin Polymers 0.000 description 1
- 239000004431 polycarbonate resin Substances 0.000 description 1
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路装置に関し、特に４セラミツク
パツケ一ジ型半導体集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a four-ceramic package type semiconductor integrated circuit device.
従来、この種の半導体集積回路装置は、図面には示さな
いが、半導体集積回路が形成された半導体チップを、セ
ラミックベースの窪みに固着し、このセラミックベース
のリードと半導体チップの入出力端子であるパッドとを
ワイヤで接続し、この半導体チップが固着されたセラミ
ックベースの窪みを塞ぐようにセラミック製のキャップ
を被せて、溶融ガラスで接着し、密封する構造となって
いた。Conventionally, this type of semiconductor integrated circuit device, although not shown in the drawings, has a semiconductor chip with a semiconductor integrated circuit formed thereon fixed in a recess of a ceramic base, and leads of the ceramic base and input/output terminals of the semiconductor chip. The structure was such that a certain pad was connected with a wire, a ceramic cap was placed to cover the recess of the ceramic base to which the semiconductor chip was fixed, and the cap was bonded with molten glass to seal it.
上述した従来の半導体集積回路装置では、封止ガラスを
高温で熱処理することにより溶解させ、ベースとキャッ
プを接着させるようになっているので、封止ガラスの体
積（特に厚み）のバラツキにより、ベースとキャップが
傾いたり、パッケージ自身の外形寸法が一定しないとい
う問題がある。In the conventional semiconductor integrated circuit device described above, the sealing glass is melted by heat treatment at high temperature and the base and cap are bonded together. There are problems with the cap being tilted and the external dimensions of the package itself being inconsistent.
本発明の目的は、かかる問題を解消する半導体集積回路
装置を提供することにある。An object of the present invention is to provide a semiconductor integrated circuit device that solves this problem.
本発明の半導体集積回路装置は、−主面に半導体集積回
路が形成された半導体チップと、この半導体チップを固
着する窪み面を有するベースと、このベースの前記窪み
を塞ぎ前記半導体チップを密封するキャップと、前記ベ
ースの前記窪みと前記半導体チップとの間に挿入される
フレームとを備え構成される。The semiconductor integrated circuit device of the present invention includes: - a semiconductor chip having a semiconductor integrated circuit formed on its main surface; a base having a recessed surface to which the semiconductor chip is fixed; and a base having a recessed surface to which the semiconductor chip is sealed by closing the recess of the base. The device includes a cap, and a frame inserted between the recess of the base and the semiconductor chip.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例を示す半導体集積回路装置の
縦断面図、第２図は第１図のフレームを示す斜視図であ
る。この半導体集積回路装置は、第１図に示すように、
半導体チップ５とベース１の間に挿入されるフレーム６
を設けたことである。また、この半導体集積回路装置は
半導体チップ５のパッドとワイヤ７を介して接続された
り−ド３は、封止ガラス４によりベース２に圧着されて
いる。さらに、キャップ１にも封止ガラスが印刷されて
いる。一方、半導体チップ５はベースに１ダイボンデイ
ングされている。このフレーム６は、ワイヤ７で配線し
た後に挿入することによって、キャップ１の位置決めに
もなるし、キャップ１とベース２のずれを生じることが
なくなる。すなわち、フレーム６を挿入してから、高温
で熱処理することにより、封止ガラスが溶解し、そこで
、キャップまたはベースの重さにより、キャラプルベー
ス間の間隔がせばまり、フレーム６により位置決めされ
る。FIG. 1 is a longitudinal sectional view of a semiconductor integrated circuit device showing an embodiment of the present invention, and FIG. 2 is a perspective view showing the frame of FIG. 1. This semiconductor integrated circuit device, as shown in FIG.
A frame 6 inserted between the semiconductor chip 5 and the base 1
This is because we have established the following. Further, this semiconductor integrated circuit device is connected to pads of a semiconductor chip 5 via wires 7, and the pad 3 is press-bonded to the base 2 through a sealing glass 4. Furthermore, the cap 1 is also printed with sealing glass. On the other hand, the semiconductor chip 5 has one die bonded to the base. By inserting the frame 6 after wiring with the wires 7, it also serves to position the cap 1 and prevents the cap 1 and the base 2 from being misaligned. That is, by inserting the frame 6 and heat-treating it at a high temperature, the sealing glass is melted, and the weight of the cap or base narrows the gap between the caps and the caps, and the frame 6 positions them. Ru.
一方、フレーム６は第２図に示すように、キャップ１の
窪みに挿入されるように枠６ｂが形成されており、足６
ａは、ワイヤが邪魔にならないように、四隅に形成され
ている。なお、このフレーム６は絶縁材料で製作されて
おり、剛性が多少必要であるため、例えば、ポリカーボ
ネート樹脂で製作されている。On the other hand, as shown in FIG.
a are formed at the four corners so that the wires do not get in the way. Note that this frame 6 is made of an insulating material and requires some degree of rigidity, so it is made of, for example, polycarbonate resin.
以上説明したように本発明の半導体集積回路装置は、搭
載された半導体チップとベースの窪みとの間に挿入され
るフレームを設けることにより、ベースとキャップのず
れをなくし、パッケージの外形寸法を一定にできるとと
もに薄型パッケージでのボンディングの作業性向上９歩
留り向上、さらに半導体装置での故障率の低減等を実現
できるという効果がある。As explained above, the semiconductor integrated circuit device of the present invention eliminates misalignment between the base and the cap by providing a frame inserted between the mounted semiconductor chip and the recess of the base, and the external dimensions of the package are kept constant. In addition, it is possible to improve bonding workability in thin packages, improve yields, and reduce failure rates in semiconductor devices.
第１図は本発明の一実施例を示す半導体集積回路装置の
縦断面図、第２図は第１図のフレームを示す斜視図であ
る。
１・・・キャップ、２・・・ベース、３・・・リード、
４・・・封止ガラス、５・・・チップ、６・・・フレー
ム、６ａ・・・足、６ｂ・・・枠、７・・・ワイヤ。
力 １ 図FIG. 1 is a longitudinal sectional view of a semiconductor integrated circuit device showing an embodiment of the present invention, and FIG. 2 is a perspective view showing the frame of FIG. 1. 1...cap, 2...base, 3...lead,
4... Sealing glass, 5... Chip, 6... Frame, 6a... Leg, 6b... Frame, 7... Wire. force 1 diagram
Claims (1)
、この半導体チップを固着する窪み面を有するベースと
、このベースの前記窪みを塞ぎ前記半導体チップを密封
するキャップと、前記ベースの前記窪みと前記半導体チ
ップとの間に挿入されるフレームとを備えることを特徴
とする半導体集積回路装置。a semiconductor chip having a semiconductor integrated circuit formed on one main surface; a base having a recessed surface to which the semiconductor chip is fixed; a cap that closes the recess of the base and seals the semiconductor chip; A semiconductor integrated circuit device comprising a frame inserted between the semiconductor chip and the semiconductor chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26959889A JPH03129858A (en) | 1989-10-16 | 1989-10-16 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26959889A JPH03129858A (en) | 1989-10-16 | 1989-10-16 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03129858A true JPH03129858A (en) | 1991-06-03 |
Family
ID=17474595
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26959889A Pending JPH03129858A (en) | 1989-10-16 | 1989-10-16 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03129858A (en) |
-
1989
- 1989-10-16 JP JP26959889A patent/JPH03129858A/en active Pending
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