JPH03126345A - Packet receiver - Google Patents
Packet receiverInfo
- Publication number
- JPH03126345A JPH03126345A JP1265549A JP26554989A JPH03126345A JP H03126345 A JPH03126345 A JP H03126345A JP 1265549 A JP1265549 A JP 1265549A JP 26554989 A JP26554989 A JP 26554989A JP H03126345 A JPH03126345 A JP H03126345A
- Authority
- JP
- Japan
- Prior art keywords
- packet
- circuit
- output
- digital filter
- reception
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005540 biological transmission Effects 0.000 claims abstract description 8
- 230000004044 response Effects 0.000 claims abstract description 4
- 206010000210 abortion Diseases 0.000 abstract 1
- 230000002401 inhibitory effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 230000001276 controlling effect Effects 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
Landscapes
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はパケット受信装置に関し、特に流量規制が可能
なパケット受信装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a packet receiving device, and particularly to a packet receiving device capable of regulating flow rate.
従来のパケット受信装置では、送信側からのパケットに
対する受信可否の応答により後続のパケットの送信の可
否を判断するよう流量制御している。In a conventional packet receiving device, the flow rate is controlled so that it is determined whether or not a subsequent packet can be transmitted based on a response from the transmitting side as to whether or not the packet can be received.
上述した従来のパケット受信装置では、流量制御時に受
信装置における処理量の増加により高速な伝送が不可能
になるという欠点がある。The conventional packet receiving device described above has a drawback in that high-speed transmission becomes impossible due to an increase in the processing amount in the receiving device when controlling the flow rate.
本発明のパケット受信装置は、伝送路上のパケットを受
信する受信回路と、受信した前記パケットに応答してパ
ルスを発生する少くとも１個のパルス発生回路と、各該
パルス発生回路に接続されたディジタルフィルタと、該
ディジタルフィルタの出力信号とあらかじめ定められた
値とを比較する比較回路と、該比較回路で前記ディジタ
ルフィルタの出力値があらかじめ定められた値を越えた
と判断された場合に対応する前記パケットの内容の出力
を禁止する制御バスとを備えている。The packet receiving device of the present invention includes a receiving circuit that receives packets on a transmission path, at least one pulse generating circuit that generates a pulse in response to the received packet, and a plurality of pulse generating circuits connected to each of the pulse generating circuits. a digital filter, a comparison circuit that compares an output signal of the digital filter with a predetermined value, and a case where the comparison circuit determines that the output value of the digital filter exceeds the predetermined value. and a control bus that prohibits output of the contents of the packet.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の第１の実施例のブロック図である。同
図において、端子ｌからパケットが入力される。端子ｌ
には伝送路が接続される。入力されたパケットは受信回
路２に入力される。受信回路２に於いて後述のごとく受
信可能状態にあれば、パケットを端子３を介して端末、
パケット中継装置、パケット交換機などに出力する。受
信回路２からの出力信号は、分岐してパルス発生回路５
にも入力される。パルス発生回路５は、パケットが入力
するごとに一定のパルスを出力する。この出力パルスは
、ディジタルフィルタ６に入力される。ディジタルは、
例えば第２図に示すごとく加算器６０．遅延器６１１乗
算器６２から成る１次フィルタで構成され、入力の平滑
可効果を持つ。これの平滑出力信号は、端子４に設定さ
れた一定値と比較器１ｉＩ８７にて比較される。もしも
平滑出力が一定値を上回る場合には既に決められた以上
のトラヒックが入力されたと判断し、受信不能状態とす
る。さもなければ受信可能状態と判断する。この比較出
力信号は受信回路２に入力され、受信回路２は、受信不
能状態時に入力されたパケットを廃棄し、受信可能状態
時に入力されたパケットは直ちに端子３を介して出力す
る。FIG. 1 is a block diagram of a first embodiment of the present invention. In the figure, a packet is input from terminal l. terminal l
A transmission line is connected to. The input packet is input to the receiving circuit 2. If the receiving circuit 2 is in a receivable state as described below, the packet is sent to the terminal via the terminal 3.
Output to a packet relay device, packet switch, etc. The output signal from the receiving circuit 2 is branched and sent to the pulse generating circuit 5.
is also entered. The pulse generation circuit 5 outputs a constant pulse every time a packet is input. This output pulse is input to the digital filter 6. Digital is
For example, as shown in FIG. 2, an adder 60. It is composed of a first-order filter consisting of a delay device 611 and a multiplier 62, and has a smoothing effect on the input. This smoothed output signal is compared with a constant value set at terminal 4 by comparator 1iI87. If the smoothed output exceeds a certain value, it is determined that more traffic than the predetermined amount has been input, and the device is placed in a reception-disabled state. Otherwise, it is determined that the state is ready for reception. This comparison output signal is input to the receiving circuit 2, which discards the packet inputted in the unreceivable state, and immediately outputs the packet inputted in the receivable state via the terminal 3.
第３図は本発明の第２の実施例のブロック図である０本
実施例は、第１の実施例における受信回路２および端子
３の間に一時記憶用の記憶回路８を介設した構成を有し
、比較回路７の比較出力は記憶回路８に入力され、記憶
回路８においては、受信不能状態であればパケットの出
力は中断され、受信可能状態であれば記憶されたパケッ
トは順次端子３を介して出力される。FIG. 3 is a block diagram of a second embodiment of the present invention. This embodiment has a configuration in which a storage circuit 8 for temporary storage is interposed between the receiving circuit 2 and the terminal 3 in the first embodiment. The comparison output of the comparison circuit 7 is input to the storage circuit 8. In the storage circuit 8, if the reception is not possible, the output of the packet is interrupted, and if the reception is possible, the stored packets are sequentially sent to the terminal. 3.
第４図は本発明の第３の実施例のブロック図である０本
実施例は、第１の実施例における受信回路２および端子
３の間に識別分岐図Ｎ９、記憶回＃ｒ８１および８２を
介設した構成を有する。端子１から入力されたパケット
は受信回路２人力される。受信されたパケットは識別分
岐回路９に入力される。受信パケットのフォーマットに
は仮想回線識別番号が含まれており、識別分岐回路９に
おいてはこの仮想回線識別番号を解読し、該当する出力
に分岐させる０分岐された各出力信号は、それぞれ記憶
回路８１および８２に入力し一時記憶される。各記憶回
路８１および８２に於いて後述のごとく受信可能状態に
あれば、パケットを出力する。記憶回路８１および８２
の各出力は、バス結合され端子３を介して端末、パケッ
ト中継装置、パケット交換機などに出力する。各記憶回
路からの出力はそれぞれパルス発生回路５１．５２にも
入力される。パルス発生回路５１および５２においては
、パケットが入力するごとに一定のパルスが出力される
。この出力パルスは、それぞれディジタルフィルタ６１
．６２に入力される。ディジタルフィルタ６１．６２の
平滑出力信号は、端子４１および４２に設定された一定
値と比較回路７１および７２に比較される。もしも平滑
出力が一定値を上回る場合には予め決められた以上のト
ラヒックが入力されたと判断し、受信不能状態とする。FIG. 4 is a block diagram of a third embodiment of the present invention. This embodiment has an identification branch diagram N9 and memory circuits #r81 and 82 between the receiving circuit 2 and the terminal 3 in the first embodiment. It has an interposed configuration. A packet input from terminal 1 is sent to two receiving circuits. The received packet is input to the identification branch circuit 9. The format of the received packet includes a virtual line identification number, and the identification branching circuit 9 decodes this virtual line identification number and branches it to the corresponding output. Each branched output signal is stored in a storage circuit 81. and 82 and is temporarily stored. If each of the storage circuits 81 and 82 is in a receivable state as described later, the packet is output. Memory circuits 81 and 82
Each output is bus-coupled and output to a terminal, a packet relay device, a packet switch, etc. via a terminal 3. The output from each memory circuit is also input to pulse generation circuits 51 and 52, respectively. The pulse generating circuits 51 and 52 output a constant pulse every time a packet is input. These output pulses are each passed through a digital filter 61.
．． 62. The smoothed output signals of digital filters 61 and 62 are compared with constant values set at terminals 41 and 42 in comparison circuits 71 and 72. If the smoothed output exceeds a certain value, it is determined that more traffic than a predetermined value has been input, and the reception is disabled.
さもなければ受信可能状態と判断する。Otherwise, it is determined that the state is ready for reception.
この各比較出力はそれぞれ記憶回路８１および８２に入
力され、記憶回路８１および８２においてはそれぞれ受
信不能状態であればパケットの出力は中断され、受信可
能状態であれば記憶されたパケットは他回路との調停の
もと順次端子３を介して出力される。These comparison outputs are input to storage circuits 81 and 82, respectively, and in storage circuits 81 and 82, if the reception is not possible, output of the packet is interrupted, and if the reception is possible, the stored packet is transferred to other circuits. The signals are sequentially outputted via terminal 3 under arbitration.
以上説明した通り本発明は、パケットの受信量を計測す
ることにより簡単な流量制御を与え、よって流量が多い
高速なパケット伝送網を構成できる効果をもつ。As explained above, the present invention provides simple flow rate control by measuring the amount of received packets, and has the effect of configuring a high-speed packet transmission network with a large flow rate.
第１図〜第４図は本発明の実施例を示すブロック図であ
る。
１．３．４．４１．４２・・・端子、２・・・受信回路
、５．５１．５２・・・パルス発生回路、６．６１．６
２・・・ディジタルフィルタ、７，７１．７２・・・比
較回路、
８゜
回路。
２・・・記憶回路、1 to 4 are block diagrams showing embodiments of the present invention. 1.3.4.41.42...Terminal, 2...Receiving circuit, 5.51.52...Pulse generation circuit, 6.61.6
2... Digital filter, 7, 71.72... Comparison circuit, 8° circuit. 2...Memory circuit,
Claims (1)
記パケットに応答してパルスを発生する少くとも１個の
パルス発生回路と、各該パルス発生回路に接続されたデ
ィジタルフィルタと、該ディジタルフィルタの出力信号
とあらかじめ定められた値とを比較する比較回路と、該
比較回路で前記ディジタルフィルタの出力値があらかじ
め定められた値を越えたと判断された場合に対応する前
記パケットの内容の出力を禁止する制御パスとを備えて
いることを特徴とするパケット受信装置。a receiving circuit that receives packets on a transmission path; at least one pulse generating circuit that generates a pulse in response to the received packet; a digital filter connected to each of the pulse generating circuits; a comparison circuit that compares the output signal with a predetermined value; and a prohibition of outputting the contents of the corresponding packet when the comparison circuit determines that the output value of the digital filter exceeds the predetermined value. What is claimed is: 1. A packet receiving device comprising: a control path;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26554989A JP2655437B2 (en) | 1989-10-11 | 1989-10-11 | Packet receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26554989A JP2655437B2 (en) | 1989-10-11 | 1989-10-11 | Packet receiver |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03126345A true JPH03126345A (en) | 1991-05-29 |
| JP2655437B2 JP2655437B2 (en) | 1997-09-17 |
Family
ID=17418661
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26554989A Expired - Lifetime JP2655437B2 (en) | 1989-10-11 | 1989-10-11 | Packet receiver |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2655437B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5859580A (en) * | 1996-09-05 | 1999-01-12 | Yazaki Corporation | Service plug having male and female terminals permanently coupled to the service plug for closing a protected circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6342543A (en) * | 1986-08-08 | 1988-02-23 | Nippon Telegr & Teleph Corp <Ntt> | Packet flow controlling system |
-
1989
- 1989-10-11 JP JP26554989A patent/JP2655437B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6342543A (en) * | 1986-08-08 | 1988-02-23 | Nippon Telegr & Teleph Corp <Ntt> | Packet flow controlling system |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5859580A (en) * | 1996-09-05 | 1999-01-12 | Yazaki Corporation | Service plug having male and female terminals permanently coupled to the service plug for closing a protected circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2655437B2 (en) | 1997-09-17 |
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