JPH0312480B2 - - Google Patents
Info
- Publication number
- JPH0312480B2 JPH0312480B2 JP10406685A JP10406685A JPH0312480B2 JP H0312480 B2 JPH0312480 B2 JP H0312480B2 JP 10406685 A JP10406685 A JP 10406685A JP 10406685 A JP10406685 A JP 10406685A JP H0312480 B2 JPH0312480 B2 JP H0312480B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- interlayer insulating
- integrated circuit
- insulating layer
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000010410 layer Substances 0.000 claims description 71
- 239000011229 interlayer Substances 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 24
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 13
- 238000010438 heat treatment Methods 0.000 claims description 11
- 238000004544 sputter deposition Methods 0.000 claims description 11
- 239000000203 mixture Substances 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 description 7
- 238000005530 etching Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000012495 reaction gas Substances 0.000 description 2
- 229910018557 Si O Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Electronic Switches (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は集積回路装置に関し、特に絶縁基板上
に複数の電極を層間絶縁層を介して少なくとも二
層に配設してなる集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit device, and more particularly to an integrated circuit device in which a plurality of electrodes are arranged in at least two layers on an insulating substrate with an interlayer insulating layer interposed therebetween. .
上述のような集積回路装置は、例えば感熱記録
用サーマルヘツド等に広く使用されている。この
ような集積回路装置における二層電極間の層間絶
縁層にピンホールがあると、このピンホールによ
り短絡が生ずる。
Integrated circuit devices such as those described above are widely used, for example, in thermal heads for heat-sensitive recording. If there is a pinhole in the interlayer insulating layer between the two electrode layers in such an integrated circuit device, the pinhole will cause a short circuit.
従来、回路板を一組ですますことにより構成を
簡単にし、印字直後に印字像を見られるように
し、かつ絶縁基板表面に印字カスがたまらないよ
うにするために、発熱要素を絶縁基板の端部に偏
らせて配列し、通電用のリードを発熱要素の列の
片側のみから引出すようにしたサーマルヘツドに
おいて、前記ピンホールによる短絡を防止するた
め、上層電極と下層電極の重なる面積を小さくす
るように、下層電極を最小導体幅とすることが知
られている（特開昭57−95484号公報）。このよう
に下層電極の面積を小さくすると、基板が絶縁物
であるためプラズマ反応コーテイング（以下、Ｐ
−CVDと表わす）やスパツターによる蒸着（以
下、単にスパツターと言う）で層間絶縁層を均一
に形成することが困難で、膜厚部分は剥れたりあ
るいは割れたり、また膜厚部分にピンホールが形
成し易い問題点がある。 Conventionally, in order to simplify the configuration by using only one circuit board, to make the printed image visible immediately after printing, and to prevent printing residue from accumulating on the surface of the insulating board, the heating element was placed at the edge of the insulating board. In a thermal head in which the conductive leads are drawn out from only one side of the row of heating elements, the overlapping area of the upper and lower electrodes is reduced to prevent short circuits due to the pinholes. It is known that the lower layer electrode has a minimum conductor width (Japanese Patent Laid-Open No. 57-95484). When the area of the lower electrode is reduced in this way, since the substrate is an insulator, plasma reaction coating (hereinafter referred to as P
It is difficult to form an interlayer insulating layer uniformly by CVD (hereinafter referred to as CVD) or vapor deposition using a sputter (hereinafter simply referred to as sputter), and the thick part of the film peels off or cracks, or there are pinholes in the thick part of the film. There are problems that are easy to form.
本発明は、上述の問題点を解消するためになさ
れたものであり、Ｐ−CVDやスパツターで下層
電極上に窒化けい素や酸化けい素の層間絶縁層を
均一にピンホールなく形成することができ、した
がつて上層電極を層間絶縁層を介し下層電極と重
なるように設けて短絡の生ずることがなく、その
ために発熱要素を絶縁基板の端部に偏らせて配列
したサーマルヘツドの信頼性を高めることができ
る多層配線の集積回路装置の提供を目的とする。
The present invention has been made to solve the above-mentioned problems, and it is possible to uniformly form an interlayer insulating layer of silicon nitride or silicon oxide on a lower electrode using P-CVD or sputtering without pinholes. Therefore, the upper layer electrode is provided so as to overlap the lower layer electrode through the interlayer insulating layer, and short circuits do not occur, which improves the reliability of the thermal head in which the heat generating elements are arranged biased toward the edge of the insulating substrate. An object of the present invention is to provide an integrated circuit device with multilayer wiring that can be improved.
本発明者は前記目的を達成すべく鋭意研究の結
果、下層電極の配線パターンを絶縁基板の上面の
70％以上を覆うものにして、層間絶縁層をＰ−
CVDやスパツターで形成した窒化けい素または
酸化けい素もしくはその混合からなる層にする
と、下層電極の配線パターンにより絶縁基板の導
電性が高められ、そのためにＰ−CVDやスパツ
ターによる窒化けい素や酸化けい素膜の形成速度
が早くなり、そして特に下層電極上に形成される
膜が均一性に優れてピンホールのないものになる
こと、したがつて上層電極を下層電極上の均一で
ピンホールのない層間絶縁層に設けるようにすれ
ば、上層電極の形成も容易で、かつ、短絡の生ず
れ惧れもないことを究明した。本発明は、この知
見に基いてなされたものである。
As a result of intensive research to achieve the above object, the inventor of the present invention found that the wiring pattern of the lower layer electrode was
The interlayer insulating layer should be P-
If the layer is made of silicon nitride or silicon oxide or a mixture thereof formed by CVD or sputtering, the conductivity of the insulating substrate will be increased by the wiring pattern of the lower electrode. The formation speed of the silicon film becomes faster, and in particular, the film formed on the lower layer electrode has excellent uniformity and no pinholes. It has been found that if the upper layer electrode is provided on an interlayer insulating layer that does not have an upper layer, it is easy to form the upper layer electrode, and there is no risk of short circuits. The present invention has been made based on this knowledge.
本発明は、絶縁基板上に複数の電極を層間絶縁
層を介して少なくとも二層に配設してなる集積回
路装置において、下層電極の配設パターンを絶縁
基板の上面の70％以上を覆うものにして、前記層
間絶縁層をＰ−CVDやスパツターで形成した窒
化けい素または酸化けい素もしくはその混合から
なる層にすると共に、下層電極の配設パターンと
上層電極の配設パターンを大部分が重なる実質的
に同一のものとしたことを特徴とする集積回路装
置にあり、この構成によつて前記目的を達成す
る。 The present invention relates to an integrated circuit device in which a plurality of electrodes are arranged in at least two layers on an insulating substrate with an interlayer insulating layer interposed therebetween, in which the arrangement pattern of the lower layer electrodes covers 70% or more of the upper surface of the insulating substrate. The interlayer insulating layer is made of silicon nitride, silicon oxide, or a mixture thereof formed by P-CVD or sputtering, and the arrangement pattern of the lower layer electrode and the arrangement pattern of the upper layer electrode are mostly changed. The present invention is an integrated circuit device characterized by overlapping and substantially identical circuits, and this structure achieves the above object.
以下、本発明をサーマルヘツドに適用した図示
例によつて説明する。第１図は、下層電極の配設
パターン平面図、第２図は層間絶縁層平面図、第
３図は抵抗発熱体部分を除いた上層電極の配設パ
ターン平面図、第４図は集積回路装置としてのサ
ーマルヘツドの上面図、第５図は第４図のＢ部の
拡大図、第６図は第４図のＡ−A′断面図、第７
図は第４図のＣ−C′断面図、第８図は下層電極配
設パターンの電極面積／絶縁基板の面積比とＰ−
CVDによる窒化けい素の成長速度及び形成膜の
均一性との関係を示すグラフである。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained below using an illustrated example in which the present invention is applied to a thermal head. Fig. 1 is a plan view of the arrangement pattern of the lower layer electrode, Fig. 2 is a plan view of the interlayer insulating layer, Fig. 3 is a plan view of the arrangement pattern of the upper layer electrode excluding the resistive heating element, and Fig. 4 is the integrated circuit. A top view of the thermal head as a device, FIG. 5 is an enlarged view of section B in FIG. 4, FIG. 6 is a sectional view taken along line A-A' in FIG.
The figure is a cross-sectional view taken along the line C-C' in Fig. 4, and Fig. 8 shows the electrode area/insulating substrate area ratio of the lower electrode arrangement pattern and P-
3 is a graph showing the relationship between the growth rate of silicon nitride by CVD and the uniformity of the formed film.
図において、４はアルミナセラミツク等からな
る絶縁基板、３は熱コントロールのために必要に
応じて設けられる硝子材料等からなるグレーズ
層、６はMo、Ta、Ｗ等からなる共通電極の下層
電極、７は絶縁基板４と下層電極６上に設けられ
た窒化けい素または酸化けい素もしくはその混合
からなる層間絶縁層、２はTa2N、Cr−Si−Ｏ等
からなる上層電極の抵抗発熱体、８および９は下
層電極６と同様の材料からなる上層電極の共通電
極および個別電極（信号電極）である。抵抗発熱
体２は共通電極８と個別電極９が0.1〜0.3mmの間
〓で対向している間を接続してその間を発熱部１
とするように、共通電極８と個別電極９の形成に
先立つて形成される。５は下層電極６と上層電極
の共通電極８またはその下側に接続している抵抗
発熱体２との接続が行われるように層間絶縁層７
に設けたスルーホールである。 In the figure, 4 is an insulating substrate made of alumina ceramic, etc., 3 is a glaze layer made of glass material, etc. provided as necessary for heat control, 6 is a lower electrode of a common electrode made of Mo, Ta, W, etc.; 7 is an interlayer insulating layer made of silicon nitride, silicon oxide, or a mixture thereof provided on the insulating substrate 4 and the lower electrode 6, and 2 is a resistance heating element of the upper electrode made of Ta 2 N, Cr-Si-O, etc. , 8 and 9 are a common electrode and individual electrodes (signal electrodes) of the upper layer electrode made of the same material as the lower layer electrode 6. The resistance heating element 2 connects the common electrode 8 and the individual electrodes 9 facing each other with a distance of 0.1 to 0.3 mm, and connects the heating element 1 between them.
This is formed prior to the formation of the common electrode 8 and the individual electrodes 9, as shown in FIG. 5 is an interlayer insulating layer 7 so that the lower electrode 6 is connected to the common electrode 8 of the upper electrode or the resistance heating element 2 connected to the lower side thereof.
This is a through hole made in the.
共通電極の下層電極６や抵抗発熱体２、共通電
極８、個別電極９から成る上層電極は蒸着膜をホ
トレジストを用いてエツチングする方法やマスク
を介するスパツターによる方法等によつて形成さ
れ、スルーホール５を有する層間絶縁層７もＰ−
CVDやスパツターを用いて同様の方法で形成さ
れる。そして下層電極６と上層電極は、下層電極
６が絶縁基板４の上面の70％以上を被覆し、かつ
下層電極６と上層電極が層間絶縁層７を介して大
部分が重なる実質的に同一の配設パターンに形成
する。 The lower electrode 6 of the common electrode, the upper electrode consisting of the resistance heating element 2, the common electrode 8, and the individual electrodes 9 are formed by etching a vapor deposited film using photoresist, sputtering through a mask, etc., and are formed by using through holes. The interlayer insulating layer 7 having P-
It is formed in a similar manner using CVD or sputtering. The lower layer electrode 6 and the upper layer electrode are substantially the same, with the lower layer electrode 6 covering 70% or more of the upper surface of the insulating substrate 4, and the lower layer electrode 6 and the upper layer electrode mostly overlapping with each other with the interlayer insulating layer 7 in between. Form into a layout pattern.
このように下層電極６を絶縁基板４の上面の70
％以上を被覆する（例えば、下層電極６の材料を
Moとした場合は70％以上、Taとした場合は80％
以上、Ｗとした場合は70％以上とするのが望まし
い）ものとしたことにより、絶縁基板４の上面の
導電性が良くなり、そのために層間絶縁層７のＰ
−CVDやスパツターによる形成速度が早くなつ
て、特に下層電極６上に形成される層間絶縁層７
が膜厚の均一性に優れて薄い膜厚でピンホールの
ないものにする。すなわち、窒化けい素、酸化け
い素をＰ−CVDあるいはスパツターで成膜する
と、下層電極６上では300〜1000Å／minの成長
速度で均一に形成されて、5000Å／μｍの膜厚で
完全にピンホールのないものにできる。特に、窒
化けい素と酸化けい素の複合膜とした場合は、窒
化けい素の応力歪みを酸化けい素で吸収する作用
を有するから、凹凸の大きい面でもカバーし合つ
て平坦でかつピンホールのない膜を形成すること
ができ、しかも容易に連続的に成膜できるので最
も好ましい。なお、窒化けい素や酸化けい素は温
度が500〜700℃の高温になつても変質することな
く安定である。層間絶縁層７が以上のように特に
下層電極６上でピンホールなく均一に形成される
ので、例えば層間絶縁層７にスルーホール５をエ
ツチング法で形成するためのホトレジスト膜を設
けた場合、ホトレジスト膜も層間絶縁層７の下層
電極６上部分では均一の膜厚のピンホールのない
ものになる。したがつて、エツチング法でスルー
ホール５を形成する際にホトレジスト膜のピンホ
ール等でスルーホール５以外の部分にもエツチン
グが生じるのは、層間絶縁層７の下層電極６上部
分ではなく、絶縁基板４の凹凸の激しい部分と言
うことになる。そこで、下層電極６と上層電極を
大部分が重なる実質的に同一の配設パターンとし
たことにより、たとえ層間絶縁層７にスルーホー
ル５以外の部分でエツチングが生じていたとして
も、それは絶縁基板４上の部分であり、下層電極
６と上層電極はピンホールのない層間絶縁層７の
下層電極６上部分で絶縁されて、短絡を生じさせ
ることがない。 In this way, the lower electrode 6 is connected to the upper surface of the insulating substrate 4 at 70°
% or more (for example, if the material of the lower layer electrode 6 is
More than 70% when set to Mo, 80% when set to Ta
As mentioned above, by using W (preferably 70% or more), the conductivity of the upper surface of the insulating substrate 4 is improved, and therefore the P of the interlayer insulating layer 7 is
- The interlayer insulating layer 7 formed on the lower electrode 6 has become faster due to CVD or sputtering.
The film should be thin and pinhole-free with excellent film thickness uniformity. That is, when silicon nitride or silicon oxide is deposited by P-CVD or sputtering, it is uniformly formed on the lower electrode 6 at a growth rate of 300 to 1000 Å/min, and is completely pinned to a film thickness of 5000 Å/μm. It can be made without holes. In particular, when a composite film of silicon nitride and silicon oxide is used, the silicon oxide has the effect of absorbing the stress strain of silicon nitride, so it can cover even large uneven surfaces, making it flat and free of pinholes. This method is most preferable because it is possible to form a film that does not contain any carbon dioxide, and it is also easy to form a film continuously. Note that silicon nitride and silicon oxide are stable without deterioration even at high temperatures of 500 to 700°C. As described above, the interlayer insulating layer 7 is formed uniformly without pinholes, especially on the lower electrode 6. For example, when a photoresist film is provided for forming the through holes 5 in the interlayer insulating layer 7 by etching, the photoresist The film also has a uniform thickness and no pinholes in the portion of the interlayer insulating layer 7 above the lower electrode 6. Therefore, when forming the through hole 5 by the etching method, etching occurs in areas other than the through hole 5 due to pinholes in the photoresist film, rather than in the upper part of the lower electrode 6 of the interlayer insulating layer 7. This can be said to be a highly uneven part of the substrate 4. Therefore, by making the lower layer electrode 6 and the upper layer electrode have substantially the same arrangement pattern in which most of them overlap, even if etching occurs in the interlayer insulating layer 7 at a portion other than the through hole 5, it will not occur on the insulating substrate. The lower electrode 6 and the upper electrode are insulated by the upper part of the lower electrode 6 of the interlayer insulating layer 7 without pinholes, so that no short circuit occurs.
Ｐ−CVDによる成膜の実施例を挙げると次の
通りである。 Examples of film formation by P-CVD are as follows.
実施例 １
窒化けい素膜の形成
ASM（Advanced Semiconductor Materials）
社製の容量結合型プラズマCVD装置を使用し、
成膜温度380℃、高周波出力250W、反応圧力
2.0Torr、
反応ガス SiH4 350SCCM
NH3 2.5LPM
の一定条件下で、アルミナセラミツク絶縁基板と
その上に設けたMo膜の下層電極上にＰ−CVDに
よりSiN膜を形成する。この場合、絶縁基板の面
積とMo電極面積の比率によつて表面に形成され
るSiN膜の成長速度と電極上面内の厚さの均一性
を示すと第８図の通りである。この図が示すよう
に電極面積／基板（セラミツク）面積の比が大き
くなる程、成長速度は速くなると共に厚さの均一
性は極めて優れたものとなる。そして厚さの均一
性の向上に伴つて薄い厚さでもピンホールがなく
なる。電極材料として、Al、Taを使用した場合
もMoの場合と殆んどである。Example 1 Formation of silicon nitride film ASM (Advanced Semiconductor Materials)
Using Capacitively Coupled Plasma CVD equipment manufactured by Co., Ltd., film formation temperature was 380℃, high frequency output was 250W, and reaction pressure was
A SiN film is formed by P-CVD on the alumina ceramic insulating substrate and the lower electrode of the Mo film provided thereon under constant conditions of 2.0 Torr and reaction gas SiH 4 350 SCCM NH 3 2.5 LPM. In this case, FIG. 8 shows the growth rate of the SiN film formed on the surface and the uniformity of the thickness within the upper surface of the electrode depending on the ratio of the area of the insulating substrate to the area of the Mo electrode. As shown in this figure, the larger the ratio of electrode area/substrate (ceramic) area, the faster the growth rate and the more excellent the uniformity of the thickness. As the uniformity of the thickness improves, pinholes are eliminated even at a thin thickness. In most cases, Al or Ta is used as the electrode material, as is Mo.
実施例 ２
酸化けい素膜の形成
実施例１と同じ装置を使用し、
成膜温度300℃、高周波出力200W、反応圧力
1.0Torr、
反応ガス SiH4 80SCCM
N2O 3.5LPM
の一定条件で実施例１と同じ基板および電極上に
酸化けい素膜を形成する。この場合も第８図と同
様の結果が得られた。Example 2 Formation of silicon oxide film Using the same equipment as in Example 1, film formation temperature 300°C, high frequency output 200W, reaction pressure
A silicon oxide film is formed on the same substrate and electrode as in Example 1 under constant conditions of 1.0 Torr and reaction gas SiH 4 80 SCCM N 2 O 3.5 LPM. In this case as well, the same results as in FIG. 8 were obtained.
なお、Ｐ−CVDの代わりにスパツターによつ
ても同様の結果が得られる。 Note that similar results can be obtained by sputtering instead of P-CVD.
本発明の集積回路装置は、下層電極の配設パタ
ーンを絶縁基板の上面の70％以上を覆うものにし
て、層間絶縁層をＰ−CVDスパツターで形成し
た窒化けい素または酸化けい素もしくはその混合
からなる層にすると共に、下層電極の配設パター
ンと上層電極の配設パターンを大部分が重なる実
質的に同一のものとしたことによつて、Ｐ−
CVDやスパツターで形成される窒化けい素や酸
化けい素の層間絶縁層が特に下層電極上で成長速
度早く均一にピンホールなく形成されて、下層電
極と上層電極の間に短絡の発生することがなく、
したがつて発熱要素の端面に持つ感熱記録用サー
マルヘツドに構成した場合にはサーマルヘツドが
極めて信頼性の高いものになると言つた優れた効
果を奏する。なお、本発明はサーマルヘツドの例
に限定されるものではない。
In the integrated circuit device of the present invention, the lower electrode arrangement pattern covers 70% or more of the upper surface of the insulating substrate, and the interlayer insulating layer is made of silicon nitride, silicon oxide, or a mixture thereof formed by P-CVD sputtering. By creating a layer consisting of P-
The interlayer insulating layer of silicon nitride or silicon oxide formed by CVD or sputtering grows quickly and uniformly on the lower electrode, and is formed uniformly without pinholes, which prevents short circuits from occurring between the lower electrode and the upper electrode. Without,
Therefore, when a thermal head for heat-sensitive recording is provided on the end face of a heat-generating element, an excellent effect is achieved in that the thermal head becomes extremely reliable. Note that the present invention is not limited to the example of a thermal head.
第１図は下層電極の配設パターン平面図、第２
図は層間絶縁層平面図、第３図は抵抗発熱体部分
を除いた上層電極の配設パターン平面図、第４図
は集積回路装置としてのサーマルヘツドの上面
図、第５図は第４図のＢ部の拡大図、第６図は第
４図のＡ−A′断面図、第７図は第４図のＣ−
C′断面図、第８図は下層電極配設パターンの電極
面積／絶縁基板の面積比とＰ−CVDによる窒化
けい素膜の成長速度及び形成膜の均一性との関係
を示すグラフである。
１：発熱部、２：抵抗発熱体、３：グレーズ
層、４：絶縁基板、５：スルーホール、６：下層
電極、７：層間絶縁層、８：上層共通電極、９：
上層個別電極。
Figure 1 is a plan view of the arrangement pattern of the lower layer electrode;
The figure is a plan view of the interlayer insulating layer, Figure 3 is a plan view of the arrangement pattern of the upper layer electrode excluding the resistive heating element, Figure 4 is a top view of the thermal head as an integrated circuit device, and Figure 5 is Figure 4. Figure 6 is an enlarged view of part B in Figure 4, Figure 7 is a cross-sectional view taken along line A-A' in Figure 4, and Figure 7 is a cross-sectional view taken along line C-- in Figure 4.
8 is a graph showing the relationship between the electrode area/insulating substrate area ratio of the lower electrode arrangement pattern, the growth rate of the silicon nitride film by P-CVD, and the uniformity of the formed film. DESCRIPTION OF SYMBOLS 1: Heat generating part, 2: Resistance heating element, 3: Glaze layer, 4: Insulating substrate, 5: Through hole, 6: Lower layer electrode, 7: Interlayer insulating layer, 8: Upper layer common electrode, 9:
Upper layer individual electrode.
Claims (1)
て少なくとも二層に配設してなる集積回路装置に
おいて、下層電極の配設パターンを絶縁基板の上
面の70％以上を覆うものにして、前記層間絶縁層
をプラズマ反応コーデイングまたはスパツターに
よる蒸着で形成した窒化けい素または酸化けい素
もしくはその混合からなる層にすると共に、下層
電極の配設パターンと上層電極の配設パターンを
大部分が重なる実質的に同一のものとしたことを
特徴とする集積回路装置。 ２ 集積回路装置が絶縁基板の一側縁に沿つて設
けた層間絶縁層の欠落部で上層電極と下層電極を
接続させ、上層電極の配設パターンの前記接続部
より内側の部分に抵抗発熱体を用いている感熱記
録用サーマルヘツドである特許請求の範囲第１項
記載の集積回路装置。[Claims] 1. In an integrated circuit device in which a plurality of electrodes are arranged in at least two layers on an insulating substrate with an interlayer insulating layer interposed therebetween, the arrangement pattern of the lower layer electrodes covers 70% or more of the upper surface of the insulating substrate. The interlayer insulating layer is made of silicon nitride, silicon oxide, or a mixture thereof formed by plasma reaction coding or sputter deposition, and the arrangement pattern of the lower layer electrode and the arrangement of the upper layer electrode. 1. An integrated circuit device characterized in that the design patterns are substantially the same and most of them overlap. 2. The integrated circuit device connects the upper layer electrode and the lower layer electrode at the missing part of the interlayer insulating layer provided along one side edge of the insulating substrate, and the resistance heating element is placed inside the connection part of the arrangement pattern of the upper layer electrode. The integrated circuit device according to claim 1, which is a thermal head for heat-sensitive recording using.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10406685A JPS61263299A (en) | 1985-05-17 | 1985-05-17 | Integrated circuit device |
| US06/862,617 US4768038A (en) | 1985-05-17 | 1986-05-13 | Thermal printhead integrated circuit device |
| EP86303734A EP0202877A3 (en) | 1985-05-17 | 1986-05-16 | Integrated circuit device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10406685A JPS61263299A (en) | 1985-05-17 | 1985-05-17 | Integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61263299A JPS61263299A (en) | 1986-11-21 |
| JPH0312480B2 true JPH0312480B2 (en) | 1991-02-20 |
Family
ID=14370790
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10406685A Granted JPS61263299A (en) | 1985-05-17 | 1985-05-17 | Integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61263299A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63168371A (en) * | 1986-12-30 | 1988-07-12 | Konica Corp | Theremal recording head |
-
1985
- 1985-05-17 JP JP10406685A patent/JPS61263299A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61263299A (en) | 1986-11-21 |
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