JPH03114077U - - Google Patents
Info
- Publication number
- JPH03114077U JPH03114077U JP2351990U JP2351990U JPH03114077U JP H03114077 U JPH03114077 U JP H03114077U JP 2351990 U JP2351990 U JP 2351990U JP 2351990 U JP2351990 U JP 2351990U JP H03114077 U JPH03114077 U JP H03114077U
- Authority
- JP
- Japan
- Prior art keywords
- section
- signal
- outputs
- receiver
- receives
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 5
- 230000005540 biological transmission Effects 0.000 claims description 4
- 230000000087 stabilizing effect Effects 0.000 claims 2
- 230000010354 integration Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Radar Systems Or Details Thereof (AREA)
Description
第１図はこの考案の実施例を示す構成図、第２
図はこの考案の受信機部の詳細な構成図、第３図
はこの考案のデフルータ回路と切り替え回路の構
成図、第４図Ａと第４図Ｂはこの考案の２つの使
用例のタイムチヤート、第５図は従来のレーダ装
置の構成図である。
図に於て１……フエーズドアレイアンテナ、２
……サーキユレータ、３……送信機部、４……Ｓ
ＴＡＬ部、５……Ｌ／Ｏ部、６……受信機部、７
……信号処理部、８……目標検出部、９……追尾
処理部、１０……表示部、１１……計算機部、１
２……ＢＳＣ部、１３……デフルータ部、１４…
…切り替え回路部、１５……ゲート回路部、１６
……受信機入力信号、１７……ＭＩＸ、１８……
ＦＩＬ、１９，２３……ＩＦＡＭＰ、２０……Ｄ
ＩＶ、２１，３４……ＤＬＹ、２２……ＧＡＴ、
２４，３０……ＤＥＴ、２５……ＶＩＤＡＭＰ、
２６……ＤＩＶ出力信号或いはデフルータ入力信
号、２７……受信機部内ゲート回路入力信号、２
８……受信機部出力信号、２９，３６……ＤＲＶ
、３１……Ａ／Ｄ、３２……比較回路、３３……
スレツシヨルド回路、３５……不一致回路、３７
〜４１……切り替えスイツチ、４２……切り替え
回路出力或いはゲート回路入力、４３……計算機
からの切り替え回路制御信号、４４……Ａ／Ｄ出
力信号、４５……スレツシヨルド信号、４６……
比較回路出力信号、４７……不一致回路出力信号
、４８……送信パルスタイミング波形、４９……
有効受信範囲を示すタイミング波形、５０……出
力信号波形、Ｓ１……非同期な妨害波、Ｓ２……
目標信号、Ｓ３……セカンドエコーである。なお
、図中同一或いは相当部分には同一符号を付して
示してある。
Figure 1 is a configuration diagram showing an embodiment of this invention, Figure 2
Figure 3 is a detailed configuration diagram of the receiver section of this invention, Figure 3 is a configuration diagram of the defruer circuit and switching circuit of this invention, and Figures 4A and 4B are time charts of two usage examples of this invention. , FIG. 5 is a block diagram of a conventional radar device. In the figure 1... Phased array antenna, 2
...Circulator, 3...Transmitter section, 4...S
TAL section, 5... L/O section, 6... Receiver section, 7
... Signal processing section, 8 ... Target detection section, 9 ... Tracking processing section, 10 ... Display section, 11 ... Computer section, 1
2... BSC section, 13... Defruter section, 14...
...Switching circuit section, 15...Gate circuit section, 16
...Receiver input signal, 17...MIX, 18...
FIL, 19, 23...IFAMP, 20...D
IV, 21, 34...DLY, 22...GAT,
24, 30...DET, 25...VIDAMP,
26...DIV output signal or defrouter input signal, 27...Receiver internal gate circuit input signal, 2
8... Receiver section output signal, 29, 36... DRV
, 31...A/D, 32...comparison circuit, 33...
Threshold circuit, 35... Mismatch circuit, 37
~41...Switchover switch, 42...Switching circuit output or gate circuit input, 43...Switching circuit control signal from computer, 44...A/D output signal, 45...Threshold signal, 46...
Comparison circuit output signal, 47... Mismatch circuit output signal, 48... Transmission pulse timing waveform, 49...
Timing waveform indicating effective reception range, 50...Output signal waveform, S1...Asynchronous interference wave, S2...
Target signal, S3... is a second echo. It should be noted that the same or equivalent parts in the figures are indicated by the same reference numerals.
Claims (1)
由にビーム走査することができ、さらに目標を捜
索或いは探知そして追尾する機能を有し、しかも
多目標についてそれを行うことができるフエイズ
ドアレイレーダ装置において、送信電波を外部に
放射し、目標からの反射波を受信する送受信共用
のフエイズドアレイレーダアンテナと、送信と受
信のアイソレーシヨンを行うサーキユレータと、
高周波電力パルスを出力する送信機部と、安定し
た周波数を出力する安定化発振器部と、上記安定
化発振器部からの信号を受けて後述の受信機で使
用するローカル信号を作り出すローカル信号発生
部と、上記アンテナからの入力を中間周波数信号
に変換した後、ビデオ信号として出力する受信機
部と、上記受信機部からのビデオ信号を受けて、
アナログ信号からデジタル信号へ変換するアナロ
グツウデジタルコンバータを含み、移動目標表示
機能やパルスドツプラー機能及びパルス積分機能
などを有する信号処理部と、上記信号処理部から
の信号を受けて目標検出を行う目標検出部と、上
記目標検出部からの信号を受けて目標追尾を行う
追尾処理部と、上記の各種処理ビデオを表示する
表示部と、上記信号処理部から表示部等のほとん
どの機能に連接されている計算機部と、上記アン
テナのビーム走査指令信号を出力するビームステ
アリング部と、上記受信機部から分配された入力
信号のヒツト間相関処理を行うデフルータ回路部
と、上記デフルータ回路部出力を受けて、上記計
算機部からの指令によりその出力信号やステータ
ス信号を上記受信機部や後述のゲート回路部へ出
力する切り替え回路部と、上記切り替え回路部か
らの信号を受けて上記目標検出部出力を無効なも
のにするか有効なものとして上記追尾処置部へ送
出するかを決めるゲート回路部から構成されてい
ることを特徴とするフエイズドアレイレーダ装置
。 In a phased array radar device that can freely scan the beam in the turning and elevation directions with the antenna fixed, and has the function of searching, detecting and tracking targets, and can do this for multiple targets. , a phased array radar antenna for both transmission and reception that radiates transmission radio waves to the outside and receives reflected waves from the target, and a circulator that isolates transmission and reception;
A transmitter section that outputs high-frequency power pulses, a stabilizing oscillator section that outputs a stable frequency, and a local signal generating section that receives the signal from the stabilizing oscillator section and generates a local signal to be used in the receiver described later. , a receiver section that converts the input from the antenna into an intermediate frequency signal and then outputs it as a video signal; and a receiver section that receives the video signal from the receiver section;
A signal processing unit that includes an analog-to-digital converter that converts analog signals to digital signals, and has a moving target display function, a pulse Doppler function, a pulse integration function, etc., and performs target detection upon receiving signals from the signal processing unit. A target detection unit, a tracking processing unit that receives signals from the target detection unit and performs target tracking, a display unit that displays the various processed videos described above, and the signal processing unit is connected to most functions such as the display unit. a computer section that outputs a beam scanning command signal for the antenna; a defruter circuit section that performs inter-human correlation processing of the input signal distributed from the receiver section; and a switching circuit section that outputs the output signal and status signal to the receiver section and the gate circuit section described later according to a command from the computer section, and a switching circuit section that receives the signal from the switching circuit section and outputs the target detection section. 1. A phased array radar device comprising a gate circuit section that determines whether to make the signal invalid or to send it to the tracking processing section as valid.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2351990U JPH03114077U (en) | 1990-03-08 | 1990-03-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2351990U JPH03114077U (en) | 1990-03-08 | 1990-03-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03114077U true JPH03114077U (en) | 1991-11-22 |
Family
ID=31526503
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2351990U Pending JPH03114077U (en) | 1990-03-08 | 1990-03-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03114077U (en) |
-
1990
- 1990-03-08 JP JP2351990U patent/JPH03114077U/ja active Pending