JPH0311396U - - Google Patents
Info
- Publication number
- JPH0311396U JPH0311396U JP1989071852U JP7185289U JPH0311396U JP H0311396 U JPH0311396 U JP H0311396U JP 1989071852 U JP1989071852 U JP 1989071852U JP 7185289 U JP7185289 U JP 7185289U JP H0311396 U JPH0311396 U JP H0311396U
- Authority
- JP
- Japan
- Prior art keywords
- pulse
- counter
- output
- chip microcomputer
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010363 phase shift Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 8
- 238000001514 detection method Methods 0.000 description 1
- 238000003708 edge detection Methods 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Landscapes
- Control Of Electric Motors In General (AREA)
Description
第1図は本考案の一実施例のワンチツプマイク
ロコンピユータのアツプ・ダウンカウンタ部分の
内部構造を示すブロツク図、第2図は本実施例の
使用例のシステム構成を示すブロツク図、第3図
は第2図の内部演算処理構成を示すブロツク図、
第4図〜第7図は第2図のモータの位相制御を行
なう場合の、位相誤差量検出のタイミング図、第
8図は本考案の第2の実施例の使用時のブロツク
図、第9図〜第11図は第8図のモータの回転数
制御(速度制御)を行なう場合のタイミング図、
第12図は従来方式のカウンタの内部構造を示す
ブロツク図、第13図は従来のカウンタを使用し
た場合の位相誤差量検出のプログラムのフローチ
ヤート、第14図〜第17図は第12図で位相誤
差量を検出する場合のタイミング図である。
1,2……パルス入力端子、3……シユミツト
回路、4……立上りエツジ検出回路、5,5a…
…カウントクロツクパルス、6……カウントパル
スセレクタ、7……アツプ・ダウンカウンタ、7
a……アツプカウンタ、8……制御回路、9,1
0,9a……キヤプチヤレジスタ、11……減算
回路、12……符号フラグ格納レジスタ、13…
…PWM変換器、14……パルス出力端子、15
,16……キヤプチヤ割込信号、17……CPU
内部バス、18……ワンチツプマイクロコンピユ
ータ、19……PWM出力端子、20,32……
モータ駆動回路、21……基準同期信号発生回路
、22……モータ、23……速度誤差量検出部、
24……速度ゲイン乗算部、25……定常回転数
調整用可変抵抗器、26……CPU内蔵A/D変
換器、27……CPU内蔵PWM発生部、28…
…位相誤差量検出用アツプ・ダウンカウンタ、2
9……位相補償フイルタ、30……位相ゲイン乗
算部、31……スイツチ、33……回転方向出力
端子。
Fig. 1 is a block diagram showing the internal structure of the up/down counter portion of a one-chip microcomputer according to an embodiment of the present invention, Fig. 2 is a block diagram showing the system configuration of an example of use of this embodiment, and Fig. 3 is a block diagram showing the internal arithmetic processing configuration of FIG.
4 to 7 are timing diagrams for detecting the amount of phase error when performing the phase control of the motor shown in FIG. 2, FIG. 8 is a block diagram when the second embodiment of the present invention is used, and FIG. Figures 11 to 11 are timing diagrams for controlling the rotational speed (speed control) of the motor shown in Figure 8;
Fig. 12 is a block diagram showing the internal structure of a conventional counter, Fig. 13 is a flowchart of a program for detecting the amount of phase error when using a conventional counter, and Figs. FIG. 4 is a timing diagram when detecting a phase error amount. 1, 2... Pulse input terminal, 3... Schmitt circuit, 4... Rising edge detection circuit, 5, 5a...
...Count clock pulse, 6...Count pulse selector, 7...Up/down counter, 7
a...Up counter, 8...Control circuit, 9,1
0, 9a...Capture register, 11...Subtraction circuit, 12...Sign flag storage register, 13...
...PWM converter, 14...Pulse output terminal, 15
, 16... Capture interrupt signal, 17... CPU
Internal bus, 18...One-chip microcomputer, 19...PWM output terminal, 20, 32...
Motor drive circuit, 21...Reference synchronization signal generation circuit, 22...Motor, 23...Speed error amount detection unit,
24... Speed gain multiplier, 25... Variable resistor for steady rotation speed adjustment, 26... CPU built-in A/D converter, 27... CPU built-in PWM generator, 28...
...up/down counter for detecting phase error amount, 2
9... Phase compensation filter, 30... Phase gain multiplier, 31... Switch, 33... Rotation direction output terminal.
Claims (1)
つワンチツプマイクロコンピユータにおいて、入
力クロツクパルスを選択するパルスセレクタと、
このパルスセレクタの出力をアツプまたはダウン
カウントするアツプ・ダウンカウンタと、このカ
ウンタ出力を保持する二つのキヤプチヤレジスタ
と、これらレジスタの差をとる減算回路と、この
減算出力から被測定入力パルスの位相が基準同期
信号の位相とのずれを示す位相誤差量を出力する
PWM変換器と、これら回路を制御する制御回路
とを有することを特徴とするワンチツプマイクロ
コンピユータ。 In a one-chip microcomputer having a counter unit built into one chip, a pulse selector for selecting an input clock pulse;
An up/down counter that counts up or down the output of this pulse selector, two capture registers that hold the output of this counter, a subtraction circuit that takes the difference between these registers, and an input pulse to be measured from this subtraction output. A one-chip microcomputer comprising: a PWM converter that outputs a phase error amount indicating a phase shift from a reference synchronization signal; and a control circuit that controls these circuits.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1989071852U JPH0311396U (en) | 1989-06-19 | 1989-06-19 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1989071852U JPH0311396U (en) | 1989-06-19 | 1989-06-19 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0311396U true JPH0311396U (en) | 1991-02-04 |
Family
ID=31609257
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1989071852U Pending JPH0311396U (en) | 1989-06-19 | 1989-06-19 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0311396U (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63209494A (en) * | 1987-02-24 | 1988-08-31 | Sanyo Electric Co Ltd | Speed phase servo device |
JPH01103185A (en) * | 1987-10-14 | 1989-04-20 | Hitachi Ltd | Digital servo device |
-
1989
- 1989-06-19 JP JP1989071852U patent/JPH0311396U/ja active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63209494A (en) * | 1987-02-24 | 1988-08-31 | Sanyo Electric Co Ltd | Speed phase servo device |
JPH01103185A (en) * | 1987-10-14 | 1989-04-20 | Hitachi Ltd | Digital servo device |
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