JPH03110867A - Vertical field-effect transistor - Google Patents
Vertical field-effect transistorInfo
- Publication number
- JPH03110867A JPH03110867A JP1247999A JP24799989A JPH03110867A JP H03110867 A JPH03110867 A JP H03110867A JP 1247999 A JP1247999 A JP 1247999A JP 24799989 A JP24799989 A JP 24799989A JP H03110867 A JPH03110867 A JP H03110867A
- Authority
- JP
- Japan
- Prior art keywords
- conductivity type
- diode
- region
- effect transistor
- schottky barrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 34
- 230000004888 barrier function Effects 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 3
- 238000011084 recovery Methods 0.000 abstract description 15
- 238000002955 isolation Methods 0.000 abstract description 10
- 238000000034 method Methods 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 10
- 230000000630 rising effect Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910001385 heavy metal Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7804—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode
- H01L29/7805—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode in antiparallel, e.g. freewheel diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野コ
本発明は、早い逆回復時間（ｔ ｒｒ）を維持する内蔵
ダイオードを備えた縦型電界効果トランジスタに関する
。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to vertical field effect transistors with built-in diodes that maintain fast reverse recovery times (trr).
［従来の技術］
この種の従来の縦型電界効果トランジスタの構造の一部
を第７図に示す。[Prior Art] A part of the structure of a conventional vertical field effect transistor of this type is shown in FIG.
この縦型電界効果トランジスタは、Ｎ導電型基板１上に
同−導１Ｂ型で不純物濃度がＮ導電型基板１より低い第
２のＮ導電型層２を有し、この第２のＮ導電型Ｍ２中に
、その接合面を一方の主表面に露出するＰ導電型領域３
が自己分離領域として形成されている。このＰ導電型領
域３の中央部は図示のように深い拡散層となっている。This vertical field effect transistor has a second N conductivity type layer 2 on an N conductivity type substrate 1, which has the same conductivity as 1B type and has an impurity concentration lower than that of the N conductivity type substrate 1. In M2, a P conductivity type region 3 whose bonding surface is exposed on one main surface
is formed as a self-isolated area. The central portion of this P conductivity type region 3 is a deep diffusion layer as shown in the figure.
さらにこのＰ導電型領域３内であって、かつ、その接合
部が１ｉｆｌ記一方の主表面に露出する第３のＮ導電型
領域４が形成されている。また、自己分離領域である眞
記Ｐ導電型領域３の表面には、絶縁Ｎ５を介してゲート
電極６が設けられている。Further, a third N-conductivity type region 4 is formed within this P-conductivity type region 3 and having a junction thereof exposed on one main surface. Furthermore, a gate electrode 6 is provided on the surface of the P conductivity type region 3, which is a self-isolation region, with an insulation N5 interposed therebetween.
前記第３のＮ導電型領域４とＰ導電型領域３とを全面的
に覆う金属層７で短絡したソース電極８を有し、また、
前記Ｎ導電型基板１の主表面と反対側となる主表面には
ドレイン電極９を有する。It has a source electrode 8 short-circuited by a metal layer 7 that completely covers the third N conductivity type region 4 and P conductivity type region 3, and
A drain electrode 9 is provided on the main surface opposite to the main surface of the N-conductivity type substrate 1 .
上記の構造の縦型電界効果トランジスタは、自己分離領
域としてのＰｉｎｔ型領域３と第２のＮ導電型層２との
間に形成されるＰＮ接合型ダイオード１０を上記ドレイ
ンｆｆｉ＋ｆｆ９−ソース電極８間に並列に内蔵した構
造となり、これを等価回路的に示すと第８図のようにな
る。The vertical field effect transistor having the above structure has a PN junction diode 10 formed between the Pint type region 3 as a self-isolation region and the second N conductivity type layer 2 between the drain ffi+ff9 and the source electrode 8. The structure is built in parallel with the circuit, and the equivalent circuit diagram of this is shown in FIG.
ところで、上記のような縦型電界効果トランジスタを１
例えば第９図に示すようなブリッジ型インバータ回路等
に用いると、縦型電界効果トランジスタＱ、、Ｑ２．Ｑ
３およびＱ４に流れる電流経路の種類は、Ａ、１３およ
びＣの３種類となる。このうち、電流経路Ａ、Ｂでは、
縦型電界効果トランジスタＱ、、Ｑ４およびＱ ３−
Ｑ ２には順方向電流が流れているが、電流経路Ｃでは
、縦型電界効果トランジスタＱ２を通る電流は逆向きと
なる。このことは当３Ｍ トランジスタＱ２に内蔵され
たフライホイールダイオードＦＤ２中を電流が流れるこ
とになり、このトランジスタＱ２の部分には電流が流九
でいないことを意味してしている。By the way, if the vertical field effect transistor as mentioned above is
For example, when used in a bridge type inverter circuit as shown in FIG. 9, vertical field effect transistors Q, , Q2 . Q
There are three types of current paths flowing through Q3 and Q4: A, 13, and C. Among these, in current paths A and B,
Vertical field effect transistors Q, , Q4 and Q3-
A forward current is flowing through Q2, but in current path C, the current passing through vertical field effect transistor Q2 is in the opposite direction. This means that current flows through the flywheel diode FD2 built into the 3M transistor Q2, and no current flows through the transistor Q2.
次に、縦型電界効果トランジスタＱ、〜Ｑ４のゲート電
極Ｇ１−０４に、図示しない制御回路から別の電流経路
、例えば電流経路Ｂとなるような信号を与えると、縦型
電界効果トランジスタＱ２は、オフ状態からオン状態に
変わるが、この時のスイッチ、ング時聞は、主として縦
型電界効果トランジスタＱ２に内蔵されたフライホイー
ルダイオードＦＤ２の逆回復時間（ｔ、 ｒｒ）に左右
されている。Next, when a signal is applied from a control circuit (not shown) to the gate electrode G1-04 of the vertical field effect transistors Q, ~Q4 to create another current path, for example, current path B, the vertical field effect transistor Q2 , the switching time changes from the off state to the on state, and the switching time at this time mainly depends on the reverse recovery time (t, rr) of the flywheel diode FD2 built in the vertical field effect transistor Q2.
その理由は、同じ大きさの電流に対し、ユニポーラ型素
子として動作する縦型電界効果トランジスタの部分と、
バイパーラ素子として動作するＰＮ接合ダイオードの部
分とでは、応答時間に約３〜４倍の差があることに起因
している。例えば縦型電界効果トランジスタの部分のタ
ーンオンタイムおよびターンオフタイムが約２００〜３
００ ｎ５ｃｃであるのに対し、ＰＮ接合ダイオードの
逆回復時ｒＩｊＪ（ｔｒ、）は、約１ｔ ０ＯＯｎｓｅ
ｃと長いのが一般的であるためである。The reason is that the vertical field effect transistor operates as a unipolar element for the same amount of current;
This is due to the fact that there is a difference of approximately 3 to 4 times in response time between the PN junction diode portion that operates as a bipolar element. For example, the turn-on time and turn-off time of the vertical field effect transistor part are approximately 200 to 3
00n5cc, whereas rIjJ(tr,) during reverse recovery of a PN junction diode is approximately 1t0OOnse
This is because it is generally long.
上記のような内蔵フライホイールダイオードの逆回復時
間（ｔ ｒｒ）は、スイッチング周波数が高くなるにし
たがい、ｔｒｒ時間内の損失が顕著となる。すなわち＋
ｔｒｒ時１ｆｌｊ内はブリッジ回路の上下で素子が
短絡されているので、その時消費される損失がより大き
いものと考えられる。また、−数的には逆回復時間ｔｒ
ｒは、素子耐圧が高くなるに従い、より低濃度で、かつ
、より厚いエピタキシャル層を使用することから、その
エピタキシャル層中のキャリアのライフタイムが長くな
り、より長い逆回復時間となる傾向がある。したがって
、高耐圧素子はどその影響はさらに大きくになる。Regarding the reverse recovery time (trr) of the built-in flywheel diode as described above, as the switching frequency becomes higher, the loss within the trr time becomes more significant. That is +
Since the elements are short-circuited at the top and bottom of the bridge circuit within 1 flj at the time of trr, it is considered that the loss consumed at that time is larger. Also, -numerically, the reverse recovery time tr
As the device breakdown voltage increases, r is used at a lower concentration and a thicker epitaxial layer, which tends to lengthen the lifetime of carriers in the epitaxial layer and result in a longer reverse recovery time. . Therefore, the influence of high voltage elements becomes even greater.
［発明が解決しようとする課題］
上記のように構成された従来の縦型電界効果トランジス
タに対し、その不都合を補うため、素子製作上あるいは
回路技術上での対策が種々ある。[Problems to be Solved by the Invention] In order to compensate for the disadvantages of the conventional vertical field effect transistor configured as described above, there are various measures in terms of device manufacturing or circuit technology.
例えば、素子製作上として、内蔵フライホイールダイオ
ード中の逆回復時間（１，、）を小さくするために、ラ
イフタイムキラーとなる重金属を公知の方法でドープさ
せたり、電子線、中性子線等を照射して結晶中にキャリ
アトラップを形成する方法等が採用されている。For example, in device manufacturing, in order to reduce the reverse recovery time (1,,) in the built-in flywheel diode, heavy metals that act as lifetime killers may be doped using known methods, or irradiation with electron beams, neutron beams, etc. A method has been adopted in which carrier traps are formed in the crystal.
しかしながら、これらの方法では、例えばしきいイ］α
電圧（Ｖい）の制御が困難になったり、オン抵抗（ＲＯ
Ｍ）が高くなる傾向がある等の縦型電界効果トランジス
タ自体の特性を損なう危険性があるという解決すべき課
題があった。However, in these methods, for example, the threshold
It may become difficult to control the voltage (V), or the on-resistance (RO) may become difficult to control.
There is a problem to be solved that there is a risk of damaging the characteristics of the vertical field effect transistor itself, such as the tendency for M) to become high.
また、回路技術上の対策としては、例えば第１０図に示
すように、フライホイールダイオードＦＤに、外付けの
ショットキーバリヤダイオードＳＢＤを直列に接続し、
ファースト・リカバリー・ダイオードＦＲＤを縦型電界
効果トランジスタのソースＳ−ドレイン９間に並列に付
加して電流経路を強制的にａからｂに変更する方法も考
えられている。In addition, as a countermeasure in terms of circuit technology, for example, as shown in Fig. 10, an external Schottky barrier diode SBD is connected in series to the flywheel diode FD.
A method of forcibly changing the current path from a to b by adding a fast recovery diode FRD in parallel between the source S and drain 9 of the vertical field effect transistor is also being considered.
しかしながら、上記の方法では部品点数の増大を招来さ
せること、また、図示の電流経路Ｃで示すように、順方
向導通時のショットキーバリャダイオードＳＢＤによる
順電圧損失を招来させること等で改善策としてはさほど
得策ではないという末だ解決すべき課題があった。However, the above method causes an increase in the number of parts, and as shown by current path C in the figure, causes forward voltage loss due to the Schottky barrier diode SBD during forward conduction. However, there were issues that needed to be resolved.
［発明の目的コ
本発明は、上記のような各課題を解決するためになされ
たもので、何ら従来の製法に追加の工程を設けることな
く、また、素子の性能を損なう危険性もなく、縦型電界
効果トランジスタに内蔵されたフライホイールダイオー
ドの逆回復時間（ｔｒｒ）を短縮し得る構造を備えた縦
型電界効果トランジスタを提供することを目的とする。[Purpose of the Invention] The present invention has been made to solve the above-mentioned problems, and can be achieved without adding any additional steps to the conventional manufacturing method and without risk of impairing the performance of the device. An object of the present invention is to provide a vertical field effect transistor having a structure capable of shortening the reverse recovery time (trr) of a flywheel diode built into the vertical field effect transistor.
ＮｊｌＴｊＪ点を解決するための手段］本発明の縦型電
界効果トランジスタは、自己分離領域としてのＰ導電型
領域の中心部を貫くように、第２のＮ導電型層をＮ導電
型基板の一方の主表面に露出させてソース電極と接する
ようにし、ショトキ−バリアダイオード領域を形成した
ものである。Means for solving the NjlTjJ point] In the vertical field effect transistor of the present invention, the second N-conductivity type layer is formed on one side of the N-conductivity type substrate so as to penetrate through the center of the P-conductivity type region as a self-isolation region. A Schottky barrier diode region is formed by exposing the main surface of the diode to be in contact with the source electrode.
［作用コ
本発明の縦型電界効果トランジスタは、ドレイン電極−
ソース１１を極間に、フライホイールダイオードを残し
たままでショトキ−バリアダイオードを並列接続した構
造となる。従って、自己分離領域を貫くようにして形成
されたショトキ−バリアダイオードの面積や形状をフラ
イホイールダイオードとの関係で適宜選択することで、
フライホイールダイオードの順方向立ち上がり電圧をシ
ョトキ−バリアダイオードの順方向立ち上がり電圧より
も高くする。かかる関係を有する場合に、縦型電界効果
トランジスタのソース電極−ドレイン電極間に流れるダ
イオード電流は、ショトキ−バリアダイオード中を優先
して流れることになり、内蔵ダイオードの逆回復時間（
Ｌｒｒ）を短縮することができる。[Function] The vertical field effect transistor of the present invention has a drain electrode
The structure is such that Schottky barrier diodes are connected in parallel with the source 11 between the poles and the flywheel diode remains. Therefore, by appropriately selecting the area and shape of the Schottky barrier diode formed to penetrate the self-isolation region in relation to the flywheel diode,
The forward rising voltage of the flywheel diode is made higher than the forward rising voltage of the Schottky barrier diode. When such a relationship exists, the diode current flowing between the source electrode and the drain electrode of the vertical field effect transistor will preferentially flow through the Schottky barrier diode, and the reverse recovery time of the built-in diode (
Lrr) can be shortened.
［実施例］ 以下に、本発明の実施例を図を参照して説明する。[Example] Embodiments of the present invention will be described below with reference to the drawings.
第１図は本発明の実施例を示す縦型電界効果トランジス
タの概略構成図である。 図において、Ｎ′導電型基板
１１上に、同一導電型で不純物濃度がＮ１導電型基板１
１より低い第２のＮ−導電型ＰＩＪ １２が、エピタキ
シャル成長により形成されている。この第２のＮ−導電
型ＮＪ１２中に、接合部の端部を、前記基板１１の一方
の主表面に露出するＰ導電型領域１３が選択的に形成さ
れるが、この部分が従来の縦型電界効果トランジスタと
大きくことなる。すなわち、この自己分離領域としての
Ｐ導電型領域１３は、図示の点線２０からも明らかなよ
うに、従来では存在した中心部の深い■〕導電型拡散層
１３は取り除かれている。換言すれば、かかる自己分離
領域の中心部をＮ−導電型層１２が貫通し、基板表面ま
で露出している。そしてソース電極１８を形成すべく設
けられたアルミニウム金属等からなる金属層１７と接し
、その界面にショトキ−バリアダイオード（以下、ＳＢ
Ｄと略記）２１を形成している。この５ＢＤ２１は、図
示の記号で示したように金、ｃＩ１層１７側が５ＢＤ２
１のアノード側に、第２のＮ導電型層１２がカソード側
に対応している。FIG. 1 is a schematic diagram of a vertical field effect transistor showing an embodiment of the present invention. In the figure, a substrate 1 of conductivity type N1 having the same conductivity type and an impurity concentration is placed on a substrate 11 of conductivity type N'.
A second N-conductivity type PIJ 12 of less than 1 is formed by epitaxial growth. In this second N-conductivity type NJ 12, a P-conductivity type region 13 is selectively formed in which the end of the bonding portion is exposed on one main surface of the substrate 11, but this portion is different from the conventional vertical It is significantly different from the type field effect transistor. That is, in the P conductivity type region 13 serving as the self-isolation region, as is clear from the dotted line 20 in the figure, the deep central conductivity type diffusion layer 13 that existed conventionally has been removed. In other words, the N-conductivity type layer 12 penetrates through the center of the self-isolation region and is exposed to the substrate surface. It is in contact with a metal layer 17 made of aluminum metal or the like provided to form a source electrode 18, and a Schottky barrier diode (hereinafter referred to as SB) is connected to the interface thereof.
Abbreviated as D) 21 is formed. This 5BD21 is made of gold, and the cI1 layer 17 side is 5BD2 as shown by the symbol in the figure.
The second N conductivity type layer 12 corresponds to the anode side of the first layer 1 and the cathode side.
上記のように、自己分離領域の中心部に５ＢＩ）２１を
形成してもこの５ＢＤ２１の外側周辺を囲むように、Ｐ
Ｎ接合ダイオードＦＤが残存していることになる。As mentioned above, even if 5BI) 21 is formed in the center of the self-isolation area, P
This means that the N-junction diode FD remains.
次に、第２図に上記実施例の変形例を示す。この変形例
を第７図の従来型と比較すると、深いＰ導電型領域１３
ａは、一部に残しているが、その中心部は第２のＮ導電
型層１２が基板表面にまで露出し、上記実施例と同様の
構成となっている。Next, FIG. 2 shows a modification of the above embodiment. Comparing this modification with the conventional type shown in FIG.
Although part a is left, the second N-conductivity type layer 12 is exposed to the substrate surface in the central part, and has the same structure as the above embodiment.
なお、第２図において、第１図と同一の構成部分には同
一符号を付し、その詳しい説明は省略する。In FIG. 2, the same components as in FIG. 1 are given the same reference numerals, and detailed explanation thereof will be omitted.
さて、上記構造を等価回路的に示すと、第３図のように
なる。この第３図と従来構造の第８図と比較すると、第
３図では縦型電界効果トランジスタのソース電極１８と
ドレイン電極１９との間に、５ＢＤ２１が並列接続され
、かつ、鎖線で示したように、ＰＮ接合型ダイオード（
以下、ＦＤと略記）１０が残存した構造となっている。Now, the above structure is shown in an equivalent circuit as shown in FIG. 3. Comparing this Fig. 3 with Fig. 8 of the conventional structure, in Fig. 3, 5BD21 is connected in parallel between the source electrode 18 and the drain electrode 19 of the vertical field effect transistor, and as shown by the chain line. , a PN junction diode (
Hereinafter, it is a structure in which 10 (abbreviated as FD) remains.
ところで、これら５ＢＤ２１およびＦＤＩＯの２つの内
蔵型ダイオードの順方向電流特性は、第４図に示すよう
になる。図中、Ａ、Ａ’は５ＢＤ２１の順方向電流特性
曲線、ＢはＦＤＩＯの順方向電流特性曲線を示している
。また、横軸に順方向電圧（Ｖ）、縦軸に電流密度（Ｉ
）を採っである。この図から明らかのように、５ＢＤ２
Ｌの面積、形状をＦＤＩＯに対して適宜選択することに
より５ＢＤ２１の立ち上がり電圧■いとＦＤＩＯの立ち
上がり電圧■８との関係を■８≦Ｖ８に維持することが
可能となる。ＶＡ≦ｖ８の関係が維持されている間は、
第３図のソース電極１８からドレイン電極１９に流れる
ダイオード電流は、ＦＤＬＯよりもＳ Ｉ３ Ｄ ２１
中を優先して流れる。この場合、５ＢＤ２１は多数キャ
リア素子であるため、ＦＤ １０の逆回復時間（ｔｒｒ
）よりも短いし、ｒを有することになる。また、自己分
離領域である■〕導電型領域１３の中心部にＳ Ｂ Ｄ
２１が設けられているので、ＦＤＩＯの実効素子領域
面積が小さくなる。このため、ＦＤＩＯ中の逆回復時の
電荷総量（Ｑｒｒ）が小さくなり、その分、５ＢＤ２Ｌ
とＦＤＩＯとを合わせた内蔵ダイオード並列接続体とし
てのＩ−ｒｒが短縮されることになる。By the way, the forward current characteristics of these two built-in diodes, 5BD21 and FDIO, are as shown in FIG. In the figure, A and A' indicate the forward current characteristic curve of 5BD21, and B indicates the forward current characteristic curve of FDIO. Also, the horizontal axis is the forward voltage (V), and the vertical axis is the current density (I
) is taken. As is clear from this figure, 5BD2
By appropriately selecting the area and shape of L with respect to FDIO, it is possible to maintain the relationship between the rising voltage (2) of the 5BD21 and the rising voltage (2) 8 of FDIO to be 8≦V8. While the relationship VA≦v8 is maintained,
The diode current flowing from the source electrode 18 to the drain electrode 19 in FIG.
Flows with priority given to the inside. In this case, since 5BD21 is a majority carrier element, the reverse recovery time (trr
) and has r. In addition, in the center of the conductivity type region 13, which is a self-separation region
21, the effective element area of the FDIO becomes smaller. Therefore, the total amount of charge (Qrr) during reverse recovery during FDIO becomes smaller, and 5BD2L
I-rr as a built-in diode parallel connection body including FDIO and FDIO is shortened.
ところで、上記のことは、５ＢＤ２１の実用的な耐圧範
囲（６０〜２００ ｖ）以下での場合であり、これをさ
らに耐圧の高いＳ Ｂ Ｄ ２１に設計すると、第４図
の点線で示した順方向電流特性曲線Ａ′となる。かかる
場合に、立ち上がり電圧はＶ侃Ｖ８であるため、もはや
上記■９≦ＶＢの関係は成立しなくなり、Ｌｒｒ短縮の
効果が得られなくなる。したがって、５ＢＤ２１の耐圧
範囲を、上記関係を維持する範囲に設計することは！Ｆ
要なことである。By the way, the above is the case below the practical breakdown voltage range (60 to 200 V) of 5BD21, and if this is designed into SBD21 with an even higher breakdown voltage, the order shown by the dotted line in Figure 4 will be achieved. The directional current characteristic curve becomes A'. In this case, since the rising voltage is from V to V8, the above relationship (19≦VB) no longer holds true, and the effect of reducing Lrr can no longer be obtained. Therefore, it is important to design the withstand voltage range of 5BD21 to a range that maintains the above relationship! F
This is important.
次に、上記本発明の構造を平面パターンとして表わした
ものを第５図および第６図に示す。Next, FIGS. 5 and 6 show the structure of the present invention expressed as a plane pattern.
このうち、第５図は丸型セル２２を六角形状に配置した
ものであり、第６図は正方形セル２３を正方形状に配置
したものである。いずれも自己分離領域としての１）導
電型領域の中心部に、縦型電界効果トランジスタに内蔵
されたＳ Ｉ３ Ｄ ２１が存在する。また、このＳ
Ｂ Ｄ ２ ］の周辺部にそれぞれＦＤＩＯがいずれの
場合も残存している。Of these, FIG. 5 shows round cells 22 arranged in a hexagonal shape, and FIG. 6 shows square cells 23 arranged in a square shape. In both cases, the S I3 D 21 built into the vertical field effect transistor exists in the center of the 1) conductivity type region serving as the self-isolation region. Also, this S
BD 2 ], FDIO remains in each case.
なお、上記＊造の製作工程は、特に述べなかったが、従
来から公知の選択拡散技術によって容易に実現すること
ができる。ただ、ソース電極としてのオーミック性接触
を維持しながら第２のＮ導電型層２の表面に５ＢＤ２１
を形成するという両者を成立させる実用的な熱処理条件
が存在することは言うまでもない。Incidentally, although the manufacturing process of the * structure described above was not specifically described, it can be easily realized by conventionally known selective diffusion technology. However, while maintaining ohmic contact as a source electrode, 5BD21 is added to the surface of the second N conductivity type layer 2.
It goes without saying that there are practical heat treatment conditions that satisfy both conditions.
［発明の効果コ
以上のように、本発明によれば、自己分離領域としての
Ｐ導電型領域の中心部を貫くように、第２のＮ導電型層
をＮ導電型基板の一方の主表面に露出させてソース電極
と接するようにし、かかる部分にショトキ−バリアダイ
オード領域を形成したので、縦型電界効果トランジスタ
のソース電極−ドレイン電極間に流れるダイオード電流
が、ＰＮ接合型ダイオードよりもショトキ−バリアダイ
オード中を優先して流れ、逆回復時間Ｄｒｒ）を短縮す
ることができるなどの優れた効果がある。[Effects of the Invention] As described above, according to the present invention, the second N conductivity type layer is formed on one main surface of the N conductivity type substrate so as to penetrate through the center of the P conductivity type region serving as the self-isolation region. Since the Schottky barrier diode region is formed in this region, the diode current flowing between the source electrode and the drain electrode of the vertical field effect transistor is more Schottky than that of a PN junction diode. It has excellent effects such as being able to preferentially flow through the barrier diode and shorten the reverse recovery time (Drr).
第１図および第２図は本発明の実施例である縦型電界効
果トランジスタの構成図、第３図はその等価回路図、第
４図は縦型１ｕ界効果トランジスタに内蔵されるショト
キ−バリアダイオードとＰＮ接合型ダイオードの順方向
特性曲線図、第５図および第６図は上記本発明の縦？ｆ
、１１ヒ界効果トランジスタの平面構造図、第７図は従
来の縦’ｆ！、ｉｎ界効果トランジスタの構成図、第８
図はその等価回路図、第９図は上記従来の縦型電界効果
トランジスタを使用して製作したブリッジ型インバータ
回路図、第１０図は従来の縦型電界効果トランジスタの
不都合を補うための回路図である。
１０・・・ＰＮ接合型ダイオード、１１・・・Ｎ導電型
基板、】２・・・第２のＮ導電型層へｉ、１３・・・Ｐ
導電型領域（自己分離領域）、１４・・・第３のＮ導電
型Ｊψ、１５・・・絶縁層、１６・・・ゲート電極、１
７・・・金属層、１８・・・ソース電極、１９・・・ド
レイン電極、２１・・・ショトキ−バリアダイオード、
ＦＤ・・・Ｉ） Ｎ接合型ダイオードFigures 1 and 2 are block diagrams of a vertical field effect transistor that is an embodiment of the present invention, Figure 3 is its equivalent circuit diagram, and Figure 4 is a Schottky barrier built in the vertical 1u field effect transistor. The forward characteristic curve diagrams of the diode and the PN junction diode, FIGS. 5 and 6, are the longitudinal characteristics of the present invention. f
, 11 A planar structural diagram of a field effect transistor, FIG. 7 is a conventional vertical 'f! , Block diagram of in-field effect transistor, No. 8
The figure shows its equivalent circuit diagram, Figure 9 is a circuit diagram of a bridge type inverter manufactured using the conventional vertical field effect transistor mentioned above, and Figure 10 is a circuit diagram to compensate for the disadvantages of the conventional vertical field effect transistor. It is. 10...PN junction diode, 11...N conductivity type substrate, ]2...i to second N conductivity type layer, 13...P
Conductivity type region (self-separation region), 14... Third N conductivity type Jψ, 15... Insulating layer, 16... Gate electrode, 1
7... Metal layer, 18... Source electrode, 19... Drain electrode, 21... Schottky barrier diode,
FD...I) N junction diode
Claims (1)
型基板より低い第２のＮ導電型層と、この第２のＮ導電
型層中に、接合部の端部が前記Ｎ導電型基板の一方の主
表面に露出するＰ導電型領域と、このＰ導電型領域中に
設けられ、接合部の端部が前記一方の主表面に露出する
第３のＮ導電型領域と、前記Ｐ導電型領域の表面に絶縁
層を介して形成したゲート電極と、前記第３のＮ導電型
領域と前記Ｐ導電型領域とを金属層により短絡して形成
したソース電極と、前記Ｎ導電型基板の主表面と反対側
となる主表面に形成したドレイン電極とを有する縦型電
界効果トランジスタにおいて、前記Ｐ導電型領域の中心
部を貫通するように前記第２のＮ導電型層を設け、その
表面を前記一方の主表面に露出させ、前記ソース電極と
接触させてショトキーバリアダイオード領域を形成した
ことを特徴とする縦型電界効果トランジスタ。A second N conductivity type layer having the same conductivity type and lower impurity concentration than the N conductivity type substrate is formed on the N conductivity type substrate; a P conductivity type region exposed on one main surface of the substrate; a third N conductivity type region provided in this P conductivity type region and having an end of a joint portion exposed on the one main surface; a gate electrode formed on the surface of the conductivity type region via an insulating layer; a source electrode formed by short-circuiting the third N conductivity type region and the P conductivity type region with a metal layer; and the N conductivity type substrate. In a vertical field effect transistor having a main surface and a drain electrode formed on a main surface opposite to the main surface, the second N conductivity type layer is provided so as to penetrate through the center of the P conductivity type region; A vertical field effect transistor, wherein a Schottky barrier diode region is formed by exposing a surface to the one main surface and contacting the source electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1247999A JPH03110867A (en) | 1989-09-26 | 1989-09-26 | Vertical field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1247999A JPH03110867A (en) | 1989-09-26 | 1989-09-26 | Vertical field-effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03110867A true JPH03110867A (en) | 1991-05-10 |
Family
ID=17171686
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1247999A Pending JPH03110867A (en) | 1989-09-26 | 1989-09-26 | Vertical field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03110867A (en) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002203967A (en) * | 2000-10-23 | 2002-07-19 | Matsushita Electric Ind Co Ltd | Semiconductor element |
| JP2003017701A (en) * | 2001-07-04 | 2003-01-17 | Denso Corp | Semiconductor device |
| JP2003526923A (en) * | 2000-02-24 | 2003-09-09 | ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング | Monolithic integrated semiconductor device |
| WO2003067665A3 (en) * | 2002-02-02 | 2003-11-13 | Koninkl Philips Electronics Nv | Cellular mosfet devices and their manufacture |
| JP2006024690A (en) * | 2004-07-07 | 2006-01-26 | Toshiba Corp | Semiconductor device for electric power |
| US7126169B2 (en) | 2000-10-23 | 2006-10-24 | Matsushita Electric Industrial Co., Ltd. | Semiconductor element |
| WO2006114424A2 (en) * | 2005-04-28 | 2006-11-02 | Siemens Aktiengesellschaft | Controllable semiconductor diode, electronic component and indirect voltage converter |
| JP2011067051A (en) * | 2009-09-18 | 2011-03-31 | Sharp Corp | Inverter, and electrical apparatus and solar power generator employing the same |
| JP2012049562A (en) * | 2011-11-04 | 2012-03-08 | Renesas Electronics Corp | Semiconductor device |
| WO2012056720A1 (en) * | 2010-10-29 | 2012-05-03 | パナソニック株式会社 | Inverter |
| US8350549B2 (en) | 2010-10-29 | 2013-01-08 | Panasonic Corporation | Converter with switches having a diode region that is unipolar-conductive only in the reverse direction |
| WO2013031212A1 (en) * | 2011-08-29 | 2013-03-07 | 次世代パワーデバイス技術研究組合 | Bidirectional element, bidirectional element circuit, and power converting apparatus |
| WO2013177552A1 (en) * | 2012-05-24 | 2013-11-28 | Microsemi Corporation | Monolithically integrated sic mosfet and schottky barrier diode |
-
1989
- 1989-09-26 JP JP1247999A patent/JPH03110867A/en active Pending
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003526923A (en) * | 2000-02-24 | 2003-09-09 | ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング | Monolithic integrated semiconductor device |
| JP2002203967A (en) * | 2000-10-23 | 2002-07-19 | Matsushita Electric Ind Co Ltd | Semiconductor element |
| US7126169B2 (en) | 2000-10-23 | 2006-10-24 | Matsushita Electric Industrial Co., Ltd. | Semiconductor element |
| JP2003017701A (en) * | 2001-07-04 | 2003-01-17 | Denso Corp | Semiconductor device |
| WO2003067665A3 (en) * | 2002-02-02 | 2003-11-13 | Koninkl Philips Electronics Nv | Cellular mosfet devices and their manufacture |
| JP2006024690A (en) * | 2004-07-07 | 2006-01-26 | Toshiba Corp | Semiconductor device for electric power |
| WO2006114424A2 (en) * | 2005-04-28 | 2006-11-02 | Siemens Aktiengesellschaft | Controllable semiconductor diode, electronic component and indirect voltage converter |
| WO2006114424A3 (en) * | 2005-04-28 | 2007-03-01 | Siemens Ag | Controllable semiconductor diode, electronic component and indirect voltage converter |
| JP2011067051A (en) * | 2009-09-18 | 2011-03-31 | Sharp Corp | Inverter, and electrical apparatus and solar power generator employing the same |
| WO2012056720A1 (en) * | 2010-10-29 | 2012-05-03 | パナソニック株式会社 | Inverter |
| US8350549B2 (en) | 2010-10-29 | 2013-01-08 | Panasonic Corporation | Converter with switches having a diode region that is unipolar-conductive only in the reverse direction |
| US8693226B2 (en) | 2010-10-29 | 2014-04-08 | Panasonic Corporation | Synchronous rectification type inverter |
| WO2013031212A1 (en) * | 2011-08-29 | 2013-03-07 | 次世代パワーデバイス技術研究組合 | Bidirectional element, bidirectional element circuit, and power converting apparatus |
| JP2012049562A (en) * | 2011-11-04 | 2012-03-08 | Renesas Electronics Corp | Semiconductor device |
| WO2013177552A1 (en) * | 2012-05-24 | 2013-11-28 | Microsemi Corporation | Monolithically integrated sic mosfet and schottky barrier diode |
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