JPH03104408A - Power amplifier - Google Patents
Power amplifierInfo
- Publication number
- JPH03104408A JPH03104408A JP1243216A JP24321689A JPH03104408A JP H03104408 A JPH03104408 A JP H03104408A JP 1243216 A JP1243216 A JP 1243216A JP 24321689 A JP24321689 A JP 24321689A JP H03104408 A JPH03104408 A JP H03104408A
- Authority
- JP
- Japan
- Prior art keywords
- class
- output
- amplifier
- power supply
- stage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010754 BS 2869 Class F Substances 0.000 claims description 9
- 230000002542 deteriorative effect Effects 0.000 abstract 1
- 230000003321 amplification Effects 0.000 description 19
- 238000003199 nucleic acid amplification method Methods 0.000 description 19
- 238000010586 diagram Methods 0.000 description 6
- 230000005540 biological transmission Effects 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/211—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0211—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the supply voltage or current
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/20—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F2203/21—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F2203/211—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
- H03F2203/21196—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers the supply voltage of a power amplifier being switchable controlled
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Control Of Amplification And Gain Control (AREA)
- Amplifiers (AREA)
Abstract
Description
【発明の詳細な説明】
［概要］
出力を容易に増減できる電力増幅器に関し、並列接続す
る増幅器の組数を調整することにより増幅器の効率を低
下させずに可変出力の得られる電力増幅器を提供するこ
とを目的とし、ＡＢ級増幅段により駆動されるＢ級乃至
Ｆ級増幅段で構戒する電力増幅器において、前記Ｂ級乃
至Ｆ級増幅段を単位組構成とし、その複数組を互いに並
列接続し、且つ各構成単位への電源の供給を個別制御す
る制御回路を具備して構成する。[Detailed Description of the Invention] [Summary] The present invention relates to a power amplifier that can easily increase or decrease its output, and provides a power amplifier that can obtain variable output without reducing efficiency of the amplifier by adjusting the number of amplifiers connected in parallel. For the purpose of this, in a power amplifier comprising a class B to class F amplifier stage driven by a class AB amplifier stage, the class B to class F amplifier stages are configured as a unit set, and multiple sets thereof are connected in parallel with each other. , and a control circuit that individually controls the supply of power to each constituent unit.
［産業上の利用分野］
本発明は出力を容易に増減できる電力増幅器に関する．
従来、トランジスタ使用の携帯用無線機において、発信
出力を低下させる必要が生じたとき、出力段の前段の電
源電圧を低下させることが実行されている。そのため回
路の効率が悪化する欠点があった。効率を低下させずに
出力を可変とする技術を開発することが要望された。[Industrial Application Field] The present invention relates to a power amplifier whose output can be easily increased or decreased. Conventionally, in portable radio devices using transistors, when it becomes necessary to reduce the transmission output, the power supply voltage at the stage preceding the output stage is reduced. Therefore, there was a drawback that the efficiency of the circuit deteriorated. There was a desire to develop a technology that could make the output variable without reducing efficiency.
［促來の技ｆ＋Ｆｉ ］
トランジスタ使用の携帯用無線機は例えば第３図に示す
構戒となっていた。第３図において、１はＣ級増幅段で
１−１．１−２−はＦＦ，Ｔを示す。２はＡＢ級増幅段
で２−１．２−２−はＦＥＴを示し、これらはＣ級増幅
段の前段回路を構成している。３はＣ級増幅段１の出力
側整合回路で、３−１．３−２−はインダクタンス・コ
ンデンサなどを適宜接続したものである。４はＣ級増幅
段ｌとＡＢ級増幅段２との整合回路で、４−１．４−２
・一は整合回路３と同様に構成している。５はドレイン
電極の電源端子で、５−１はＣ級増幅段、５−２はＡＢ
級増幅段の電ｌｌＪＸ端子、６はゲート電極の電源端子
で６−１ ． ６−２は電源端子５と同様に符号付けし
ている。７は信号人力端子、８は信号出力端子でアンテ
ナと接続されるものを示ず。電′ｔＸ端子５，６から所
定の電圧を各増幅段１．２に印加すると、信号人力端子
７から入力された信号はＡＢ級ま曽幅段２で電圧増幅さ
れ、Ｃ級増幅段ｌで電力増幅の後、端子８に到達する。[Promoting technique f+Fi] A portable radio device using a transistor had the structure shown in FIG. 3, for example. In FIG. 3, 1 indicates a class C amplification stage, and 1-1.1-2- indicates FF and T. Reference numeral 2 denotes an AB class amplification stage, and 2-1, 2-2- denotes FETs, which constitute a pre-stage circuit of the C class amplification stage. 3 is a matching circuit on the output side of the class C amplifier stage 1, and 3-1, 3-2- are connected with inductances, capacitors, etc. as appropriate. 4 is a matching circuit between class C amplifier stage 1 and class AB amplifier stage 2, and 4-1.4-2
・1 has the same configuration as the matching circuit 3. 5 is the power supply terminal of the drain electrode, 5-1 is the class C amplifier stage, and 5-2 is AB
The power supply terminal 11JX of the class amplification stage, 6 is the power supply terminal of the gate electrode, and 6-1. 6-2 is given the same reference numeral as the power supply terminal 5. 7 is a signal input terminal, and 8 is a signal output terminal, which is not shown to be connected to the antenna. When a predetermined voltage is applied from the electric terminals 5 and 6 to each amplification stage 1.2, the signal input from the signal input terminal 7 is voltage amplified in the AB class or so width stage 2, and is amplified in the class C amplification stage l. After power amplification, it reaches terminal 8.
このとき整合回路３．４が増幅信号に対し所定の整合を
行う。At this time, matching circuit 3.4 performs predetermined matching on the amplified signal.
移動通信を行うとき、移動機は基地局（または中継局）
との間で常に略同一の電界強度で通信することが望まし
いため、移動機の出力電力を制御する必要がある。第３
図の回路構成の場合、ＡＢ級増幅段２のドレイン電源５
−２の電圧を制御することが最も簡単であるため、実用
化されている。When performing mobile communication, the mobile device is a base station (or relay station)
Since it is desirable to always communicate with the mobile device with approximately the same electric field strength, it is necessary to control the output power of the mobile device. Third
In the case of the circuit configuration shown in the figure, the drain power supply 5 of the AB class amplifier stage 2
Since it is easiest to control the voltage of -2, it has been put into practical use.
即ち、所定値の電圧のとき最大出力を発生し、電圧を低
下させると最終段の送信出力も低下する。That is, the maximum output is generated when the voltage is at a predetermined value, and when the voltage is lowered, the transmission output of the final stage also decreases.
［発明が解決しようとする課題コ
第３図の回路構戒において、整合回路３．４は通常最大
出力の場合に正常な整合がとられているように設計して
いる。若し、送信出力を低下するため、ＡＢ級増幅段２
のドレイン電極電源５−２の電圧を可変抵抗器を使用す
るなどして低下させると、整合回路から見たトランジス
タのインピーダンス値が変化する。そのため整合回路に
よる整合が崩れて折角、効率が良くなるように設計した
増幅段も総合効率は低下することとなった。[Problems to be Solved by the Invention] In the circuit configuration shown in FIG. 3, the matching circuits 3.4 are designed so that normal matching is normally achieved at maximum output. In order to reduce the transmission output, the AB class amplification stage 2
When the voltage of the drain electrode power source 5-2 is lowered by using a variable resistor or the like, the impedance value of the transistor as seen from the matching circuit changes. As a result, the overall efficiency of the amplification stage, which was designed to improve the efficiency due to the loss of matching by the matching circuit, was reduced.
本発明の目的は前述の欠点を改善し、並列接続される増
幅器の組数を調整することにより増幅器の効率を低下さ
せずに可変出力の得られる増幅器を提供することにある
。SUMMARY OF THE INVENTION An object of the present invention is to improve the above-mentioned drawbacks and to provide an amplifier that can obtain a variable output without reducing the efficiency of the amplifier by adjusting the number of amplifiers connected in parallel.
［課題を解決するための千段コ
第ｌ図は本発明の原理構戒を示す図である。第ｌ図にお
いて、１−１ ． １−２−・・はＢ級乃至Ｆ級増幅段
、３−１．３−２・・−は同増幅段の出力側整合回路、
４−１．４−２は同入力側整合回路、５は電源を示し例
えばドレイン電極の電源、８は信号出力端子、９は電源
供給の制御回路を示す。[1000 Steps for Solving the Problems] Figure 1 is a diagram showing the principle structure of the present invention. In Figure 1, 1-1. 1-2-... is a B-class to F-class amplification stage, 3-1.3-2...- is an output side matching circuit of the same amplification stage,
Reference numerals 4-1 and 4-2 refer to a matching circuit on the input side, 5 a power source, for example, a power source for a drain electrode, 8 a signal output terminal, and 9 a control circuit for power supply.
ＡＢ級増幅段により駆動されるＢ級乃至Ｆ級増幅段で構
成する電力増幅器において、本発明は下記の構成とする
。即ち、
前記Ｂ級乃至Ｆ級増幅段ｌを単位組構成とし、その複数
組１−１．１−２−を互いに並列接続し、且つ各構成単
位への電源５−１の供給を個別制御する制御回路９を具
備することで構威する。The present invention has the following configuration in a power amplifier constituted by a class B to class F amplifier stage driven by a class AB amplifier stage. That is, the B-class to F-class amplification stages 1 are configured as unit sets, and the plural sets 1-1, 1-2- are connected in parallel with each other, and the supply of power 5-1 to each component unit is individually controlled. This can be achieved by providing the control circuit 9.
［作用］
Ｂ級乃至Ｆ級電力増幅段１−１は入力側に整合回路４−
１，出力側に整合回路３−１を設けて、他の増幅段１−
２− も同様に整合回路を有するから、制御回路９を総
てオンとして電源５−１からの電圧を全増幅段に印加し
て動作させるとき、信号出力端子８に最大出力が得られ
る。次に制御回路９を制御して比較的大出力の得られる
Ｂ級乃至Ｆ級電力増幅段１−３の電源をオフとすれば、
例えば増幅段の出力は半分に減少できる。そのとき他の
増幅段は整合回路３，４のため依然として効率良く動作
し、最大出力が半減するのみである。他の増幅段に対す
る電源をオフすれば、更に出力を減少させることが出来
る。[Function] The class B to class F power amplification stage 1-1 has a matching circuit 4- on the input side.
1. A matching circuit 3-1 is provided on the output side, and the other amplifier stage 1-
2- also has a matching circuit, so when all the control circuits 9 are turned on and the voltage from the power supply 5-1 is applied to all amplification stages for operation, the maximum output is obtained at the signal output terminal 8. Next, if the control circuit 9 is controlled to turn off the power supply of the class B to class F power amplifier stage 1-3, which can obtain a relatively large output,
For example, the output of the amplifier stage can be reduced by half. At that time, the other amplifier stages still operate efficiently because of the matching circuits 3 and 4, and the maximum output is only halved. The output can be further reduced by turning off the power to the other amplifier stages.
（実施例〕 第２図は本発明の実施例の構戒を示す図である。(Example〕 FIG. 2 is a diagram showing the structure of an embodiment of the present invention.
第２図において、１−３はＣ級増幅段ＦＥＴを２個並列
接続して単位組構成とし、１−１．１−２は単一段ＦＥ
Ｔの構成である。Ｃ級増幅段の単位組は同一出力の場合
と、互いに出力を異ならせて設定する場合とがある。ま
た６はゲート電極の電源、ＩＯは電源供給の制御回路と
してのスイッチを示す。In Fig. 2, 1-3 is a unit set consisting of two class C amplification stage FETs connected in parallel, and 1-1.1-2 is a single-stage FE.
This is the configuration of T. The unit sets of class C amplifier stages may have the same output or may be set to have different outputs. Further, 6 indicates a power source for the gate electrode, and IO indicates a switch as a control circuit for power supply.
破線枠１１は枠内全体をモノリシック・マイクロＩＣと
して単一チップに構戒できることを示している。電源６
はＦ Ｅ Ｔのゲート電極をバイアスするための電源で
あり、スイソチ１０−１． １０−２． １０−３の切
換えにより深いバイアスを与えたＦＥＴは、不動作状態
となる。逆に浅いバイアスの与えられたＦＥＴは正常の
動作状態となる。そのため総てのスイッチが浅いバイア
スを与えたとき、Ｃ級増幅段も総て動作し、最大出力が
端子８に得られる。A broken line frame 11 indicates that the entire area within the frame can be constructed as a single chip as a monolithic micro IC. power supply 6
is a power supply for biasing the gate electrode of FET, and Swissochi 10-1. 10-2. The FET given a deep bias by switching 10-3 becomes inactive. On the other hand, an FET to which a shallow bias is applied is in a normal operating state. Therefore, when all the switches apply a shallow bias, all the class C amplifier stages also operate, and the maximum output is obtained at the terminal 8.
スイッチ１０−２のみを深いバイアスに切換えると、動
作中のＦＥＴが半減し出力パワーが半滅する。When only switch 10-2 is switched to deep bias, the number of active FETs is halved and the output power is halved.
更にスイッチ１０−１も深いバイアスに切換えると、出
力パワーが更に半減し当初から見てＡとなる。Furthermore, when the switch 10-1 is also switched to a deep bias, the output power is further halved and becomes A from the beginning.
最大出力から見て−３ｄＢ〜−６ｄＢの変化がなされて
いる。A change of -3 dB to -6 dB is made when viewed from the maximum output.
以上はＣ級増幅段についての説明であるが、増幅段はＣ
級以外のＢ，Ｄ．Ｅ，Ｆ級であっても同様である。The above is an explanation of the class C amplification stage, but the amplification stage is
B, D other than grade. The same applies to E and F classes.
［発明の効果］
このようにして本発明によると、Ｂ級乃至Ｆ級増幅段を
、同出力の或いは互いに出力の異なる単位組を含む複数
組の構成とし、動作電源印加をオンオフするのみで、簡
易確実に出力を変化させることが出来る。且つ各段は電
力効率が最良となるように整合回路などにより予め調整
しておくから、出力を変化させても効率が低下すること
はない。[Effects of the Invention] In this way, according to the present invention, the class B to class F amplification stages are configured into a plurality of sets including unit sets having the same output or mutually different outputs, and by simply turning on and off the application of operating power, Output can be changed easily and reliably. Moreover, since each stage is adjusted in advance using a matching circuit or the like so that the power efficiency is maximized, the efficiency does not decrease even if the output is changed.
第２図は本発明の実施例の構戊を示す図、第３図は従来
の電力増幅器の構戊を示す図である。FIG. 2 is a diagram showing the structure of an embodiment of the present invention, and FIG. 3 is a diagram showing the structure of a conventional power amplifier.
１ ． １−１．，１−２ −Ｂ級乃至Ｆ級増幅段２
． ２−Ｌ２−２ −．−Ａ Ｂ級増幅段３． ３−１
．３−２・一整合回路
４ ． ４−Ｌ４−２ ．−一整合回路５ ． ５−Ｌ
５−２−・ドレイン電極の電源６． ６−１．６−２−
・・ゲート電極の電源７一人力信号端子
８一出力信号端子
９−・制御回路
特許出噸人 富士通株式会社
代 理 人 弁理士 鈴木栄祐1. 1-1. , 1-2 - Class B to Class F amplification stage 2
．． 2-L2-2 -. -A Class B amplifier stage 3. 3-1
．． 3-2. Matching circuit 4. 4-L4-2. -1 matching circuit 5. 5-L
5-2-・Drain electrode power source 6. 6-1.6-2-
・・Gate electrode power supply 7・Power signal terminal 8・Output signal terminal 9・・Control circuit patent agent Fujitsu Limited Agent Patent attorney Eisuke Suzuki
第１図は本発明の原理構成を示す図、 本発明の原理構成図 第１凶 ６ ５ 実施例 第２図 FIG. 1 is a diagram showing the principle configuration of the present invention, Principle configuration diagram of the present invention First evil 6 5 Example Figure 2
Claims (1)
成する電力増幅器において、 前記Ｂ級乃至Ｆ級増幅段（１）を単位組構成とし、その
複数組（１−１）（１−２）・・・を互いに並列接続し
、且つ各構成単位への電源（５−１）の供給を個別制御
する制御回路（９）を具備すること を特徴とする電力増幅器。[Scope of Claims] A power amplifier comprising a class B to class F amplifier stage driven by a class AB amplifier stage, wherein the class B to class F amplifier stage (1) is configured as a unit set, and a plurality of sets (1 -1) (1-2)... are connected in parallel with each other, and a power amplifier characterized by comprising a control circuit (9) that individually controls the supply of power (5-1) to each component unit. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1243216A JPH03104408A (en) | 1989-09-19 | 1989-09-19 | Power amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1243216A JPH03104408A (en) | 1989-09-19 | 1989-09-19 | Power amplifier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03104408A true JPH03104408A (en) | 1991-05-01 |
Family
ID=17100555
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1243216A Pending JPH03104408A (en) | 1989-09-19 | 1989-09-19 | Power amplifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03104408A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5796306A (en) * | 1995-08-28 | 1998-08-18 | Nec Corporation | Wide range variable output amplifier apparatus with high efficiency |
| JP2002330030A (en) * | 2001-05-01 | 2002-11-15 | Mitsubishi Electric Corp | High-frequency integrated circuit |
| KR100651159B1 (en) * | 2002-06-01 | 2006-11-29 | 김송강 | High power amplifier |
| JP2006333060A (en) * | 2005-05-26 | 2006-12-07 | Renesas Technology Corp | High frequency power amplifier and radio communication device using the same |
| JP2007116694A (en) * | 2005-10-17 | 2007-05-10 | Korea Electronics Telecommun | Power amplifier in high-efficiency mixed mode |
| JP2008295088A (en) * | 1995-09-29 | 2008-12-04 | Panasonic Corp | Power amplifier |
| EP2302851A1 (en) * | 2009-09-29 | 2011-03-30 | Alcatel Lucent | Power supply arrangement for line termination units |
| JP2011512098A (en) * | 2008-02-08 | 2011-04-14 | クゥアルコム・インコーポレイテッド | Multiple mode power amplifier |
| WO2014170955A1 (en) * | 2013-04-16 | 2014-10-23 | 三菱電機株式会社 | Highly efficient power amplifier |
| JP2019097143A (en) * | 2017-11-17 | 2019-06-20 | 株式会社東芝 | Switched amplifier |
-
1989
- 1989-09-19 JP JP1243216A patent/JPH03104408A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5796306A (en) * | 1995-08-28 | 1998-08-18 | Nec Corporation | Wide range variable output amplifier apparatus with high efficiency |
| JP2008295088A (en) * | 1995-09-29 | 2008-12-04 | Panasonic Corp | Power amplifier |
| JP2002330030A (en) * | 2001-05-01 | 2002-11-15 | Mitsubishi Electric Corp | High-frequency integrated circuit |
| KR100651159B1 (en) * | 2002-06-01 | 2006-11-29 | 김송강 | High power amplifier |
| JP2006333060A (en) * | 2005-05-26 | 2006-12-07 | Renesas Technology Corp | High frequency power amplifier and radio communication device using the same |
| JP2007116694A (en) * | 2005-10-17 | 2007-05-10 | Korea Electronics Telecommun | Power amplifier in high-efficiency mixed mode |
| US8718582B2 (en) | 2008-02-08 | 2014-05-06 | Qualcomm Incorporated | Multi-mode power amplifiers |
| JP2011512098A (en) * | 2008-02-08 | 2011-04-14 | クゥアルコム・インコーポレイテッド | Multiple mode power amplifier |
| WO2011039063A1 (en) * | 2009-09-29 | 2011-04-07 | Alcatel Lucent | Power supply arrangement for line termination units |
| EP2302851A1 (en) * | 2009-09-29 | 2011-03-30 | Alcatel Lucent | Power supply arrangement for line termination units |
| WO2014170955A1 (en) * | 2013-04-16 | 2014-10-23 | 三菱電機株式会社 | Highly efficient power amplifier |
| JP2019097143A (en) * | 2017-11-17 | 2019-06-20 | 株式会社東芝 | Switched amplifier |
| US10547279B2 (en) | 2017-11-17 | 2020-01-28 | Kabushiki Kaisha Toshiba | Switched amplifier |
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