JPH0310230B2 - - Google Patents
Info
- Publication number
- JPH0310230B2 JPH0310230B2 JP58197085A JP19708583A JPH0310230B2 JP H0310230 B2 JPH0310230 B2 JP H0310230B2 JP 58197085 A JP58197085 A JP 58197085A JP 19708583 A JP19708583 A JP 19708583A JP H0310230 B2 JPH0310230 B2 JP H0310230B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- semiconductor device
- buried layer
- epitaxial layer
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 20
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 8
- 238000005468 ion implantation Methods 0.000 claims description 6
- 238000010894 electron beam technology Methods 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 3
- 238000000034 method Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 230000001976 improved effect Effects 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 5
- 230000003321 amplification Effects 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000003199 nucleic acid amplification method Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は、半導体装置の製造方法に関する。[Detailed description of the invention] [Technical field of invention] The present invention relates to a method for manufacturing a semiconductor device.
〔発明の技術的背景〕
従来、例えばバイポーラICとして使用される
半導体装置の製造は、第１図Ａに示す如く、先ず
Ｐ型のシリコン基板１の所定領域に選択拡散によ
りSb、As等の不純物を導入して埋込層２となる
高濃度Ｎ型領域を形成する。次いで、シリコン基
板１上にＮ型のエピタキシヤル層３をエピタキシ
ヤル成長法にて形成する。然る後、エピタキシヤ
ル層３に所定の素子を形成して半導体装置を得
る。[Technical Background of the Invention] Conventionally, in manufacturing a semiconductor device used as a bipolar IC, for example, as shown in FIG. is introduced to form a highly doped N-type region that will become the buried layer 2. Next, an N-type epitaxial layer 3 is formed on the silicon substrate 1 by an epitaxial growth method. Thereafter, predetermined elements are formed on the epitaxial layer 3 to obtain a semiconductor device.
而して、埋込層２は、表面濃度が約２×1019cm
-3、深さが3.5〜4.5μｍに設定される。このため、
従来の半導体装置の製造方法では、埋込層２の形
成の際に1250℃の温度で約80分の熱処理を必要と
する。このような高温下での高濃度拡散を行うも
のでは、埋込層２中の結晶欠陥の発生を皆無に抑
えることはほとんど不可能である。その結果発生
する結晶欠陥は、次工程でのエピタキシヤル成長
の際に結晶欠陥発生の核となり、エピタキシヤル
層３中に積層欠陥、Shallow Pit、スリツプ等を
誘起する。このため、エピタキシヤル層３に形成
された能動素子等で構成された半導体装置に、リ
ーク電流の増加、更には異常拡散によるエミツタ
ーベース短絡が起きる。
Therefore, the buried layer 2 has a surface concentration of approximately 2×10 19 cm
-3 , the depth is set to 3.5 to 4.5 μm. For this reason,
In the conventional semiconductor device manufacturing method, when forming the buried layer 2, heat treatment is required at a temperature of 1250° C. for about 80 minutes. With such a device that performs high-concentration diffusion at high temperatures, it is almost impossible to completely suppress the occurrence of crystal defects in the buried layer 2. The crystal defects generated as a result become a core of crystal defect generation during epitaxial growth in the next step, and induce stacking faults, shallow pits, slips, etc. in the epitaxial layer 3. As a result, in a semiconductor device composed of active elements and the like formed in the epitaxial layer 3, an increase in leakage current and further an emitter-base short circuit due to abnormal diffusion occur.
また、埋込層２の形成後のエピタキシヤル成長
は、通常1150〜1210℃で行われるため、埋込層２
がエピタキシヤル層３中にしみ出し、能動素子の
耐圧低下、電流増幅率等の電気特性の劣化を起こ
す問題があつた。 In addition, since epitaxial growth after the formation of the buried layer 2 is normally performed at 1150 to 1210°C, the buried layer 2
There was a problem in that this seeped into the epitaxial layer 3, causing a decrease in breakdown voltage of the active element and deterioration of electrical characteristics such as current amplification factor.
本発明は、素子特性を向上させると共に、寄生
効果の抑制を図つた半導体装置を容易に得ること
ができる半導体装置の製造方法を提供するもので
ある。
The present invention provides a method for manufacturing a semiconductor device that can easily obtain a semiconductor device that improves device characteristics and suppresses parasitic effects.
本発明は、エピタキシヤル成長層の結晶性を損
わずに高濃度埋込層を形成し、かつ能動素子領域
の結晶性を改善して、素子特性を向上させると共
に、寄生効果の抑制を図つた半導体装置を容易に
得ることができる半導体装置の製造方法である。
The present invention aims to form a highly concentrated buried layer without impairing the crystallinity of the epitaxially grown layer and improve the crystallinity of the active device region, thereby improving device characteristics and suppressing parasitic effects. This is a method for manufacturing a semiconductor device that can easily produce a semiconductor device with a high quality.
以下、本発明の実施例について図面を参照して
説明する。
Embodiments of the present invention will be described below with reference to the drawings.
先ず、第２図Ａに示す如く、例えばＰ型シリコ
ン基板〔100mmφ、（111）、ρ＝２〜６Ω・cm〕１
０上に、シリンダ型エピタキシヤル成長装置を用
いてSiH2Cl2を反応ガスとして使用し、厚さ約3μ
ｍ（ρ＝2.0Ω・cm）のＮ型エピタキシヤル層１
１を形成する。 First, as shown in FIG. 2A, for example, a P-type silicon substrate [100 mmφ, (111), ρ=2 to 6 Ω・cm] 1
0 using SiH 2 Cl 2 as a reaction gas using a cylinder type epitaxial growth apparatus to a thickness of about 3 μm.
m (ρ=2.0Ω・cm) N-type epitaxial layer 1
form 1.
次いで、同図Ｂに示す如く、P+型不純物の選
択拡散を施し、Ｎ型エピタキシヤル層１１の所定
領域にシリコン基板１０に達する素子分離拡散領
域１２を形成する。次いで、後述する埋込層１３
に達するN+領域１４を素子領域内に形成する。
然る後、硼素のイオン注入及びヒ素のイオン注入
を順次施し、素子領域内にベース領域１５及びエ
ミツタ領域１６を夫々形成する。なお、１７は、
エミツタ領域１６、ベース領域１５等の不純物領
域の形成の際にエピタキシヤル層１１の表面に形
成された酸化膜である。 Next, as shown in FIG. B, selective diffusion of P + type impurities is performed to form an element isolation diffusion region 12 reaching the silicon substrate 10 in a predetermined region of the N type epitaxial layer 11. Next, a buried layer 13 to be described later
An N + region 14 reaching 100 nm is formed in the element region.
Thereafter, boron ion implantation and arsenic ion implantation are sequentially performed to form a base region 15 and an emitter region 16 in the element region, respectively. In addition, 17 is
This is an oxide film formed on the surface of the epitaxial layer 11 when forming impurity regions such as the emitter region 16 and the base region 15.
次に、同図Ｃに示す如く、酸化膜１７を除去し
た後、例えばタンデム型高電圧イオン注入装置に
より、照射エネルギーが7MeV、ドーズ量３×
1015cm-2の条件でAs+ 75を選択的に注入し、シリ
コン基板１０とエピタキシヤル層１１間の所定領
域にN+領域１４と接続する埋込層１３を形成す
る。ここで、埋込層１３の深さ方向の形成位置
は、照射エネルギーの値によつて決定され、その
濃度はドーズ量によつて決定される。上述の照射
条件の場合、埋込層１３のピーク濃度深さは約
3μｍ、エピタキシヤル層１１の実効の厚さは約
1μｍとなる。また、寄生効果を抑制するために、
フイールド領域の少数キヤリアライフタイムを低
くして表面再結合速度を大きくする必要がある場
合には、第３図Ａに示す如く、能動素子の形成後
に保護用の酸化膜１７を残存した状態で、例えば
照射エネルギー3MeV、ドーズ量１×1014cm-2の
条件で素子全面に電子線を照射する。この電子線
照射によりフイールド領域の少数キヤリアのライ
フタイムは、100μsecオーダーから1μsecオーダー
に低下する。次いで、第３図Ｂに示す如く、酸化
膜７を除去した後、上述と同様の照射条件で
As+ 75をイオン注入し、シリコン基板１０とエピ
タキシヤル層１１間の所定領域に埋込層１３を形
成する。なお、As原子は、高エネルギーイオン
注入によつて誘起される格子振動により格子位置
（Substitutional Site）におさまるため、活性化
のための熱処理は不要である。 Next, as shown in FIG.
As + 75 is selectively implanted under the condition of 10 15 cm -2 to form a buried layer 13 connected to the N + region 14 in a predetermined region between the silicon substrate 10 and the epitaxial layer 11. Here, the formation position of the buried layer 13 in the depth direction is determined by the value of irradiation energy, and its concentration is determined by the dose amount. In the case of the above-mentioned irradiation conditions, the peak concentration depth of the buried layer 13 is approximately
3 μm, the effective thickness of the epitaxial layer 11 is approximately
It becomes 1μm. In addition, to suppress parasitic effects,
When it is necessary to increase the surface recombination rate by decreasing the minority carrier lifetime in the field region, as shown in FIG. For example, the entire surface of the device is irradiated with an electron beam under the conditions of irradiation energy of 3 MeV and dose of 1×10 14 cm −2 . Due to this electron beam irradiation, the lifetime of minority carriers in the field region decreases from the order of 100 μsec to the order of 1 μsec. Next, as shown in FIG. 3B, after removing the oxide film 7, irradiation was performed under the same irradiation conditions as described above.
As + 75 ions are implanted to form a buried layer 13 in a predetermined region between the silicon substrate 10 and the epitaxial layer 11. Note that since the As atoms settle in lattice sites (substitutional sites) due to lattice vibration induced by high-energy ion implantation, heat treatment for activation is not necessary.
然る後、第２図Ｄに示す如く、エピタキシヤル
層１１の表面に絶縁膜１８を形成し、これにN+
領域１４、ベース領域１５、エミツタ領域１６に
通じるコンタクトホールを開口する。このコンタ
クトホールを介して各の不純物領域１４，１５，
１６に接続する電極１９ａ，１９ｂ，１９ｃを形
成して半導体装置２０を得る。なお、フイールド
領域のライフタイム回復を防止するため、オーミ
ツクコンタクトを得るためのシンターは、クイツ
クアニール法により10秒程度施す。 Thereafter, as shown in FIG. 2D, an insulating film 18 is formed on the surface of the epitaxial layer 11, and N +
A contact hole communicating with the region 14, the base region 15, and the emitter region 16 is opened. Each impurity region 14, 15,
Electrodes 19a, 19b, and 19c connected to 16 are formed to obtain semiconductor device 20. In order to prevent lifetime recovery of the field region, sintering to obtain ohmic contact is performed for about 10 seconds using a quick annealing method.
このようにこの半導体装置の製造方法によれ
ば、次のような効果を有する。 As described above, this semiconductor device manufacturing method has the following effects.
(1) 埋込層１３が熱工程にさらされるのを回避で
きる。このため、埋込層１３の浮き上りが大幅
に減少し、実効エピ厚の均一性は、従来の±８
％から±３％と改善される。その結果、例えば
I2L素子（ベース深さ0.5μｍ、コレクタ深さ
0.3μｍ）の耐圧（BVCEO）歩留を従来の78％か
ら92％に向上させることができる。(1) Exposure of the buried layer 13 to a thermal process can be avoided. Therefore, the lifting of the buried layer 13 is significantly reduced, and the uniformity of the effective epitaxial thickness is improved by ±8
% to ±3%. As a result, for example
I 2 L element (base depth 0.5μm, collector depth
The yield of BV CEO (0.3μm) can be improved from 78% to 92%.
(2) 能動素子形成後に高エネルギー（MeV）の
イオン注入によつて埋込層１３を形成すること
により、高エネルギーイオンが通過した素子領
域の結晶が格子振動を起こして再配列し、結晶
性が改善される。その結果、NPNトランジス
タ（ベース深さ0.5μｍ、エミツタ深さ0.3μｍ）
のベース領域１５の少数キヤリアライフタイム
が、従来の数μsecから20μsecに向上される。そ
の結果、低コレクタ電流領域の電流増幅率
（hFE）の低下は、第４図に特性線（）にて示
す如く抑制される。なお、同図中特性線（）
は、従来方法にて得られた半導体装置のもので
ある。(2) By forming the buried layer 13 by high-energy (MeV) ion implantation after forming the active element, the crystals in the element region through which the high-energy ions have passed undergo lattice vibration and rearrange, resulting in improved crystallinity. is improved. As a result, an NPN transistor (base depth 0.5 μm, emitter depth 0.3 μm)
The minority carrier lifetime of the base region 15 is improved from the conventional several μsec to 20 μsec. As a result, the decrease in the current amplification factor (h FE ) in the low collector current region is suppressed as shown by the characteristic line () in FIG. In addition, the characteristic line () in the same figure
is a semiconductor device obtained by a conventional method.
(3) 能動素子形成後に素子全面に電子線を照射
し、その後に高エネルギーイオン注入を使つて
埋込層１３を形成することにより、フイールド
領域のライフタイムを低くし、かつ、素子領域
のライフタイムを高く制御することができる。
その結果、寄生PNPトランジスタの電流増幅
率（hFE）を従来の20〜50から１〜２程度まで
低減することができる。(3) By irradiating the entire surface of the device with an electron beam after forming the active device, and then forming the buried layer 13 using high-energy ion implantation, the lifetime of the field region can be reduced and the lifetime of the device region can be reduced. Time can be highly controlled.
As a result, the current amplification factor (h FE ) of the parasitic PNP transistor can be reduced from the conventional 20-50 to about 1-2.
以上説明した如く、本発明に係る半導体装置の
製造方法にによれば、素子特性を向上させると共
に、寄生効果の抑制を図つた半導体装置を容易に
得ることができるものである。
As described above, according to the method of manufacturing a semiconductor device according to the present invention, it is possible to easily obtain a semiconductor device in which element characteristics are improved and parasitic effects are suppressed.
第１図Ａ及び同図Ｂは、従来の半導体装置の製
造方法を示す説明図、第２図Ａ乃至同図Ｄは、本
発明方法を工程順に示す説明図、第３図Ａ及び同
図Ｂは、電子線の照射状態を示す説明図、第４図
は、低コレクタ電流領域の電流増幅率の変化を示
す特性図である。
１０……シリコン基板、１１……エピタキシヤ
ル層、１２……素子分離拡散領域、１３……埋込
層、１４……N+領域、１５……ベース領域、１
６……エミツタ領域、１７……酸化膜、１８……
絶縁膜、１９ａ，１９ｂ，１９ｃ……電極、２０
……半導体装置。
1A and 1B are explanatory diagrams showing a conventional semiconductor device manufacturing method, FIGS. 2A to 2D are explanatory diagrams showing the method of the present invention in the order of steps, and FIGS. 3A and 3B FIG. 4 is an explanatory diagram showing the electron beam irradiation state, and FIG. 4 is a characteristic diagram showing changes in the current amplification factor in the low collector current region. 10...Silicon substrate, 11...Epitaxial layer, 12...Element isolation diffusion region, 13...Buried layer, 14...N + region, 15...Base region, 1
6... Emitter region, 17... Oxide film, 18...
Insulating film, 19a, 19b, 19c...electrode, 20
...Semiconductor device.
Claims (1)
工程と、前記エピタキシヤル層に所定の能動素子
を形成する工程と、前記エピタキシヤル層及び前
記半導体基板内の所定領域に不純物を選択的にイ
オン注入して埋込層を形成する工程とを具備する
ことを特徴とする半導体装置の製造方法。 ２ 埋込層を形成する不純物の選択的イオン注入
は、能動素子の全域に電子線照射を施した後に行
なうものである特許請求の範囲第１項記載の半導
体装置の製造方法。[Claims] 1. A step of forming an epitaxial layer on a semiconductor substrate, a step of forming a predetermined active element in the epitaxial layer, and a step of doping impurities in a predetermined region in the epitaxial layer and the semiconductor substrate. 1. A method of manufacturing a semiconductor device, comprising the step of selectively implanting ions to form a buried layer. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the selective ion implantation of impurities forming the buried layer is performed after electron beam irradiation is applied to the entire area of the active element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19708583A JPS6089939A (en) | 1983-10-21 | 1983-10-21 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19708583A JPS6089939A (en) | 1983-10-21 | 1983-10-21 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6089939A JPS6089939A (en) | 1985-05-20 |
| JPH0310230B2 true JPH0310230B2 (en) | 1991-02-13 |
Family
ID=16368469
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19708583A Granted JPS6089939A (en) | 1983-10-21 | 1983-10-21 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6089939A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6386565A (en) * | 1986-09-30 | 1988-04-16 | Fuji Electric Co Ltd | Manufacture of semiconductor device |
| US6358823B1 (en) * | 2000-04-12 | 2002-03-19 | Institut Fuer Halbleiterphysik Frankfurt (Oder) Gmbh. | Method of fabricating ion implanted doping layers in semiconductor materials and integrated circuits made therefrom |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5021350A (en) * | 1973-06-27 | 1975-03-06 | ||
| JPS514978A (en) * | 1974-07-02 | 1976-01-16 | Mitsubishi Electric Corp | HANDOTAISHUSEKIKAIRONO SEISAKUHO |
| JPS5173887A (en) * | 1974-12-23 | 1976-06-26 | Fujitsu Ltd | HANDOTAISOCHINOSEIZOHOHO |
| JPS51113469A (en) * | 1975-03-31 | 1976-10-06 | Fujitsu Ltd | Manufacturing method of semiconductor device |
| JPS5693341A (en) * | 1979-12-21 | 1981-07-28 | Fujitsu Ltd | Manufacture of bipolar ic |
-
1983
- 1983-10-21 JP JP19708583A patent/JPS6089939A/en active Granted
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5021350A (en) * | 1973-06-27 | 1975-03-06 | ||
| JPS514978A (en) * | 1974-07-02 | 1976-01-16 | Mitsubishi Electric Corp | HANDOTAISHUSEKIKAIRONO SEISAKUHO |
| JPS5173887A (en) * | 1974-12-23 | 1976-06-26 | Fujitsu Ltd | HANDOTAISOCHINOSEIZOHOHO |
| JPS51113469A (en) * | 1975-03-31 | 1976-10-06 | Fujitsu Ltd | Manufacturing method of semiconductor device |
| JPS5693341A (en) * | 1979-12-21 | 1981-07-28 | Fujitsu Ltd | Manufacture of bipolar ic |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6089939A (en) | 1985-05-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20160307993A1 (en) | Semiconductor device and method of manufacturing semiconductor device | |
| JPH0147014B2 (en) | ||
| KR20000007303A (en) | Fabricating method of mos transistor | |
| US10607839B2 (en) | Method of reducing an impurity concentration in a semiconductor body | |
| JPH0469814B2 (en) | ||
| KR900005123B1 (en) | Bipolar transistor manufacturing method | |
| JPH0738102A (en) | Manufacture of high withstand voltage semiconductor device | |
| JPH0521448A (en) | Manufacture of semiconductor device | |
| JP4951872B2 (en) | Manufacturing method of semiconductor device | |
| JPH0310230B2 (en) | ||
| JP2991386B2 (en) | Method for manufacturing semiconductor device | |
| JPS6325508B2 (en) | ||
| JPS6392030A (en) | Manufacture of semiconductor device | |
| US7164186B2 (en) | Structure of semiconductor device with sinker contact region | |
| US5556793A (en) | Method of making a structure for top surface gettering of metallic impurities | |
| JP3145694B2 (en) | Semiconductor device | |
| JPH1174275A (en) | Semiconductor device and its manufacture | |
| JP3300645B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP3051088B2 (en) | Method for manufacturing extrinsic base of NPN transistor using high frequency bipolar technology | |
| JPS646537B2 (en) | ||
| JPH079929B2 (en) | Method of manufacturing integrated circuit | |
| JPH0595000A (en) | Manufacture of semiconductor device | |
| JP2735079B2 (en) | Boron doping method | |
| JPH0661234A (en) | Production of semiconductor device | |
| JPS6159723A (en) | Manufacture of semiconductor device |