JPH03101509A - Control circuit for power amplifier output signal - Google Patents
Control circuit for power amplifier output signalInfo
- Publication number
- JPH03101509A JPH03101509A JP1238656A JP23865689A JPH03101509A JP H03101509 A JPH03101509 A JP H03101509A JP 1238656 A JP1238656 A JP 1238656A JP 23865689 A JP23865689 A JP 23865689A JP H03101509 A JPH03101509 A JP H03101509A
- Authority
- JP
- Japan
- Prior art keywords
- power
- output signal
- power amplifier
- output
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims abstract description 16
- 230000000979 retarding effect Effects 0.000 abstract 1
- 238000004891 communication Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000002131 composite material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Landscapes
- Amplifiers (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野］
本発明は複数台のパワーアンプの出力信号を合成して出
力するパワーアンプ回路に関し、特に合成されたアンプ
出力信号を制御するための制御回路に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a power amplifier circuit that synthesizes and outputs output signals from a plurality of power amplifiers, and particularly relates to a control circuit for controlling the synthesized amplifier output signal. Regarding.
従来、この種のパワーアンプ回路では、複数台のパワー
アンプを分岐器と合成器を介して並列接続し、入力信号
を分岐器で分岐した上で各パワーアンプでそれぞれ増幅
し、増幅された各信号を合成器で合成して出力させるよ
うに構成されている。Conventionally, in this type of power amplifier circuit, multiple power amplifiers are connected in parallel via a splitter and a combiner, and the input signal is split by the splitter and amplified by each power amplifier. It is configured to combine signals with a combiner and output the result.
上述した従来のパワーアンプ回路では、１台以上のアン
プを残して他のアンプの電源を断した場合、または再び
電源を入力した場合に、当該パワーアンプによる利得骨
が急激に低減され、或いは増加されるため、合成出力の
レベルが急激に変化されてオーバシュート状態となり、
この種のパワーアンプ回路を通信装置の送信機等に用い
た場合には、通信エラーが発生したり、回線断になると
いう問題がある。また、電源の立上り、立下りの過程に
おいてパワーアンプがフルゲインとなり、その歪のため
にエラーが発生したり回線断になるということもある。In the conventional power amplifier circuit described above, when the power to one or more amplifiers is turned off, or when the power is turned on again, the gain of the power amplifier is suddenly reduced or increased. As a result, the level of the composite output changes rapidly, resulting in an overshoot condition.
When this type of power amplifier circuit is used in a transmitter of a communication device, etc., there are problems such as communication errors or line disconnections. In addition, the power amplifier reaches full gain during the power supply rising and falling processes, which may cause errors or line disconnections due to distortion.
本発明の目的は電源の断接時やその立ち上がり。The purpose of the present invention is to solve the problem when the power is connected or disconnected or when it starts up.
立ち下り時における出力レベルの急激な変動を防止して
、エラーの発生や回線断を防止するようにした制御回路
を提供することにある。An object of the present invention is to provide a control circuit that prevents sudden fluctuations in output level at the time of falling, thereby preventing occurrence of errors and line disconnections.
本発明のパワーアンプ出力信号制御回路は、複数台のパ
ワーアンプの出力レベルを検出する出力信号検出回路と
、検出した出力レベルに基づいて各パワーアンプの利得
を制御するレベル制御回路と、各パワーアンプの電源電
圧を検出する電源電圧検出回路と、この電源電圧検出回
路の検出信号に所要の時間遅れを生じさせる時定数回路
とを備えており、かつ前記したレベル制御回路はこの時
定数回路の出力によっても前記パワーアンプの利得を制
御し得るように構成している。The power amplifier output signal control circuit of the present invention includes an output signal detection circuit that detects the output level of a plurality of power amplifiers, a level control circuit that controls the gain of each power amplifier based on the detected output level, and a level control circuit that controls the gain of each power amplifier based on the detected output level. It is equipped with a power supply voltage detection circuit that detects the power supply voltage of the amplifier, and a time constant circuit that causes a required time delay in the detection signal of this power supply voltage detection circuit, and the level control circuit described above is provided with a time constant circuit that causes a required time delay in the detection signal of this power supply voltage detection circuit. The configuration is such that the gain of the power amplifier can also be controlled by the output.
この構成では、レベル制御回路は電源電圧の変動に伴な
い、時定数回路で設定される時定数に応じてパワーアン
プの利得を制御するため、電源断。In this configuration, the level control circuit controls the gain of the power amplifier according to the time constant set by the time constant circuit as the power supply voltage fluctuates, so the power is turned off.
接待におけるパワーアンプ出力を徐々に増減させてオー
バシュートを防止する。To prevent overshoot by gradually increasing or decreasing power amplifier output during entertainment.
次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例のブロック図である。FIG. 1 is a block diagram of one embodiment of the present invention.
入力端子１から入力する信号は分岐器２により２つの信
号に分岐され、それぞれパワーアンプ３Ａ。A signal input from an input terminal 1 is branched into two signals by a splitter 2, and each signal is sent to a power amplifier 3A.
３Ｂに入力する。そして、これらのパワーアンプ３Ａ、
３Ｂで増幅された出力信号は合成器４で合成され、出力
端子５から出力される。Enter in 3B. And these power amplifiers 3A,
The output signals amplified by 3B are combined by a combiner 4 and output from an output terminal 5.
前記各パワーアンプ３Ａ、３Ｂの出力側には、それぞれ
出力信号検出回路６Ａ、６Ｂが接続され、各出力レベル
が検出される。この検出した出力信号レベルは、それぞ
れレベル制御回路７Ａ、７Ｂに入力され、各レベル制御
回路７Ａ、７Ｂではこの出力信号レベルに基づいて、各
出力信号レベルが一定となるように前記パワーアンプ３
Ａ、３Ｂの利得を制御する。Output signal detection circuits 6A and 6B are connected to the output sides of the power amplifiers 3A and 3B, respectively, and each output level is detected. The detected output signal levels are input to the level control circuits 7A and 7B, respectively, and the level control circuits 7A and 7B control the power amplifier 3 based on the output signal levels so that each output signal level is constant.
Control the gains of A and 3B.
一方、前記パワーアンプ３Ａ、３Ｂの電源８Ａ。On the other hand, the power source 8A for the power amplifiers 3A and 3B.
８Ｂの電圧は、電源電圧検出回路９Ａ、９Ｂにより検出
され、時定数回路１０Ａ、ＩＯＢに入力される。これら
時定数回路１０Ａ、ＩＯＢは電源の断、接状態信号を所
定の時間遅延させながらレベル制御回路７Ａ、７Ｂに出
力し、この信号に基づいてレベル制御回路７Ａ、７Ｂに
よりパワーアンプ３Ａ、３Ｂの利得を徐々に変化させる
。The voltage of 8B is detected by power supply voltage detection circuits 9A and 9B, and inputted to time constant circuit 10A and IOB. These time constant circuits 10A and IOB output the power-off and connection state signals to the level control circuits 7A and 7B while delaying them for a predetermined time, and based on these signals, the level control circuits 7A and 7B control the power amplifiers 3A and 3B. Gradually change the gain.
このため、電源電圧入力時には、パワーアンプ３Ａ、３
Ｂの利得を徐々に上げ、その出力信号レベルを要求され
ているレベルまで徐々に増大させる。また、電源電圧断
時にはパワーアンプ３Ａ。Therefore, when inputting the power supply voltage, the power amplifiers 3A and 3A
Gradually increase the gain of B to gradually increase its output signal level to the required level. Also, when the power supply voltage is interrupted, the power amplifier is 3A.
３Ｂの利得を徐々に下げ、その出力信号レベルを徐々に
低下させる。したがって、電源断接時に出力レベルが急
激に変化してオーバシュートとなることが防止でき、通
信装置に利用した際のエラーの発生や、回路断を防止す
ることができる。The gain of 3B is gradually lowered, and its output signal level is gradually lowered. Therefore, it is possible to prevent the output level from rapidly changing and overshooting when the power supply is connected or disconnected, and it is possible to prevent errors from occurring or circuit breakage when used in a communication device.
なお、前記実施例では２台のパワーアンプで構成した例
を示しているが、３台以上のパワーアンプで構成された
パワーアンプ回路においても本発明を同様に適用するこ
とができる。Although the above embodiment shows an example in which the power amplifier circuit is configured with two power amplifiers, the present invention can be similarly applied to a power amplifier circuit configured with three or more power amplifiers.
以上説明したように本発明は、電源電圧の変化を検出し
、時定数回路により設定される時定数に基ツいてレベル
制御回路がパワーアンプの利得を制御するので、出力信
号レベルを徐々に増減することができ、電源の断接時に
おける出力信号レベルのオーバシュートを防止し、エラ
ーの発生や回線断を防止できる効果がある。As explained above, the present invention detects changes in the power supply voltage, and the level control circuit controls the gain of the power amplifier based on the time constant set by the time constant circuit, so the output signal level is gradually increased or decreased. This has the effect of preventing the output signal level from overshooting when the power supply is connected or disconnected, thereby preventing the occurrence of errors and line disconnections.
第１図は本発明の一実施例のブロック図である。
１・・・入力端子、２・・・分岐器、３Ａ、３Ｂ・・・
パワーアンプ、４・・・合成器、５・・・出力端子、６
Ａ、６Ｂ・・・出力信号検出回路、７Ａ、７Ｂ・・・出
力信号レベル制御回路、８Ａ、８Ｂ・・・電源、９Ａ、
９Ｂ・・・電源電圧検出回路、ＩＯＡ、ＩＯＢ・・・時
定数回路。FIG. 1 is a block diagram of one embodiment of the present invention. 1... Input terminal, 2... Branch, 3A, 3B...
Power amplifier, 4...Synthesizer, 5...Output terminal, 6
A, 6B... Output signal detection circuit, 7A, 7B... Output signal level control circuit, 8A, 8B... Power supply, 9A,
9B...Power supply voltage detection circuit, IOA, IOB...Time constant circuit.
Claims (1)
プ回路において、前記各パワーアンプの出力レベルを検
出する出力信号検出回路と、検出した出力レベルに基づ
いて各パワーアンプの利得を制御するレベル制御回路と
、前記各パワーアンプの電源電圧を検出する電源電圧検
出回路と、この電源電圧検出回路の検出信号に所要の時
間遅れを生じさせる時定数回路とを備え、前記レベル制
御回路はこの時定数回路の出力によっても前記パワーア
ンプの利得を制御し得るように構成したことを特徴とす
るパワーアンプ出力信号制御回路。1. In a power amplifier circuit that combines the outputs of multiple power amplifiers, an output signal detection circuit that detects the output level of each power amplifier, and a level control that controls the gain of each power amplifier based on the detected output level. a power supply voltage detection circuit that detects the power supply voltage of each of the power amplifiers, and a time constant circuit that causes a required time delay in the detection signal of the power supply voltage detection circuit, and the level control circuit is configured to detect the power supply voltage of each power amplifier. 1. A power amplifier output signal control circuit, characterized in that the power amplifier output signal control circuit is configured such that the gain of the power amplifier can also be controlled by the output of the circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1238656A JP3038729B2 (en) | 1989-09-14 | 1989-09-14 | Power amplifier output signal control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1238656A JP3038729B2 (en) | 1989-09-14 | 1989-09-14 | Power amplifier output signal control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03101509A true JPH03101509A (en) | 1991-04-26 |
| JP3038729B2 JP3038729B2 (en) | 2000-05-08 |
Family
ID=17033372
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1238656A Expired - Lifetime JP3038729B2 (en) | 1989-09-14 | 1989-09-14 | Power amplifier output signal control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3038729B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008135822A (en) * | 2006-11-27 | 2008-06-12 | Renesas Technology Corp | Rf power amplifier and wireless communication terminal mounting it |
| KR20140129107A (en) * | 2012-02-03 | 2014-11-06 | 블루 솔루션즈 | Positioning spacer, energy storage module using said spacer and method for assembling the module |
-
1989
- 1989-09-14 JP JP1238656A patent/JP3038729B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008135822A (en) * | 2006-11-27 | 2008-06-12 | Renesas Technology Corp | Rf power amplifier and wireless communication terminal mounting it |
| KR20140129107A (en) * | 2012-02-03 | 2014-11-06 | 블루 솔루션즈 | Positioning spacer, energy storage module using said spacer and method for assembling the module |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3038729B2 (en) | 2000-05-08 |
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