JPH03101241A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH03101241A JPH03101241A JP1238600A JP23860089A JPH03101241A JP H03101241 A JPH03101241 A JP H03101241A JP 1238600 A JP1238600 A JP 1238600A JP 23860089 A JP23860089 A JP 23860089A JP H03101241 A JPH03101241 A JP H03101241A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- wiring pattern
- electrode
- insulating film
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 58
- 239000002245 particle Substances 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims description 23
- 229920005989 resin Polymers 0.000 abstract description 32
- 239000011347 resin Substances 0.000 abstract description 32
- 239000011521 glass Substances 0.000 abstract description 18
- 239000000853 adhesive Substances 0.000 abstract description 8
- 230000001070 adhesive effect Effects 0.000 abstract description 8
- 238000005530 etching Methods 0.000 abstract description 3
- 239000011810 insulating material Substances 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 12
- 230000007547 defect Effects 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- 229920001187 thermosetting polymer Polymers 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 238000007747 plating Methods 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002923 metal particle Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 229920001169 thermoplastic Polymers 0.000 description 2
- 229920005992 thermoplastic resin Polymers 0.000 description 2
- 239000004416 thermosoftening plastic Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、半導体チップの配線基板上への実装構造に関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a structure for mounting a semiconductor chip on a wiring board.
［従来の技術］
近年液晶表示体やＩＣカード等一定面積の配線基板に、
多数の半導体チップを高密度かつ薄型に実装する需要が
強まっている。これらの要求に対応して半導体チップを
フェースダウンの形で直接基板上に実装する方法として
、半導体チップ７上の電極と、基板１上の配線パターン
２とを突起電極または導電粒子３を介して電気的接続を
とる方法が、知られていた。第５図は、このような従来
例を示す断面図であり、１はガラス基板、２は配線パタ
ーン、３は導電粒子、４は樹脂、５は接着剤、６は電極
、７は半導体チップである。[Prior art] In recent years, wiring boards with a fixed area such as liquid crystal displays and IC cards,
There is a growing demand for high-density and thin packaging of a large number of semiconductor chips. In response to these demands, as a method for directly mounting a semiconductor chip face-down on a substrate, the electrodes on the semiconductor chip 7 and the wiring pattern 2 on the substrate 1 are connected via protruding electrodes or conductive particles 3. Methods of making electrical connections were known. FIG. 5 is a sectional view showing such a conventional example, in which 1 is a glass substrate, 2 is a wiring pattern, 3 is a conductive particle, 4 is a resin, 5 is an adhesive, 6 is an electrode, and 7 is a semiconductor chip. be.
［発明が解決しようとする課題］
しかしながら、従来の方法では、第５図に示した上うに
配線パターン２と半導体チップ７のエツジとの間に入
り込んだ導電粒子３や、半導体チップ７のエツジにある
Ａ１配線等のダイシング時に生じるめくれ等により、半
導体チップ７と配線パターン２との間が電気的に短絡す
るというエツジショート不良が発生する。第５図では、
導電粒子３を電気的接続に使用しているが、突起電極を
用いても同様の問題を有する。[Problems to be Solved by the Invention] However, in the conventional method, as shown in FIG. Due to curling of a certain A1 wiring or the like during dicing, an edge short defect occurs in which an electrical short circuit occurs between the semiconductor chip 7 and the wiring pattern 2. In Figure 5,
Although conductive particles 3 are used for electrical connection, similar problems arise even when protruding electrodes are used.
［０１題を解決するための手段］
本発明の半導体装置は、突起電極または導電粒子を介し
、半導体チップ上の電極と基板上の配線パターンとの電
気的接続を取る構造の半導体装置において、配線パター
ン上のすくなくとも半導体チップのエツジと対向する場
所に絶縁膜を形成したことを特徴とする。[Means for Solving Problem 01] A semiconductor device of the present invention has a structure in which an electrode on a semiconductor chip is electrically connected to a wiring pattern on a substrate through a protruding electrode or a conductive particle. It is characterized in that an insulating film is formed on the pattern at least at a location facing the edge of the semiconductor chip.
［実施例］ 以下、実施例により本発明の詳細を示す。[Example] Hereinafter, the details of the present invention will be shown by examples.
（実施例１）
第１図は本発明の一実施例を示す断面図であり、１はガ
ラス基板、２は配線パターン、３は導電粒子、４は樹脂
、５は接着剤、６は電極、７は半導体チップ、８は絶縁
膜である。(Example 1) FIG. 1 is a sectional view showing an example of the present invention, in which 1 is a glass substrate, 2 is a wiring pattern, 3 is a conductive particle, 4 is a resin, 5 is an adhesive, 6 is an electrode, 7 is a semiconductor chip, and 8 is an insulating film.
まず、ガラス基板１上に半導体チップ７の電極６と対応
する形に、インジウム−スズ酸化物およびＮｉメツキに
より配線パターン２を形成する。First, the wiring pattern 2 is formed on the glass substrate 1 by indium-tin oxide and Ni plating in a shape corresponding to the electrode 6 of the semiconductor chip 7.
このガラス基板１上の全面を覆うようにポリイミド系の
絶縁材料を約１〜２μｍの厚みとなるようにスピンコー
ド、或はフレキソ印刷等を用いて塗布し絶縁膜８を形成
する。この後、配線パターン２上の絶縁Ｉｌｌ ８を半
導体チップ７の電極６と対向する場所のみエツチングに
より剥離し、配線パターン２と電極６との電気的導通が
可能となるようにする。（第２図）
次に、７．５μｍの平均直径をもつ樹脂ボール上にＡｕ
メツキを約５０ｎｍ施した導電粒子３を含むアクリル系
光硬化形樹脂４を 配線パターン２上の電極６と対応し
た位置にスクリーン印刷する。このとき、導電粒子３を
含んだ樹脂４を半導体チップ７の電極６の上に印刷して
もよい。印刷した樹脂は、約１０１００Ｏ／ｃｍ２の強
さの紫外線を２０秒間照射することによって、あらかじ
め硬化させておく。樹脂４は、導電粒子３が配線パター
ン上から流れ出さないように保持するために使用してい
る。このため樹脂４は、熱硬化性樹脂、溶剤揮発性樹脂
、熱可塑性樹脂、等の樹脂でも代用が可能である。また
、導電粒子３は、Ｎｉ、錫、半田、等のめっきを施した
樹脂ボール、或は、金、銀、銅、半田、等の金属粒子を
使用してもよい。An insulating film 8 is formed by coating the entire surface of the glass substrate 1 with a polyimide-based insulating material to a thickness of about 1 to 2 μm using a spin cord or flexographic printing. Thereafter, the insulating layer 8 on the wiring pattern 2 is removed by etching only at the portion facing the electrode 6 of the semiconductor chip 7, so that electrical continuity between the wiring pattern 2 and the electrode 6 becomes possible. (Figure 2) Next, Au was placed on a resin ball with an average diameter of 7.5 μm.
An acrylic photocurable resin 4 containing conductive particles 3 plated to a thickness of about 50 nm is screen printed on the wiring pattern 2 at positions corresponding to the electrodes 6. At this time, the resin 4 containing the conductive particles 3 may be printed on the electrodes 6 of the semiconductor chip 7. The printed resin is cured in advance by irradiating it with ultraviolet light having an intensity of about 10,100 O/cm 2 for 20 seconds. The resin 4 is used to hold the conductive particles 3 so that they do not flow out from the wiring pattern. Therefore, the resin 4 can be replaced by a thermosetting resin, a solvent volatile resin, a thermoplastic resin, or the like. Further, the conductive particles 3 may be resin balls plated with Ni, tin, solder, etc., or metal particles such as gold, silver, copper, solder, etc.
半導体チップ７とガラス基板１は、エポキシ系熱硬化・
熱可塑併用形接着剤５を配線パターン２、もしくは半導
体チップ７に塗布し、半導体チップ７の電極６と配線パ
ターン２の位置合わせを行った後、半導体チップ７を約
１０ｋｇ／ｃｍ２の圧力で加圧しかつ、１７０ ’Ｃに
加熱し１０秒間硬化させ半導体チップ７をガラス基板１
上に圧着固定する。The semiconductor chip 7 and the glass substrate 1 are made of epoxy thermosetting resin.
After applying the thermoplastic adhesive 5 to the wiring pattern 2 or the semiconductor chip 7 and aligning the electrodes 6 of the semiconductor chip 7 and the wiring pattern 2, the semiconductor chip 7 is applied with a pressure of about 10 kg/cm2. Press and heat to 170'C for 10 seconds to harden the semiconductor chip 7 to the glass substrate 1.
Crimp and fix on top.
また、接着剤として、熱硬化性樹脂、熱可塑性樹脂、常
温硬化性樹脂、嫌気性樹脂、光硬化性樹脂、電子線硬化
性樹脂、紫外線硬化性樹脂、等の樹脂を使用してもよい
。Further, as the adhesive, resins such as thermosetting resins, thermoplastic resins, room temperature curable resins, anaerobic resins, photocurable resins, electron beam curable resins, and ultraviolet curable resins may be used.
このようにして、第１図に示した様な半導体装置を作成
した。In this way, a semiconductor device as shown in FIG. 1 was produced.
（実施例２）
ガラス基板１上に半導体チップ７の電極６と対応する形
に、インジウム−スズ酸化物およびＮｉメツキにより配
線パターン２を形成する。さらにこのＮｉメツキ上に入
出力インピーダンスの低下のため、Ａｕメツキを１１０
０ｎ施す。この配線パターン２上の半導体チップ７の電
極６を含む能動面と対応する部分にレジストを塗布しマ
スクを施す。レジストによりマスクを施したガラス基板
１上にＳｉＯ２薄膜、またはＳｉＮ薄膜等の絶縁性薄膜
をプラズマＣＶＤ法により約１μｍ成長させ絶縁ＴｌＡ
３を形成する。この１組 配線パターン２上のレジス
トを適当な溶剤で剥離することにより、配線パターン２
と電極６との電気的導通が可能となるようにする。（第
３図）
次に、約２０μｍの平均直径をもつ半田粒子を導電粒子
３とし、これを含むアクリル系光硬化形樹脂４を 配線
パターン２上の電極６と対応した位置にスクリーン印刷
する。このとき、導電粒子３を含んだ樹脂４を半導体チ
ップ７の電極６の上に印刷してもよい。印刷した樹脂は
、約１０００ｍ Ｗ ／ ｃ ｍ ２の強さの紫外線を
２０秒間照射する°ことによって、あらかじめ硬化させ
ておく。(Example 2) A wiring pattern 2 is formed on a glass substrate 1 in a shape corresponding to the electrodes 6 of a semiconductor chip 7 using indium-tin oxide and Ni plating. Furthermore, in order to reduce the input/output impedance on this Ni plating, Au plating of 110
Apply 0n. A resist is applied to a portion of the wiring pattern 2 corresponding to the active surface including the electrode 6 of the semiconductor chip 7, and a mask is applied. An insulating thin film such as a SiO2 thin film or a SiN thin film is grown to a thickness of approximately 1 μm on a glass substrate 1 masked with a resist by plasma CVD to form an insulating TlA film.
form 3. By peeling off the resist on this one set of wiring patterns 2 with an appropriate solvent, wiring pattern 2
and the electrode 6 to be electrically connected to each other. (FIG. 3) Next, solder particles having an average diameter of about 20 μm are used as conductive particles 3, and acrylic photocurable resin 4 containing them is screen printed on the wiring pattern 2 at positions corresponding to the electrodes 6. At this time, the resin 4 containing the conductive particles 3 may be printed on the electrodes 6 of the semiconductor chip 7. The printed resin is precured by irradiation with ultraviolet light at an intensity of approximately 1000 m W/cm 2 for 20 seconds.
半導体チップ７とガラス基板１は、エポキシ系熱硬化・
熱硬化併用型接着剤５を配線パターン２、もしくは半導
体チップ７に塗布し、半導体チップ７の電極６と配線パ
ターン２の位置合わせを行った後、半導体チップ７を約
２０ ｋ ｇ ／ ｃ ｍ ２の圧力で加圧しかつ、１
７０°Ｃに加熱し３０秒間硬化させ半導体チップ７をガ
ラス基板１上に圧着固定する。このようにして、第１図
に示したような半導体装置を作成した。The semiconductor chip 7 and the glass substrate 1 are made of epoxy thermosetting resin.
After applying the thermosetting adhesive 5 to the wiring pattern 2 or the semiconductor chip 7 and aligning the electrodes 6 of the semiconductor chip 7 and the wiring pattern 2, the semiconductor chip 7 is heated to about 20 kg/cm 2 . Pressurized at a pressure of 1
The semiconductor chip 7 is fixed by pressure on the glass substrate 1 by heating to 70° C. and curing for 30 seconds. In this way, a semiconductor device as shown in FIG. 1 was produced.
ｍ２の強さの紫外線を２０秒間照射することによって、
電極６に対応した位置の樹脂のみ硬化させる。By irradiating ultraviolet light with an intensity of m2 for 20 seconds,
Only the resin at the position corresponding to the electrode 6 is cured.
薄板を取り除いたのち余分な樹脂を純水等で洗い流し、
配線パターン２上に樹脂４を形成する。After removing the thin plate, wash off the excess resin with pure water, etc.
A resin 4 is formed on the wiring pattern 2.
また、導電粒子３は、Ｎｉ、ｌ、半田、等のめっ施した
樹脂ボール、或は、金、銀、銅、半田、等の金属粒子を
使用してもよい。Further, the conductive particles 3 may be resin balls plated with Ni, L, solder, etc., or metal particles such as gold, silver, copper, solder, etc.
次に、実施例１と同様な方法で半導体チップ７を圧着固
定し、第１図に示したような半導体装置を作成した。Next, the semiconductor chip 7 was crimped and fixed in the same manner as in Example 1 to produce a semiconductor device as shown in FIG.
（実施例３）
実施例１で示した方法により第２図のような基板を作成
する。次に、７．５μｍの平均直径をもつ樹脂ボール上
にＡｕメツキを約５０ｎｍ＊した導電粒子３を含むアク
リル系光硬化形樹脂４を配線パターン２上の全面に塗布
する。電極６に対応した位置にエツチング等により穴あ
けを行った光を通さない薄板を配線パターン２上に位置
合わせを行う。薄板の穴を通して、約１０１００Ｏ／ｃ
（実施例４）
実施例１で示したような方法により第２図の様な基板を
作成する。次に約７．５μｍの平均直径を持つ樹脂ボー
ル上にＡｕメツキを５０ｎｍｆＩ！ｌ、。(Example 3) A substrate as shown in FIG. 2 is produced by the method shown in Example 1. Next, an acrylic photocurable resin 4 containing conductive particles 3 plated with Au to a thickness of approximately 50 nm* on a resin ball having an average diameter of 7.5 μm is applied over the entire surface of the wiring pattern 2 . A light-blocking thin plate with holes formed by etching or the like at positions corresponding to the electrodes 6 is aligned on the wiring pattern 2. Approximately 10100O/c through the hole in the thin plate
(Example 4) A substrate as shown in FIG. 2 is prepared by the method shown in Example 1. Next, Au plating was applied to a resin ball with an average diameter of about 7.5 μm to a thickness of 50 nm! l.
た導電粒子３を熱可塑・熱硬化併用型接着剤５に約３０
ｗｔ％含有させる。これを配線パターン２、或は、半導
体チップ７に塗布し、半導体チップ７の電極６と配線パ
ターン２の位置合わせを行った後、半導体チップ７を約
２０ｋｇ／Ｃｍ２の圧力で加圧しかつ、１７０“Ｃに加
熱し３０秒間硬化させ半導体チップ７をガラス基板１上
に圧着固定する。Approximately 30% of the conductive particles 3 were added to the thermoplastic/thermosetting adhesive 5.
Contain wt%. After applying this to the wiring pattern 2 or the semiconductor chip 7 and aligning the electrodes 6 of the semiconductor chip 7 and the wiring pattern 2, the semiconductor chip 7 is pressurized at a pressure of about 20 kg/cm2 and The semiconductor chip 7 is fixed on the glass substrate 1 by heating and curing for 30 seconds.
このようにして、第４図に示したような半導体装置を作
成した。In this way, a semiconductor device as shown in FIG. 4 was produced.
第１表
実施例１から４に示した方法で半導体装置を各々１００
個作成し、エツジショートによる不良の発生率を調べた
。また、比較例として第５図に示した従来例の構造を持
つ半導体装置を同様に１００個作成し、エツジショート
不良の発生率を調べた。これらをあわせて、試料１００
個中何個エッジショート不良が発生したかを調べ第１表
に示した。100 pieces of each semiconductor device were manufactured by the methods shown in Examples 1 to 4 of Table 1.
A number of samples were prepared and the incidence of defects due to edge shorts was investigated. Furthermore, as a comparative example, 100 semiconductor devices having the conventional structure shown in FIG. 5 were manufactured in the same manner, and the incidence of edge short defects was investigated. In total, 100 samples
Table 1 shows how many edge short defects occurred among the samples.
第１表から明かなごとく、実施例１から４では絶縁膜８
をガラス基板１上に施したことにより、比較例として作
成した従来例において多発したエツジショート不良を完
全になくすことができ、半導体装置の歩留まりを著しく
向上させることができた。また、比較例においては、導
電粒子３のつぶれ量に大きな差が出来たが、実施例１か
ら４の場合には、絶縁１ｉＪ８がギャップ材の役目も兼
ね、半導体チップ７とガラス基板１とのギャップを均一
に保っている。このため、実施例１から４においては導
電粒子３のつぶれ量に差は見られず、導電粒子３のつぶ
れ量の制御が容易となった。As is clear from Table 1, in Examples 1 to 4, the insulating film 8
By applying this to the glass substrate 1, it was possible to completely eliminate the edge short defects that occurred frequently in the conventional example prepared as a comparative example, and the yield of semiconductor devices could be significantly improved. In addition, in the comparative example, there was a large difference in the amount of crushing of the conductive particles 3, but in the case of Examples 1 to 4, the insulation 1iJ8 also served as a gap material, and the insulation between the semiconductor chip 7 and the glass substrate 1 Keeping the gap uniform. Therefore, in Examples 1 to 4, no difference was observed in the amount of crushing of the conductive particles 3, and it became easy to control the amount of crushing of the conductive particles 3.
このようにして、絶縁膜８を施すことにより、半導体装
置の信頼性を著しく向上させることが出来た。By applying the insulating film 8 in this manner, it was possible to significantly improve the reliability of the semiconductor device.
［発明の効果］
以上述べたように本発明によれば、配線パターン上のす
くなくとも半導体チップのエツジと対向する場所に絶縁
膜を形成することにより以下の効果が得られる。[Effects of the Invention] As described above, according to the present invention, the following effects can be obtained by forming an insulating film on the wiring pattern at least at a location facing the edge of the semiconductor chip.
■半導体チップと配線パターンとの間のエツジショート
不良を防ぐことが出来る。■Edge short defects between the semiconductor chip and the wiring pattern can be prevented.
■絶縁膜が配線パターンの外気と触れている部分を覆う
ことにより、酸化や腐食や機械的摩耗等から配線パター
ンを保護することができ、半導体装置の寿命を著しく延
長することが出来る。(2) By covering the parts of the wiring pattern that are in contact with the outside air with an insulating film, the wiring pattern can be protected from oxidation, corrosion, mechanical wear, etc., and the life of the semiconductor device can be significantly extended.
■絶縁膜は、ギャップ材の役目も兼ね、半導体チップと
基板とのギャップを均一にし、導電粒子のつぶれ量をコ
ントロールすることが容易となる。■The insulating film also serves as a gap material, making the gap between the semiconductor chip and the substrate uniform, and making it easier to control the amount of crushing of the conductive particles.
このため半導体装１の信頼性を著しく向上させることが
出来る。Therefore, the reliability of the semiconductor device 1 can be significantly improved.
第１図は、本発明における半導体装置の一実施例を示す
断面図である。
第２図は、基板上に絶縁膜を形成した一実施例を示した
斜視図である。
第３図は、基板上に絶縁膜を形成した一実施例を示した
斜視図である。
第４図は、本発明における半導体装置の一実施例を示す
断面図である。
第５図は、従来例の断面図である。
（１）
（２）
（３）
（４）
（５）
（６）
（７）
（８）
ガラス基板
配線パターン
導電粒子
樹脂
接着剤
電極
半導体チップ
絶縁膜
以 上FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention. FIG. 2 is a perspective view showing an embodiment in which an insulating film is formed on a substrate. FIG. 3 is a perspective view showing an embodiment in which an insulating film is formed on a substrate. FIG. 4 is a sectional view showing an embodiment of the semiconductor device according to the present invention. FIG. 5 is a sectional view of a conventional example. (1) (2) (3) (4) (5) (6) (7) (8) Glass substrate wiring pattern Conductive particles Resin adhesive Electrode Semiconductor chip Insulating film
Claims (1)
と基板上の配線パターンとの電気的接続を取る構造の半
導体装置において、配線パターン上のすくなくとも半導
体チップのエッジと対向する場所に絶縁膜を形成したこ
とを特徴とする半導体装置。In a semiconductor device having a structure in which an electrode on a semiconductor chip is electrically connected to a wiring pattern on a substrate through a protruding electrode or conductive particles, an insulating film is formed on the wiring pattern at least at a location facing the edge of the semiconductor chip. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1238600A JPH03101241A (en) | 1989-09-14 | 1989-09-14 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1238600A JPH03101241A (en) | 1989-09-14 | 1989-09-14 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03101241A true JPH03101241A (en) | 1991-04-26 |
Family
ID=17032600
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1238600A Pending JPH03101241A (en) | 1989-09-14 | 1989-09-14 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03101241A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0794551A (en) * | 1993-09-25 | 1995-04-07 | Nec Corp | Semiconductor device |
-
1989
- 1989-09-14 JP JP1238600A patent/JPH03101241A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0794551A (en) * | 1993-09-25 | 1995-04-07 | Nec Corp | Semiconductor device |
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