JPH03101158A - Composite electronic component - Google Patents

Composite electronic component

Info

Publication number
JPH03101158A
JPH03101158A JP1237510A JP23751089A JPH03101158A JP H03101158 A JPH03101158 A JP H03101158A JP 1237510 A JP1237510 A JP 1237510A JP 23751089 A JP23751089 A JP 23751089A JP H03101158 A JPH03101158 A JP H03101158A
Authority
JP
Japan
Prior art keywords
chip
capacitor
electronic component
composite electronic
dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1237510A
Other languages
Japanese (ja)
Inventor
Takao Takahashi
崇夫 高橋
Itsuo Sasaki
逸夫 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JFE Engineering Corp
Original Assignee
NKK Corp
Nippon Kokan Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NKK Corp, Nippon Kokan Ltd filed Critical NKK Corp
Priority to JP1237510A priority Critical patent/JPH03101158A/en
Publication of JPH03101158A publication Critical patent/JPH03101158A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

PURPOSE:To enhance the mounting density by a method wherein a dielectric sheet is pasted on the rear of an IC chip and the rear is used as a capacitor CONSTITUTION:A semiconductor capacitor element 3 of a grain-boundary type is pasted on the rear of a DRAM chip 1 via an Ag paste 2. In addition, a lead frame 5 is pasted via an Ag paste 4; a dielectric layer provided with a capacitor for bypass use is obtained on the rear side of the chip 1. A VSS of the chip 1 is connected to the frame 5 by using a bonding wire 6. Then, the capacitor for bypass is formed on the rear side of the chip 1; the mounting density is enhanced sharply; dielectric loss as viewed from the chip 1 is reduced. Thereby, a composite electronic component provided with the capacitor can be obtained easily.

Description

【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、コンデンサーを具備する複合電子部品に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a composite electronic component including a capacitor.

［従来技術及び発明が解決しようとする課題］通常、バ
イパス用コンデンサー用に用いられる約０．０１〜０，
１μＦの大容量コンデンサーは、２０ピン程度のＩＣ１
個につき１個程度の割合で外付けされる。例えば、第４
図に示すように、ＩＣのバイパス用コンデンサー１１は
、個別部品として基板１２に取り付けられ、基板１２に
形成された配線１３ａ、１３ｂ及びＩＣパッケージ１４
の外部端子１５ａ、１５ｂを通じてＩＣチップに接続さ
れていた。[Prior art and problems to be solved by the invention] Usually about 0.01 to 0.0, which is used for bypass capacitors.
A large capacity capacitor of 1μF is about 20 pins of IC1.
Approximately one per unit is externally attached. For example, the fourth
As shown in the figure, the IC bypass capacitor 11 is attached to the substrate 12 as an individual component, and the IC package 14 is connected to wirings 13a and 13b formed on the substrate 12.
It was connected to the IC chip through external terminals 15a and 15b.

このような場合、コンデンサーの存在のため、素子の実
装密度が低下し、またそれだけでなく配線引き回しによ
るインダクタンス成分が無視てきなくなるという問題が
ある。。In such a case, there is a problem that the presence of the capacitor lowers the packaging density of the elements, and that the inductance component due to the wiring cannot be ignored. .

一方、反応性ＤＣスパッタリングによりｎ　−３ｉ表面
にＴａ２０５を含む誘電体膜を形成する例が、ＩＥＥＥ
、ＩＥＤＭ　　６８４〜６８７頁に記載されている。即
ち、ｎ−８ｊ　ウェハーの（１００）面にポリシリコン
膜を形成し、リンをドープした後、フッ酸により処理し
、次いでＣＶＤにより６層ｍの厚さのＳｉ、Ｎ４層を形
成する。次に、７．５層ｍの厚さのＴａ２０９層を反応
性ＤＣスパッタにより形成し、高温（９００〜１００°
Ｃ）でアニールすることにより、５ｊ３Ｎ４層とＴａ　
２０５層との間にＳｉＯ２層を形成する。最後にＷ（タ
ングステン）電極を形成して、ＤＲＡＭのコンデンサー
か得られる。On the other hand, an example of forming a dielectric film containing Ta205 on an n-3i surface by reactive DC sputtering is described in IEEE
, IEDM pages 684-687. That is, a polysilicon film is formed on the (100) plane of an n-8j wafer, doped with phosphorus, treated with hydrofluoric acid, and then a 6 m thick Si, N4 layer is formed by CVD. Next, a Ta209 layer with a thickness of 7.5 m was formed by reactive DC sputtering at a high temperature (900-100°).
By annealing in C), the 5j3N4 layer and Ta
A SiO2 layer is formed between the 205th layer and the 205th layer. Finally, a W (tungsten) electrode is formed to obtain a DRAM capacitor.

しかし、このようなコンデンサーは、誘電体薄膜がＣＶ
Ｄ５ＰＶＤ、反応性スパッタリング等により形成される
ため、成膜に長時間を要し、このため電子部品のコスト
がかなり高くなってしまう。However, in such a capacitor, the dielectric thin film is CV
Since the film is formed by D5PVD, reactive sputtering, etc., it takes a long time to form the film, and therefore the cost of the electronic component becomes considerably high.

また、通常のＩＣ製造プロセスに適合しなければならな
いことから、膜形成条件、膜形成物質にかなりの制限を
受けてしまう。特に、高温での処理をきらうため、良好
な誘電体を得ることか困難である。Furthermore, since the film must be compatible with normal IC manufacturing processes, there are considerable restrictions on film forming conditions and film forming materials. In particular, it is difficult to obtain a good dielectric material because it is reluctant to be processed at high temperatures.

本発明は、上記事情の下になされたものであって、実装
密度を低下させることなく、簡（１１かつ安価な方法で
コンデンサーを具備する複合電子部品を提供することを
目的とする。The present invention has been made under the above circumstances, and it is an object of the present invention to provide a composite electronic component equipped with a capacitor in a simple and inexpensive manner without reducing the packaging density.

［課題を解決するための手段］ 本発明の複合電子部品は、ＩＣチップと、このＩＣチッ
プの裏面に貼（−１けられた誘′屯体板とを具備するこ
とを特徴とする。[Means for Solving the Problems] The composite electronic component of the present invention is characterized in that it comprises an IC chip and a dielectric plate attached to the back surface of the IC chip.

ＩＣチップの裏面への誘電体板の貼付けは、ＩＣチップ
の裏面に形成された導体ペースト層を介して行うことが
出来る。The dielectric plate can be attached to the back surface of the IC chip through a conductive paste layer formed on the back surface of the IC chip.

ＩＣチップがリードフレーム上にマウントされる構造の
場合には、誘電体板は、ＩＣチップとリードフレームと
の間に挟み込まれた構造となる。In the case of a structure in which the IC chip is mounted on a lead frame, the dielectric plate is sandwiched between the IC chip and the lead frame.

この場合、導体ペースト層は、ＩＣチップの裏面だけで
なく、誘電体板のリードフレームとの対向面にも形成す
ることが可能である。In this case, the conductive paste layer can be formed not only on the back surface of the IC chip but also on the surface of the dielectric plate facing the lead frame.

［作　用］ ＩＣチップは、通常、半導体基板上に各種膜形成法によ
り回路を形成することにより製造されるか、半導体基板
自体は通常Ｖ　　、とすることＤ が出来、回路形成面と反対側の面は特に利用されでいな
い。[Function] IC chips are usually manufactured by forming a circuit on a semiconductor substrate using various film formation methods, or the semiconductor substrate itself is usually made to have V and D, and the side opposite to the circuit formation surface. This aspect is not particularly utilized.

本発明においては、ＩＣチップの裏面に誘電体板を貼付
けることにより、バイパス用コンデンサ等に用いること
が出来るコンデンサーが、通常利用されていないＩＣチ
ップの裏面に容品に形成される。In the present invention, by pasting a dielectric plate on the back side of an IC chip, a capacitor that can be used as a bypass capacitor or the like is formed on the back side of the IC chip, which is not normally used.

このように、本発明の複合電子部品では、ＩＣチップの
裏面に誘電体板を貼付けることにより、実装密度が向上
するのみならず、配線引き回しによるインダクタンス成
分を殆ど無視することか出来、素子の高速動作が可能と
なる。As described above, in the composite electronic component of the present invention, by attaching a dielectric plate to the back surface of the IC chip, not only the packaging density is improved, but also the inductance component due to wiring can be almost ignored, and the element High-speed operation is possible.

例えば、本発明の複合電子部品において、どのＩＣにも
必ず必要とされる０、０１〜０．１μＦのバイパス用コ
ンデンサーを内蔵させることにより、実装密度か向上す
るたけでなく、配線引き回しによるインダクタンス成分
を低下させることが出来、ＩＣチップからみた実質的な
誘電損失を低減することが出来る。このため、ＩＣのよ
り一層の高速動作が可能となる。For example, in the composite electronic component of the present invention, by incorporating a bypass capacitor of 0.01 to 0.1 μF, which is absolutely necessary for every IC, it not only improves the packaging density, but also reduces the inductance component due to wiring. Therefore, it is possible to reduce the substantial dielectric loss seen from the IC chip. Therefore, even higher speed operation of the IC is possible.

特に、ＩＣチップの裏面への誘電体板の貼付けは、導電
ペーストにより容易に行うことか出来るため、ＣＶＤ、
ＰＶＤ、反応性スパッタリングという高価な装置と長時
間を要する薄膜形成プロセスを用いる必要がなく、コス
トの低減を図ることが出来る。また、誘電体の材質を自
由に選択することが出来るとともに、誘電体の形成を最
適な条件で行うことか可能である。In particular, since the dielectric plate can be easily attached to the back side of the IC chip using conductive paste, CVD,
There is no need to use expensive equipment such as PVD or reactive sputtering and a thin film formation process that requires a long time, and costs can be reduced. Furthermore, the material of the dielectric can be freely selected, and the dielectric can be formed under optimal conditions.

なお、本発明の複合電子部品においては、ＩＣチップの
裏面に誘電体板が貼付けられているため、ＩＣチップの
高さは見掛は上高くなるが、平面的な実装面積はほぼ１
／２となる。In addition, in the composite electronic component of the present invention, since a dielectric plate is attached to the back surface of the IC chip, the height of the IC chip is apparently higher, but the planar mounting area is approximately 1.
/2.

［実施例コ 以下、図面を参照して本発明の実施例を示し、本発明を
より具体的に説明する。[Embodiments] Hereinafter, embodiments of the present invention will be shown and the present invention will be explained in more detail with reference to the drawings.

第１図に示すように、２５６にビットのＤＲＡＭチップ
１の裏面に、Ａｇペースト２を介して粒界型半導体コン
デンサー素体３を貼付け、更にこれをＡｇペースト４を
介してリードフレム５に貼付けることにより、容量０．
０２２μＦのバイパス用コンデンサーを具備するＤＲＡ
Ｍを形成した。ＤＲＡＭチップ１のＶ　　はポンデイＳ ングワイヤ６によりリードフレーム５に結線されている
。As shown in FIG. 1, a grain boundary type semiconductor capacitor body 3 is attached to the back side of the DRAM chip 1 of the bit at 256 via Ag paste 2, and this is further attached to the lead frame 5 via Ag paste 4. By this, the capacity is 0.
DRA with 022μF bypass capacitor
M was formed. V of the DRAM chip 1 is connected to the lead frame 5 by a connecting wire 6.

粒界型半導体コンデンサー索体３はチタン酸ストロンチ
ウム系半導体からなるコンデンサー素体であり、結晶粒
径を８０μｍ程度とし、１０００℃という低温でＢｊを
拡散させて粒界絶縁化を行うことにより、１２Ｖでバリ
スタ性を発現させ、ＤＲＡＭチップ１の保護の機能を果
たさせている。The grain boundary type semiconductor capacitor cable body 3 is a capacitor element body made of a strontium titanate-based semiconductor, with a crystal grain size of approximately 80 μm, and by diffusing Bj at a low temperature of 1000°C to perform grain boundary insulation, a voltage of 12V is achieved. It exhibits varistor properties and functions to protect the DRAM chip 1.

第１図に示す構造とすることにより、従来、外付けされ
ていたバイパス用コンデンサーがＤＲＡＭチップの裏面
に形成されるため、実装密度が大幅に向上し、チップか
らみた誘電損失も１／２以下に低減した。By adopting the structure shown in Figure 1, the bypass capacitor that was conventionally attached externally is formed on the back side of the DRAM chip, greatly improving packaging density and reducing dielectric loss by half or less when viewed from the chip. It was reduced to

第２図は、ハイブリッドＩＣ基板又は複合基板７上に、
粒界型半導体コンデンサー索体３を間に挟んでＤ　Ｒ，
Ａ　Ｍチップ１をマウントシた構造を示す。また、第３
図は、■　　およびＶ　　を独立ＤＤ　　　　　ＳＳ したパッドからとり、■　　を粒界型半導体コンＤ デンサー素体３に、■　　をリードフレーム５に、ＳＳ ボンディングワイヤ６により結線した構造を示す。FIG. 2 shows that on the hybrid IC board or composite board 7,
D R with the grain boundary type semiconductor capacitor cable body 3 in between,
The structure in which the AM chip 1 is mounted is shown. Also, the third
The figure shows a structure in which ■ and V are taken from independent DDSS pads, and ■ is connected to a grain boundary type semiconductor capacitor D capacitor body 3, and ■ is connected to a lead frame 5 by SS bonding wires 6.

いずれの構造も、第１図に示すＤＲＡＭと同様、実装密
度が大幅に向上し、チップからみた誘電損失も１／２以
下に低減した。In both structures, as with the DRAM shown in FIG. 1, the packaging density has been greatly improved, and the dielectric loss seen from the chip has been reduced to less than half.

［発明の効果コ 以上説明したように、本発明によると、従来利用されて
いなかったＩＣチップの裏面に誘電体板を貼付けること
により、実装密度が向上した、コンデンサーを具備する
複合電子部品を容易に得ることが出来る。また、配線引
き回しによるインダクタンス成分を殆ど無視することが
出来るため、素子の高速動作が可能となる。[Effects of the Invention] As explained above, according to the present invention, by pasting a dielectric plate on the back side of an IC chip, which has not been used in the past, it is possible to create a composite electronic component equipped with a capacitor with improved packaging density. It can be obtained easily. Furthermore, since the inductance component due to wiring can be almost ignored, the device can operate at high speed.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、本発明の一実施例に係る、ＤＲＡＭチップの
裏面にバイパス用コンデンサーを具備する複合電子部品
を示す断面図、第２図及び第３図は、第１図に示す複合
電子部品の変形例を示す断面図、第４図は、従来のバイ
パス用コンデンサとＩＣチップトノ接続を示す図である
。 １・・・ＤＲＡＭチップ、２，４・・Ａｇペースト、３
・・・粒界型半導体コンデンサー素体、５・・・リード
フレーム、６・・・ハイブリッドＩＣ基板、７・・ボン
ディングワイヤ。FIG. 1 is a sectional view showing a composite electronic component including a bypass capacitor on the back side of a DRAM chip according to an embodiment of the present invention, and FIGS. 2 and 3 are a sectional view of the composite electronic component shown in FIG. 1. FIG. 4 is a sectional view showing a modification of the conventional bypass capacitor and an IC chip top connection. 1...DRAM chip, 2,4...Ag paste, 3
... Grain boundary type semiconductor capacitor element body, 5... Lead frame, 6... Hybrid IC board, 7... Bonding wire.

Claims (5)

【特許請求の範囲】[Claims] （１）ＩＣチップと、このＩＣチップの裏面に貼付けら
れた誘電体板とを具備する複合電子部品。(1) A composite electronic component comprising an IC chip and a dielectric plate attached to the back surface of the IC chip. （２）前記ＩＣチップの裏面に第１の導体ペースト層が
設けられていることを特徴とする請求項１に記載の複合
電子部品。(2) The composite electronic component according to claim 1, wherein a first conductive paste layer is provided on the back surface of the IC chip. （３）前記誘電体板は、前記ＩＣチップとリードフレー
ムとの間に挟み込まれていることを特徴とする請求項１
に記載の複合電子部品。(3) Claim 1, wherein the dielectric plate is sandwiched between the IC chip and a lead frame.
Composite electronic components described in . （４）前記誘電体板の前記リードフレームとの対向面に
第２の導体ペースト層が設けられていることを特徴とす
る請求項３に記載の複合電子部品。(4) The composite electronic component according to claim 3, wherein a second conductive paste layer is provided on a surface of the dielectric plate facing the lead frame. （５）前記ＩＣチップの裏面に第１の導体ペースト層が
設けられ、かつ前記誘電体板の前記リードフレームとの
対向面に第２の導体ペースト層が設けられていることを
特徴とする請求項３に記載の複合電子部品。(5) A first conductive paste layer is provided on the back surface of the IC chip, and a second conductive paste layer is provided on the surface of the dielectric plate facing the lead frame. Composite electronic component according to item 3.
JP1237510A 1989-09-13 1989-09-13 Composite electronic component Pending JPH03101158A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1237510A JPH03101158A (en) 1989-09-13 1989-09-13 Composite electronic component

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1237510A JPH03101158A (en) 1989-09-13 1989-09-13 Composite electronic component

Publications (1)

Publication Number Publication Date
JPH03101158A true JPH03101158A (en) 1991-04-25

Family

ID=17016392

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1237510A Pending JPH03101158A (en) 1989-09-13 1989-09-13 Composite electronic component

Country Status (1)

Country Link
JP (1) JPH03101158A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008028004A (en) * 2006-07-19 2008-02-07 Toshiba Corp Semiconductor device
JP2008251901A (en) * 2007-03-30 2008-10-16 Fuji Electric Device Technology Co Ltd Composite semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008028004A (en) * 2006-07-19 2008-02-07 Toshiba Corp Semiconductor device
JP2008251901A (en) * 2007-03-30 2008-10-16 Fuji Electric Device Technology Co Ltd Composite semiconductor device

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