JPH03101147A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03101147A JPH03101147A JP23577489A JP23577489A JPH03101147A JP H03101147 A JPH03101147 A JP H03101147A JP 23577489 A JP23577489 A JP 23577489A JP 23577489 A JP23577489 A JP 23577489A JP H03101147 A JPH03101147 A JP H03101147A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- film
- insulating film
- silicon oxide
- photoresist mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000002955 isolation Methods 0.000 claims abstract description 43
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 40
- 238000000034 method Methods 0.000 claims abstract description 34
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 30
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000000151 deposition Methods 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 238000001020 plasma etching Methods 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052710 silicon Inorganic materials 0.000 abstract description 6
- 239000010703 silicon Substances 0.000 abstract description 6
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 238000001312 dry etching Methods 0.000 abstract description 4
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 4
- 230000010354 integration Effects 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000007791 liquid phase Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 239000012670 alkaline solution Substances 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- KGBXLFKZBHKPEV-UHFFFAOYSA-N boric acid Chemical compound OB(O)O KGBXLFKZBHKPEV-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- -1 boron ions Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- LRCFXGAMWKDGLA-UHFFFAOYSA-N dioxosilane;hydrate Chemical compound O.O=[Si]=O LRCFXGAMWKDGLA-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 239000012047 saturated solution Substances 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
本発明は、半導体装置の製造方法に係り、とくに微細幅
の素子分離領域の形成工程の改良に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and particularly to an improvement in a process for forming a device isolation region with a fine width.
（従来の技術）
ＭＯＳ集積回路における素子の微細化、高集積化を実現
するための素子分離法として、これまで広く用いられて
きたＬＯＣＯ８法に代わって、半導体基板に溝を掘って
ここに素子分離絶縁膜を埋め込む方法が提案されている
。(Prior art) In place of the LOCO8 method that has been widely used as an element isolation method to achieve miniaturization and high integration of elements in MOS integrated circuits, trenches are dug in the semiconductor substrate and elements are placed here. A method of embedding an isolation insulating film has been proposed.
第２図（ａ＞〜（Ｃ）は、その様な埋込み法を利用した
従来の素子分離の工程である。（ａ）に示すように、シ
リコン基板２１にシリコン酸化膜２２゜シリコン窒化膜
２３を積層形成し、この上に素子分離領域に開口を持つ
フォトレジスト・マスク２４を形成する。そしてこのフ
ォトレジスト・マスク２４を用いてシリコン窒化膜２３
．シリコン酸化膜２２．シリコン基板２１を順次をドラ
イエツチング法によって選択エツチングして、（ｂ）に
示すように素子分離溝２５を形成する。その後（Ｃ）に
示すように溝にシリコン酸化膜２６を形成して反転防止
層形成用のイオン注入を行い、次いでＣＶＤ法によりシ
リコン酸化膜２７を溝２５内に埋込み形成する。この酸
化膜埋込みは例えば、全面に酸化膜を堆積形成した後、
その表面をフォトレジスト等によって平坦化し、フォト
レジストと酸化膜に対するエツチング速度が等しい条件
に設定されたドライエツチング法によって全面エツチン
グすることにより行う。2(a> to (C)) show a conventional device isolation process using such a burying method.As shown in FIG. 2(a), a silicon oxide film 22, a silicon nitride film 23, A photoresist mask 24 having an opening in the element isolation region is formed on this layer.Then, using this photoresist mask 24, a silicon nitride film 23 is formed.
．． Silicon oxide film 22. The silicon substrate 21 is sequentially selectively etched using a dry etching method to form element isolation grooves 25 as shown in FIG. Thereafter, as shown in (C), a silicon oxide film 26 is formed in the trench, ions are implanted to form an anti-inversion layer, and then a silicon oxide film 27 is buried in the trench 25 by CVD. This oxide film embedding can be done, for example, by depositing an oxide film on the entire surface, and then
The surface is planarized using a photoresist or the like, and the entire surface is etched using a dry etching method in which the etching rates for the photoresist and the oxide film are set to be equal.
しかしながらこの方法では、埋込み酸化膜の膜厚制御性
が十分でない。そして、素子分離溝の上部コーナーが露
出する状態になると素子特性上問題となる。この問題を
具体的に第３図を用いて説明する。However, this method does not provide sufficient control over the thickness of the buried oxide film. If the upper corner of the element isolation trench is exposed, it will cause problems in terms of element characteristics. This problem will be specifically explained using FIG. 3.
第３図は上述した方法により素子分離された基板に、ゲ
ート酸化膜２８を形成してこの上にゲート電極２９を形
成し、ゲート電極２９をマスクとして不純物をドープし
てソース、ドレイン拡散層３０．３１を形成した状態を
示している。図では、素子分離溝２５に埋め込まれたシ
リコン酸化膜２６が薄＜、！２５の上部コーナーが露出
する状態を示している。このとき図のようにゲート電極
２９が配設されると、ＭＯＳトランジスタのチャネル幅
方向端部の溝上部コーナーＡ、Ｂにゲート電極２９が対
向し、これらの上部コーナーＡ、 Ｂで電界集中が起
こる。この結果上部コーナーＡ。FIG. 3 shows that a gate oxide film 28 is formed on a substrate subjected to device isolation by the method described above, a gate electrode 29 is formed thereon, and impurities are doped using the gate electrode 29 as a mask to form source and drain diffusion layers 30. .31 is shown. In the figure, the silicon oxide film 26 buried in the element isolation trench 25 is thin <,! The upper corner of No. 25 is shown exposed. At this time, if the gate electrode 29 is disposed as shown in the figure, the gate electrode 29 faces the upper corners A and B of the groove at the ends in the channel width direction of the MOS transistor, and the electric field is concentrated at these upper corners A and B. happen. This results in upper corner A.
Ｂでは反転が起り易くなり、従って特にチャネル幅の狭
いＭＯＳ）ランジスタでは大きいしきい値の低下をもた
らす。In the case of B, inversion is more likely to occur, resulting in a large reduction in the threshold value, especially in a MOS transistor with a narrow channel width.
これを解決する方法として、素子分離溝にシリコン酸化
膜を埋込み形成した後、さらにその上にシリコン酸化膜
をＣＶＤ法によって堆積し、パターン形成して素子分離
領域を絶縁膜で覆う方法が提案されている。As a method to solve this problem, a method has been proposed in which a silicon oxide film is buried in the element isolation trench, and then a silicon oxide film is deposited on top of it by the CVD method, and then patterned to cover the element isolation region with an insulating film. ing.
第４図（ａ）〜（ｅ）は、その様な素子分離形成工程で
ある。（ａ） 〜（ｃ）までは第２図の（ａ） 〜（ｃ
）と同じである。この後、（ｄ）に示すように全面にＣ
ＶＤ法によりシリコン酸化膜３０を堆積し、その上にフ
ォトレジスト・マスク３１を形成する。FIGS. 4(a) to 4(e) show such element isolation formation steps. (a) to (c) in Figure 2
) is the same as After this, as shown in (d), the entire surface is covered with C.
A silicon oxide film 30 is deposited by the VD method, and a photoresist mask 31 is formed thereon.
そしてこのマスク３１を用いて酸化膜３０を選択エツチ
ングし、（ｅ）に示すように素子分離溝領域上に酸化膜
３０を残す。Then, the oxide film 30 is selectively etched using this mask 31, leaving the oxide film 30 on the element isolation groove region as shown in FIG.
この方法によれば、当初に埋め込まれた酸化膜２７の膜
厚が溝の深さより薄い場合であっても、この上をさらに
酸化膜３０で覆うことにより、溝２５の上部コーナーの
露出が防止される。According to this method, even if the thickness of the initially buried oxide film 27 is thinner than the depth of the trench, by further covering it with the oxide film 30, the upper corner of the trench 25 is prevented from being exposed. be done.
しかしながらこの方法では、酸化膜３０のパターン形成
にフォトリソグラフィを用いているために、合わせずれ
を考慮しなければならず、それだけ素子分離領域幅が増
大してしまうという難点がある。However, since this method uses photolithography to pattern the oxide film 30, it is necessary to take misalignment into consideration, which has the disadvantage that the width of the element isolation region increases accordingly.
（発明が解決しようとする課題）
以上のように従来の絶縁膜埋込みを利用した素子分離技
術では、素子分離溝上部コーナーの露出による素子特性
劣化があり、これを解決しようとすると素子分離領域幅
が増大するといった問題があった。(Problems to be Solved by the Invention) As described above, in the conventional device isolation technology using insulating film embedding, device characteristics deteriorate due to exposure of the upper corner of the device isolation trench. There was a problem with the increase in
本発明はこのような問題を解決した素子分離法を利用し
た半導体装置の製造方法を提供することを目的とする。An object of the present invention is to provide a method for manufacturing a semiconductor device using an element isolation method that solves these problems.
［発明の構成コ
（課題を解決するための手段）
本発明の方法は、まず半導体基板上にフォトレジスト・
マスクを形成し、このフォトレジスト・マスクを用いて
基板を選択エツチングして素子分離領域に溝を形成する
。次いでフォトレジスト・マスクを残した状態で形成さ
れた溝にその深さ以上の膜厚をもって第１の絶縁膜を埋
込み形成する。その後フォトレジスト・マスクを除去し
た後、第１の絶縁膜の側壁に選択的に第２の絶縁膜を形
成する。そして第１および第２の絶縁膜により囲まれた
素子形成領域に所望の素子を形成する。[Configuration of the Invention (Means for Solving the Problems) The method of the present invention first includes forming a photoresist on a semiconductor substrate.
A mask is formed and the photoresist mask is used to selectively etch the substrate to form trenches in isolation regions. Next, a first insulating film is buried in the trench formed with the photoresist mask left in place to a thickness equal to or greater than the depth of the trench. After removing the photoresist mask, a second insulating film is selectively formed on the sidewalls of the first insulating film. Then, a desired element is formed in the element formation region surrounded by the first and second insulating films.
（作用）
本発明によれば、素子分離溝を形成した後に、その溝形
成に用いたフォトレジスト・マスクを残したまま絶縁膜
埋込みを行って、溝の深さ以上の膜厚の第１の絶縁膜を
形成し、その側壁に更に第２の絶縁膜を形成するから、
素子分離溝の上部コーナーが露出することはない。従っ
て素子分離溝の上部コーナーが露出することによる素子
特性劣化が防止される。しかも第２の絶縁膜は所謂側壁
残しの技術により自己整合的に形成できるので、合わせ
ずれを考慮する必要がなく、素子分離領域幅を必要最小
限に抑えることができる。以上により、優れた特性の素
子を高密度集積化することができる。(Function) According to the present invention, after forming an element isolation trench, an insulating film is buried with the photoresist mask used for forming the trench remaining, and a first film having a thickness equal to or greater than the depth of the trench is formed. Since an insulating film is formed and a second insulating film is further formed on the side wall of the insulating film,
The upper corner of the element isolation trench is never exposed. Therefore, deterioration of device characteristics due to exposure of the upper corner of the device isolation trench is prevented. Moreover, since the second insulating film can be formed in a self-aligned manner by a so-called sidewall leaving technique, there is no need to consider misalignment, and the width of the element isolation region can be suppressed to the necessary minimum. As described above, elements with excellent characteristics can be integrated at high density.
（実施例） 以下、本発明の詳細な説明する。(Example) The present invention will be explained in detail below.
第１図（ａ）〜（ｈ）は、一実施例の素子形成工程を示
す断面図である。ｐ型シリコン基板１を酸化して約５０
０人のシリコン酸化膜２を形成した後、この上にＣＶＤ
法によって約１５０ＯＡのシリコン窒化膜３を堆積形成
する。そしてこの上にフォトリソグラフィによって、素
子形成領域を覆うフォトレジスト・マスク４を形成する
（（ａ））。FIGS. 1(a) to 1(h) are cross-sectional views showing the element forming process of one embodiment. The p-type silicon substrate 1 is oxidized to about 50%
After forming the silicon oxide film 2, CVD is performed on it.
A silicon nitride film 3 having a thickness of about 150 OA is deposited by a method. Then, a photoresist mask 4 covering the element formation region is formed on this by photolithography ((a)).
そして反応性イオンエツチング法等の異方性ドライエツ
チング法を用いて基板を選択エツチングして、略垂直側
壁を持つ深さ０．５μｍ程度の素子分離溝５を形成する
。その後、ボロンをイオン注入して素子分離溝５の底、
部に反転防止層６を形成する（（ｂ））。Then, the substrate is selectively etched using an anisotropic dry etching method such as a reactive ion etching method to form an element isolation groove 5 having a depth of about 0.5 μm and having substantially vertical sidewalls. After that, boron ions are implanted into the bottom of the element isolation trench 5.
An anti-inversion layer 6 is formed on the portion ((b)).
次に、フォトレジスト・マスク４を残した状態で選択的
に素子分離溝５の領域に第１の絶縁膜として例えばシリ
コン酸化膜７を埋込み形成する（（Ｃ））。このとき埋
め込まれるシリコン酸化膜７は、素子分離溝５の深さ以
上の膜厚とする。このシリコン酸化膜埋込みには、次の
ような液相成長法を利用する。まず、シリカ（Ｓｉ０２
）を飽和させた珪弗化水素酸（ＨｚＳｉＦ６）水溶液に
硼酸（Ｈ３ＢＯ３）水溶液を添加して、シリカを過飽和
させる。このシリカ過飽和液を例えば３０℃に保ち、こ
の液中に（ｂ）のシリコン基板を浸すことにより、フォ
トレジスト・マスク４で覆われた領域以外の領域に選択
的にシリコン酸化膜を析出させる。なおこの析出堆積を
行うためには、素子分離溝５の内壁を水洗等により親水
性処理しておくことが必要である。また酸化膜埋込みに
先立って、素子分離溝５の内壁をアルカリ溶液を含むエ
ツチング液により或いはＣＤＥ法によって５０〜１００
おぐエツチングして、反応性イオンエツチングによるダ
メージ層を除去する工程を付加する事も有効である。Next, with the photoresist mask 4 remaining, for example, a silicon oxide film 7 is selectively buried in the region of the element isolation trench 5 as a first insulating film ((C)). The silicon oxide film 7 buried at this time has a thickness equal to or greater than the depth of the element isolation trench 5. The following liquid phase growth method is used to embed the silicon oxide film. First, silica (Si02
) is added to an aqueous solution of hydrosilicic acid (HzSiF6) saturated with boric acid (H3BO3) to supersaturate the silica. This silica supersaturated solution is maintained at, for example, 30° C., and by immersing the silicon substrate (b) in this solution, a silicon oxide film is selectively deposited in areas other than the area covered with the photoresist mask 4. Note that in order to carry out this precipitation deposition, it is necessary to perform a hydrophilic treatment on the inner wall of the element isolation groove 5 by washing with water or the like. In addition, prior to embedding the oxide film, the inner wall of the element isolation trench 5 is etched to a depth of 50 to 100% using an etching solution containing an alkaline solution or by the CDE method.
It is also effective to add a step of removing the damaged layer caused by reactive ion etching.
こうしてシリコン酸化膜７を埋込み形成した後、フォト
レジスト・マスク４を除去する（（ｄ））。After forming the silicon oxide film 7 in this way, the photoresist mask 4 is removed ((d)).
その後、８５０℃程度の水蒸気雰囲気中で熱処理する。Thereafter, heat treatment is performed in a steam atmosphere at about 850°C.
この処理により、析出されたシリコン酸化膜７からの酸
素供給によって、内壁面には約２００人の良質の熱酸化
膜８が形成される（（ｅ））。Through this treatment, about 200 high quality thermal oxide films 8 are formed on the inner wall surface due to the supply of oxygen from the deposited silicon oxide film 7 ((e)).
次いでシリコン窒化膜３をエツチング除去する（（１’
））。Next, the silicon nitride film 3 is removed by etching ((1')
)).
その後、素子分離領域に突出したシリコン酸化膜７の側
壁に選択的に、第２の絶縁膜としてシリコン酸化膜９を
形成する （（ｇ））。このシリコン酸化膜９の形成は
、まず全面にＣＶＤ法により１０００人程度シリコン酸
化膜を堆積した後、全面を反応性イオンエツチング法で
エツチングして側壁部にのみ選択的にシリコン酸化膜９
を残置させる、所謂側壁残しの技術を利用する。Thereafter, a silicon oxide film 9 is selectively formed as a second insulating film on the sidewalls of the silicon oxide film 7 protruding into the element isolation region ((g)). The silicon oxide film 9 is formed by first depositing about 1,000 silicon oxide films on the entire surface using the CVD method, and then etching the entire surface using the reactive ion etching method to selectively selectively form the silicon oxide film 9 only on the side walls.
The so-called side wall leaving technique is used.
この後は通常の素子形成工程にしたがって、素子形成領
域にゲート酸化膜１０を形成し、多結晶シリコン膜の堆
積とパターニングによってゲート電極１１を形成し、ゲ
ート電極をマスクとして砒素等をイオン注入してソース
、ドレイン拡散層１２．１３を形成する（ （ｈ））。After this, according to the usual device formation process, a gate oxide film 10 is formed in the device formation region, a gate electrode 11 is formed by depositing and patterning a polycrystalline silicon film, and arsenic or the like is ion-implanted using the gate electrode as a mask. Then, source and drain diffusion layers 12 and 13 are formed ((h)).
図では、一つのＭＯＳ）ランジスタのチャネル幅方向の
断面を示している。その後は図示しないが、全面をＣＶ
Ｄ絶縁膜で覆い、コンタクト孔を開けてｌ？配線を施す
ことより、ＭＯ８集積回路が完成する。The figure shows a cross section of one MOS transistor in the channel width direction. After that, although not shown, the entire surface is CV
D Cover with insulating film and make a contact hole. The MO8 integrated circuit is completed by wiring.
この実施例によれば、第１図（ｈ）から明らかなように
、素子分離溝の上部コーナーが露出することはなく、形
成されたＭＯＳ）ランジスタのチ０
ャネル幅方向端部での電界集中によるしきい値低下が確
実に防止される。したがって微細寸法のＭＯＳトランジ
スタであっても優れた特性が得られる。また素子分離領
域端部を覆うシリコン酸化膜９は、側壁残しによって素
子分離領域に自己整合されて形成されるから、素子分離
領域幅が無用に増大することはなく、従って素子の高密
度集積化が実現できる。According to this embodiment, as is clear from FIG. 1(h), the upper corner of the element isolation trench is not exposed, and the electric field is concentrated at the end of the channel width of the formed MOS transistor. This will reliably prevent the threshold value from decreasing. Therefore, excellent characteristics can be obtained even in a MOS transistor with minute dimensions. In addition, since the silicon oxide film 9 covering the end of the element isolation region is formed in a self-aligned manner with the element isolation region by leaving sidewalls, the width of the element isolation region does not increase unnecessarily, and therefore high-density integration of elements is possible. can be realized.
本発明は上記実施例に限られるものではない。The present invention is not limited to the above embodiments.
例えば実施例では、素子分離溝へのシリコン酸化膜埋込
みをシリカ飽和溶液を用いた液相成長法によったが、Ｃ
ＶＤ法により埋込みを行うこともできる。この場合、フ
ォトレジスト・マスク上にもシリコン酸化膜が堆積する
が、これはフォトレジストと共にリフトオフすることに
よって、上記実施例と同様の埋込み構造が得られる。そ
の池水発明はその趣旨を逸脱しない範囲で種々変形して
実施することができる。For example, in the example, the silicon oxide film was buried in the element isolation trench by a liquid phase growth method using a silica saturated solution.
Embedding can also be performed by the VD method. In this case, a silicon oxide film is also deposited on the photoresist mask, and by lifting off together with the photoresist, a buried structure similar to that of the above embodiment is obtained. The pond water invention can be implemented with various modifications without departing from the spirit thereof.
［発明の効果コ
以上述べたように本発明による素子分離技術で１
は、素子分離溝上部コーナーが露出することによる素子
特性劣化か防止され、しかも素子分離溝上部コーナーは
自己整合的に絶縁膜で覆われる。したがって優れた素子
特性をもって微細素子の高密度集積化をはかることがで
きる。[Effects of the Invention] As described above, the device isolation technology according to the present invention prevents deterioration of device characteristics due to exposure of the upper corners of the device isolation trenches, and furthermore, the upper corners of the device isolation trenches are formed with an insulating film in a self-aligned manner. covered with Therefore, it is possible to achieve high-density integration of fine devices with excellent device characteristics.
第１図（ａ）〜（ｈ）は本発明の一実施例の製造工程を
示す断面図、
第２図（ａ）〜（ｃ）は従来の素子分離法を説明するた
めの断面図、
第３図は従来法による問題を説明するための断面図、
第４図（ａ）〜（ｅ）は従来の別の素子分離法を説明す
るための断面図である。
１・・・シリコン基板、２・・シリコン酸化膜、３・・
・シリコン窒化膜、４・・・フォトレジスト・マスク、
５・・素子分離溝、６・・・反転防止層、７・・・シリ
コン酸化膜（第１の絶縁膜）、８・・・熱酸化膜、９・
・・シリコン酸化膜（第２の絶縁膜）、１０・・・ゲー
ト酸化膜、１１・・・ゲート電極、１２．１３・・ソー
ス。
２
ドレイン拡散層。FIGS. 1(a) to (h) are cross-sectional views showing the manufacturing process of an embodiment of the present invention. FIGS. 2(a) to (c) are cross-sectional views for explaining the conventional element isolation method. FIG. 3 is a cross-sectional view for explaining problems caused by the conventional method, and FIGS. 4(a) to (e) are cross-sectional views for explaining another conventional element isolation method. 1...Silicon substrate, 2...Silicon oxide film, 3...
・Silicon nitride film, 4... Photoresist mask,
5... Element isolation trench, 6... Inversion prevention layer, 7... Silicon oxide film (first insulating film), 8... Thermal oxide film, 9...
... Silicon oxide film (second insulating film), 10... Gate oxide film, 11... Gate electrode, 12.13... Source. 2 Drain diffusion layer.
Claims (3)
、このフォトレジスト・マスクを用いて基板を選択エッ
チングして素子分離領域に溝を形成する工程と、 前記フォトレジスト・マスクを残した状態で前記溝にそ
の深さ以上の膜厚をもって第１の絶縁膜を埋込み形成す
る工程と、 前記フォトレジスト・マスクを除去した後、前記第１の
絶縁膜の側壁に選択的に第２の絶縁膜を形成する工程と
、 前記第１および第２の絶縁膜により囲まれた素子形成領
域に所望の素子を形成する工程と、を有することを特徴
とする半導体装置の製造方法。(1) A step of forming a photoresist mask on a semiconductor substrate, selectively etching the substrate using this photoresist mask to form a groove in an element isolation region, and leaving the photoresist mask in place. burying a first insulating film in the trench to a thickness equal to or greater than the depth thereof; and after removing the photoresist mask, selectively forming a second insulating film on the sidewalls of the first insulating film; A method for manufacturing a semiconductor device, comprising: forming a desired element in an element forming region surrounded by the first and second insulating films.
を用いて前記フォトレジスト・マスク以外の領域に選択
的にシリコン酸化膜を析出させる請求項１記載の半導体
装置の製造方法。(2) The method of manufacturing a semiconductor device according to claim 1, wherein in the step of forming the first insulating film, a silicon oxide film is selectively deposited in a region other than the photoresist mask using a supersaturated silica solution.
を形成する工程は、ＣＶＤ法により全面に第２の絶縁膜
を堆積した後、これを反応性イオンエッチング法により
全面エッチングする請求項１記載の半導体装置の製造方
法。(3) The step of selectively forming a second insulating film on the sidewalls of the first insulating film involves depositing the second insulating film on the entire surface using the CVD method, and then depositing the second insulating film on the entire surface using the reactive ion etching method. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23577489A JPH03101147A (en) | 1989-09-13 | 1989-09-13 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23577489A JPH03101147A (en) | 1989-09-13 | 1989-09-13 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03101147A true JPH03101147A (en) | 1991-04-25 |
Family
ID=16991042
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23577489A Pending JPH03101147A (en) | 1989-09-13 | 1989-09-13 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03101147A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0646956A2 (en) * | 1993-09-30 | 1995-04-05 | Motorola, Inc. | Trench isolation structure in an integrated circuit and method of formation |
| US5433794A (en) * | 1992-12-10 | 1995-07-18 | Micron Technology, Inc. | Spacers used to form isolation trenches with improved corners |
| US5677229A (en) * | 1992-10-27 | 1997-10-14 | Kabushiki Kaisha Toshiba | Method for manufacturing semiconductor device isolation region |
| US5741738A (en) * | 1994-12-02 | 1998-04-21 | International Business Machines Corporation | Method of making corner protected shallow trench field effect transistor |
| WO1999010918A1 (en) * | 1997-08-22 | 1999-03-04 | Micron Technology, Inc. | Process of isolation in integrated circuit fabrication, using an antireflective coating |
| KR19990057300A (en) * | 1997-12-29 | 1999-07-15 | 김영환 | Trench formation method with improved leakage characteristics |
| US6444588B1 (en) | 1999-04-26 | 2002-09-03 | Micron Technology, Inc. | Anti-reflective coatings and methods regarding same |
| US6541843B2 (en) | 1998-09-03 | 2003-04-01 | Micron Technology, Inc. | Anti-reflective coatings and methods for forming and using same |
| JP2006078489A (en) * | 2004-09-08 | 2006-03-23 | Korea Electronics Telecommun | Device for measuring image and lifetime of display panel |
| CN100359665C (en) * | 2002-07-24 | 2008-01-02 | 三星电子株式会社 | Method for fabricating low well of semiconductor device using low energy ion implantation |
| JP4955880B2 (en) * | 1999-08-30 | 2012-06-20 | スパンション エルエルシー | Method for fabricating an integrated circuit forming a trench in a substrate |
-
1989
- 1989-09-13 JP JP23577489A patent/JPH03101147A/en active Pending
Cited By (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5677229A (en) * | 1992-10-27 | 1997-10-14 | Kabushiki Kaisha Toshiba | Method for manufacturing semiconductor device isolation region |
| US5433794A (en) * | 1992-12-10 | 1995-07-18 | Micron Technology, Inc. | Spacers used to form isolation trenches with improved corners |
| US5868870A (en) * | 1992-12-10 | 1999-02-09 | Micron Technology, Inc. | Isolation structure of a shallow semiconductor device trench |
| EP0646956A2 (en) * | 1993-09-30 | 1995-04-05 | Motorola, Inc. | Trench isolation structure in an integrated circuit and method of formation |
| EP0646956A3 (en) * | 1993-09-30 | 1997-07-09 | Motorola Inc | Trench isolation structure in an integrated circuit and method of formation. |
| US5741738A (en) * | 1994-12-02 | 1998-04-21 | International Business Machines Corporation | Method of making corner protected shallow trench field effect transistor |
| US6423631B1 (en) | 1997-08-22 | 2002-07-23 | Micron Technology, Inc. | Isolation using an antireflective coating |
| US6121133A (en) * | 1997-08-22 | 2000-09-19 | Micron Technology, Inc. | Isolation using an antireflective coating |
| US6174590B1 (en) | 1997-08-22 | 2001-01-16 | Micron Technology, Inc. | Isolation using an antireflective coating |
| WO1999010918A1 (en) * | 1997-08-22 | 1999-03-04 | Micron Technology, Inc. | Process of isolation in integrated circuit fabrication, using an antireflective coating |
| US6605502B2 (en) | 1997-08-22 | 2003-08-12 | Micron Technology, Inc. | Isolation using an antireflective coating |
| US6495450B1 (en) | 1997-08-22 | 2002-12-17 | Micron Technology, Inc. | Isolation using an antireflective coating |
| KR19990057300A (en) * | 1997-12-29 | 1999-07-15 | 김영환 | Trench formation method with improved leakage characteristics |
| US6541843B2 (en) | 1998-09-03 | 2003-04-01 | Micron Technology, Inc. | Anti-reflective coatings and methods for forming and using same |
| US6673713B2 (en) | 1998-09-03 | 2004-01-06 | Micron Technology, Inc. | Anti-reflective coatings and methods for forming and using same |
| US6784094B2 (en) | 1998-09-03 | 2004-08-31 | Micron Technology, Inc. | Anti-reflective coatings and methods for forming and using same |
| US6444588B1 (en) | 1999-04-26 | 2002-09-03 | Micron Technology, Inc. | Anti-reflective coatings and methods regarding same |
| JP4955880B2 (en) * | 1999-08-30 | 2012-06-20 | スパンション エルエルシー | Method for fabricating an integrated circuit forming a trench in a substrate |
| CN100359665C (en) * | 2002-07-24 | 2008-01-02 | 三星电子株式会社 | Method for fabricating low well of semiconductor device using low energy ion implantation |
| JP2006078489A (en) * | 2004-09-08 | 2006-03-23 | Korea Electronics Telecommun | Device for measuring image and lifetime of display panel |
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