JPH0287677A - Non-volatile mos semiconductor memory - Google Patents
Non-volatile mos semiconductor memoryInfo
- Publication number
- JPH0287677A JPH0287677A JP63241406A JP24140688A JPH0287677A JP H0287677 A JPH0287677 A JP H0287677A JP 63241406 A JP63241406 A JP 63241406A JP 24140688 A JP24140688 A JP 24140688A JP H0287677 A JPH0287677 A JP H0287677A
- Authority
- JP
- Japan
- Prior art keywords
- silicon layer
- floating gate
- insulating film
- trench
- polycrystal silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000002955 isolation Methods 0.000 claims abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 12
- 229910052710 silicon Inorganic materials 0.000 abstract description 12
- 239000010703 silicon Substances 0.000 abstract description 12
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 5
- 239000012535 impurity Substances 0.000 abstract description 4
- 238000000059 patterning Methods 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract description 2
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 9
- 230000002093 peripheral effect Effects 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 3
- 210000004709 eyebrow Anatomy 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は不揮発性ＭＯＳ半導体記憶装置に関し、特にセ
ル・トラジスタのチャンネル領域と浮遊ゲート多結晶シ
リコン層を自己整合的に形成した記憶装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a nonvolatile MOS semiconductor memory device, and more particularly to a memory device in which a channel region of a cell transistor and a floating gate polycrystalline silicon layer are formed in a self-aligned manner.
従来、この種の不揮発性ＭＯＳ半導体記憶装置（以下Ｅ
ＰＲＯＭという）は、浮遊ゲート多結晶シリコン層を素
子分離絶縁膜上に面積の許す限り大きくオーバー・ラッ
プさせる構造が採られている。Conventionally, this type of nonvolatile MOS semiconductor memory device (hereinafter referred to as E
A PROM) has a structure in which a floating gate polycrystalline silicon layer overlaps an element isolation insulating film as much as the area allows.
第４図は従来の不揮発性ＭＯＳ半導体記憶装置のトラン
ジスタ・セル領域の断面図で、浮遊ゲート多結晶シリコ
ン層３と素子分離絶縁膜１２との関係をこのように設定
することにより、第２ゲート絶縁ＦＭ４で決定される浮
遊ゲートと制御ゲート間の容量を増加させ、読み出し時
に選択されたセルの浮遊ゲート電位をできる限り吊り上
げてチャンネルのオン電流を増やし、アクセス時間を短
縮させている。ここで、１はＰ型シリコン基板。FIG. 4 is a cross-sectional view of a transistor cell region of a conventional nonvolatile MOS semiconductor memory device. The capacitance between the floating gate and the control gate determined by the insulating FM 4 is increased, and the floating gate potential of the cell selected during reading is raised as much as possible to increase the on-current of the channel and shorten the access time. Here, 1 is a P-type silicon substrate.
２．５．６は第１ゲート絶縁膜、制御ゲート多結晶シリ
コン膜、眉間絶縁膜、また、７はアルミニウム配線（デ
イジット線）をそれぞれ示している６
〔発明が解決しようとする課題〕
しかし、近年記憶容量の大容量化に伴ないセル面積の縮
小化が進められており、この浮遊ゲート多結晶シリコン
層の素子分離絶縁股上へのオーバー・ラップ量を極力小
さくする必要が生じて来ている。しかしながら、この構
造の記憶装置では、最小でも浮遊ゲート多結晶シリコン
層と素子分離領域間の目合せマージン分のオーバー・ラ
ップ量だけは必要とするので、アクセス時間を短縮する
うえには効果があるものの、セル縮小化のためにはこの
ようにオーバー・ラップ・マージンを必要とすることが
大きな障害となっている。2.5.6 indicates the first gate insulating film, the control gate polycrystalline silicon film, the eyebrow insulating film, and 7 indicates the aluminum wiring (digit line)6 [Problem to be solved by the invention] However, In recent years, with the increase in memory capacity, the cell area has been reduced, and it has become necessary to minimize the amount of overlap between this floating gate polycrystalline silicon layer and the element isolation insulating layer. . However, in a memory device with this structure, at least an overlap amount equivalent to the alignment margin between the floating gate polycrystalline silicon layer and the element isolation region is required, so it is effective in shortening the access time. However, the need for such an overlap margin is a major obstacle to cell miniaturization.
本発明の目的は、上記の情況に鑑み、浮遊ゲート多結晶
シリコン層を素子分離絶縁股上にオーバー・ラップさせ
ることなくアクセス時間の短縮およびセル面積の縮小化
をそれぞれ達成し得るセル構造を備えた不揮発性ＭＯＳ
半導体記憶装置を提供することである。In view of the above circumstances, an object of the present invention is to provide a cell structure that can shorten access time and reduce cell area without overlapping a floating gate polycrystalline silicon layer with an element isolation insulating layer. Non-volatile MOS
An object of the present invention is to provide a semiconductor memory device.
本発明によれば、不揮発性ＭＯ８半導体記憶装置は、半
導体基板と、前記半導体基板上に隣接配置される浮遊ゲ
ート型ＥＰＲＯＭトランジスタ・セルとを含んで成り、
前記隣接するＥＰＲＯＭトランジスタ・セルは浮遊ゲー
ト多結晶シリコン層に対するトレンチ溝分離膜によって
互いに分離され、チャンネル領域と浮遊ゲート多結晶シ
リコン層とが自己整合的に形成されることを含んで構成
される。According to the present invention, a nonvolatile MO8 semiconductor memory device includes a semiconductor substrate and a floating gate EPROM transistor cell disposed adjacently on the semiconductor substrate,
The adjacent EPROM transistor cells are separated from each other by a trench isolation layer for the floating gate polycrystalline silicon layer, and the channel region and the floating gate polycrystalline silicon layer are formed in a self-aligned manner.
以下図面を参照して本発明の詳細な説明する。 The present invention will be described in detail below with reference to the drawings.
第１図＜ａ）および（ｂ）、（Ｃ）はそれぞれ本発明の
一実施例を示す不揮発性ＭＯＳトランジスタ・セル領域
の平面図およびそのＡ−Ａ’断面図、Ｂ−Ｂ’断面図で
ある。本実施例によれば、本発明の不揮発性ＭＯＳ半導
体記憶装置は、浮遊ゲート多結晶シリコン層３がトレン
チ溝８によって絶縁分離され、浮遊ゲートとチャネル領
域とが自己整合的に形成されたセル・トランジスタ配列
を含んで成る。ここでまず、この作り方について説明す
る。FIGS. 1A, 1B, and 1C are a plan view, an AA' sectional view, and a BB' sectional view, respectively, of a nonvolatile MOS transistor cell region showing one embodiment of the present invention. be. According to this embodiment, the nonvolatile MOS semiconductor memory device of the present invention is a cell in which the floating gate polycrystalline silicon layer 3 is insulated and separated by the trench groove 8, and the floating gate and channel region are formed in a self-aligned manner. It comprises an array of transistors. First, I will explain how to make this.
第２図（ａ）〜（ｆ）は上記実施例の製造方法の一つを
示す工程順序図である。まず、通常の手法によりＰ型シ
リコン基板１上にＥＰＲＯＭセルアレイ領域以外の素子
領域をロコス（ＬＯＣＯ３）法により形成し、後にＥＰ
ＲＯＭセルの第１ゲート絶縁膜２となる絶縁膜を熱酸化
法により形成する。ここで、１２はロコス法で形成され
た素子分離絶縁膜である。さらに、その上にＣＶＤ法に
より浮遊ゲート多結晶シリコン層３を堆積しＮ型不純物
を導入し、ついでパターニングを行なって所定のＥＰＲ
ＯＭセルアレイ領域のみに浮遊ゲートＮ型多結晶シリコ
ン層３を残す〔第２図（ａ））。FIGS. 2(a) to 2(f) are process flow diagrams showing one of the manufacturing methods of the above embodiment. First, an element area other than the EPROM cell array area is formed on a P-type silicon substrate 1 by the LOCO3 method using a conventional method, and then an EPROM cell array area is formed using the LOCO3 method.
An insulating film that will become the first gate insulating film 2 of the ROM cell is formed by thermal oxidation. Here, 12 is an element isolation insulating film formed by the LOCOS method. Furthermore, a floating gate polycrystalline silicon layer 3 is deposited thereon by CVD method, N-type impurities are introduced, and patterning is performed to achieve a predetermined EPR.
The floating gate N-type polycrystalline silicon layer 3 is left only in the OM cell array region [FIG. 2(a)].
次に基板全面にフォトレジストを被覆し、セルアレイ領
域上の溝を形成する領域のみに窓を開け、残りの領域は
全てフォトレジスト１３で覆う〔第２図（ｂ）〕。つい
でフォトレジスト１３をマスクとして異方性ドライエツ
チングを行い、浮遊ゲート多結晶シリコンＮ３．第１ゲ
ート絶縁膜２およびシリコン基板１を順次エツチングし
ておよそ５μｍ程度の深さのトレンチ溝８を形成する〔
第２図（ｃ））、その後、熱酸化法によってこの浮遊ゲ
ート多結晶シリコンＮ３上の第２ゲート絶縁膜４．トレ
ンチ溝８内の側壁絶縁膜および周辺トランジスタ部のゲ
ートの絶縁膜を同時に形成する。Next, the entire surface of the substrate is coated with photoresist, a window is opened only in the area where the groove is to be formed above the cell array area, and the remaining area is all covered with photoresist 13 (FIG. 2(b)). Next, anisotropic dry etching is performed using the photoresist 13 as a mask, and the floating gate polycrystalline silicon N3. The first gate insulating film 2 and the silicon substrate 1 are sequentially etched to form a trench groove 8 with a depth of approximately 5 μm.
2(c)), a second gate insulating film 4. is then formed on the floating gate polycrystalline silicon N3 by a thermal oxidation method. A sidewall insulating film in the trench groove 8 and an insulating film at the gate of the peripheral transistor section are formed at the same time.
ついでＣＶＤ法によりセルアレイ領域上に絶縁膜を堆積
させ、トレンチ溝８の内部までも完全に埋めた後、異方
性ドライエッチによりエッチバックを行ない、トレンチ
溝８内部にのみ絶縁膜を残す〔第２図（ｄ）〕。その後
さらにＣＶＤ法により多結晶シリコン層を堆積し、Ｎ型
不純物を導入してバターニングを行なってＥＰＲＯＭセ
ル上の制御ゲート多結晶シリコン層５と周辺トランジス
タのゲート電極１５をそれぞれ形成する。第２図（ｅ）
は、その後熱酸化を行なって制御ゲート多結晶シリコン
層５および周辺部のゲート電極１５の側面酸化膜を形成
した後の断面図である。その後、従来プロセスと同様に
周辺トランジスタのＮ型拡散層１４を設け、更にＣＶＤ
法により眉間絶縁膜６を形成してコンタクトを開孔しア
ルミ配線（デイジット線）７を設けることにより、第２
図（ｆ）に示すような断面構造を得る。第２図（ｆ）に
示す断面構造では、セル・トラジスタのそれぞれはトレ
ンチ溝８で浮遊ゲートと共に相互に分離されているので
、従来の如く浮遊グーＩ・多結晶シリコン層３の形成に
素子分離絶縁膜上べのオーバー・ラップ・マージンを全
く必要としない。従って、アクセス時間の短縮と共にセ
ル面積の縮・小化を図ることができる。Next, an insulating film is deposited on the cell array area by the CVD method, completely filling the inside of the trench groove 8, and then etched back by anisotropic dry etching to leave the insulating film only inside the trench groove 8. Figure 2 (d)]. Thereafter, a polycrystalline silicon layer is further deposited by the CVD method, and N-type impurities are introduced and patterning is performed to form the control gate polycrystalline silicon layer 5 on the EPROM cell and the gate electrode 15 of the peripheral transistor, respectively. Figure 2(e)
2 is a cross-sectional view after thermal oxidation is performed to form a side oxide film of the control gate polycrystalline silicon layer 5 and the gate electrode 15 in the peripheral area. After that, the N-type diffusion layer 14 of the peripheral transistor is provided as in the conventional process, and further CVD
By forming an insulating film 6 between the eyebrows by the method, opening a contact hole, and providing an aluminum wiring (digit line) 7, the second
A cross-sectional structure as shown in Figure (f) is obtained. In the cross-sectional structure shown in FIG. 2(f), each of the cells and transistors is separated from each other along with the floating gate by the trench groove 8, so that the formation of the floating goo I/polycrystalline silicon layer 3 is used to separate the elements. No overlap margin on the insulation film is required. Therefore, the access time can be shortened and the cell area can be reduced.
第３図は本発明を表面フラット型下揮発性ＭＯ８半導体
記憶装置に実施した場合の一実施例を示すトラジスタ・
セル領域の断面図である。本実施例によれば、前実施例
のワード線（制御ゲート）方向に対する縮小化に加えて
デイジット線方向に対する縮小化も図ることができる。FIG. 3 shows an example of a transistor and a transistor in which the present invention is applied to a flat-surface type volatile MO8 semiconductor memory device.
FIG. 3 is a cross-sectional view of a cell region. According to this embodiment, in addition to the reduction in the word line (control gate) direction of the previous embodiment, it is also possible to achieve reduction in the digit line direction.
この半導体構造は前実施例と同様Ｐ型シリコン基板１上
にセル・トラジスタを形成し、ＣＶＤ法により眉間絶縁
膜６を形成した後、異方性ドライエツチング法を用いて
テーパーをつけずに垂直にコンタクト孔をエツチング開
口し、ついでＣＶＤ法によって多結晶シリコン層を堆積
させてコンタクト部を完全に埋め、コンタクト抵抗を下
げるために不純物を添加した後エッチバックしてコンタ
クト部にのみＮ型ドープ多結晶シリコンＮ１１を残すこ
とによって作られる。この構造によれば、前実施例に比
べて眉間絶縁膜６のリフロー性やコンタクトのテーパー
形状を気にすることなく、浮遊ゲートとドレイン・コン
タクト１０との間隔を小さくすることが可能となるので
デイジット線方向にも縮小化され、またセルアレイ上は
、はぼ平坦となりアルミ配線のステップカバレッジが良
好となる。This semiconductor structure is constructed by forming a cell transistor on a P-type silicon substrate 1 as in the previous embodiment, forming a glabella insulating film 6 by the CVD method, and then using an anisotropic dry etching method to form a vertical film without a taper. A contact hole is opened by etching, and then a polycrystalline silicon layer is deposited by CVD to completely fill the contact area. After adding impurities to lower the contact resistance, it is etched back to form an N-type doped polycrystalline silicon layer only in the contact area. It is made by leaving crystalline silicon N11 behind. According to this structure, compared to the previous embodiment, it is possible to reduce the distance between the floating gate and the drain contact 10 without worrying about the reflowability of the glabella insulating film 6 or the tapered shape of the contact. The size is also reduced in the digit line direction, and the cell array becomes substantially flat, resulting in good step coverage of the aluminum wiring.
以上詳細に説明したように、本発明によれば、ＥＰＲＯ
Ｍセルトランジスタの素子領域において、浮遊ゲート多
結晶シリコン層をトレンチ溝を用いて隣接するセル領域
から分離する為、セルのチャンネル領域と浮遊ゲート多
結晶シリコン層とを同時に自己整合的に形成することが
できる。従って、従来の如く浮遊ゲート多結晶シリコン
層の素子分離絶縁膜上へのオーバー・ラップ・マージン
を考慮することなく製造することができる他、セル面積
が従来よりも一段と小さな高速記憶装置を得ることか可
能である。As explained in detail above, according to the present invention, EPRO
In order to separate the floating gate polycrystalline silicon layer from the adjacent cell region using a trench in the element region of the M cell transistor, the cell channel region and the floating gate polycrystalline silicon layer are simultaneously formed in a self-aligned manner. Can be done. Therefore, it is possible to manufacture the device without considering the overlap margin of the floating gate polycrystalline silicon layer on the element isolation insulating film as in the past, and also to obtain a high-speed memory device with a cell area much smaller than the conventional one. It is possible.
第１図（ａ）および（ｂ）、（ｃ）はそれぞれ本発明の
一実施例を示す不揮発性ＭＯＳトランジスタ・セル領域
の平面図およびＡ−Ａ′断面図、Ｂ−Ｂ’断面図、第２
図＜ａ）〜（ｆ＞は上記実施例の製造方法の一つを示す
工程順序図、第３図は本発明を表面フラット型下揮発性
ＭＯＳ半導体記憶装置に実施した場合の一実施例を示す
トランジスタ・セル領域の断面図、第４図は従来の不揮
発生ＭＯＳ半導体記憶装置のトランジスタ・セル領域の
断面図である。
１・・・Ｐ型シリコン基板、２・・・第１ゲート絶縁膜
、３・・・浮遊ゲート多結晶シリコン層、４・・・第２
ゲート絶縁膜、５・・・制御ゲート多結晶シリコン層、
６・・・眉間絶縁膜、７・・・アルミ配線（デイジッド
線）、８・・・トレンチ溝、９・・・Ｎ型拡散層（ソー
ス）、１０・・・Ｎ型拡散層（ドレイン）、１１・・・
Ｎ型ドープト多結晶シリコン層、１２・・・素子分離絶
縁膜、１３・・・フォトレジスト、１４・・・周辺部ト
ランジスタのＮ型拡散層、１５・・・周辺トランジスタ
のゲート電極。FIGS. 1(a), 1(b), and 1(c) are a plan view, an AA' sectional view, a BB' sectional view, and a BB' sectional view, respectively, of a nonvolatile MOS transistor cell region showing one embodiment of the present invention. 2
Figures <a) to (f> are process sequence diagrams showing one of the manufacturing methods of the above embodiment, and Figure 3 shows an example in which the present invention is applied to a flat surface type bottom volatile MOS semiconductor memory device. FIG. 4 is a cross-sectional view of the transistor cell region of a conventional non-volatile MOS semiconductor memory device. 1... P-type silicon substrate, 2... First gate insulating film , 3... floating gate polycrystalline silicon layer, 4... second
Gate insulating film, 5... control gate polycrystalline silicon layer,
6... Insulating film between eyebrows, 7... Aluminum wiring (digital line), 8... Trench groove, 9... N type diffusion layer (source), 10... N type diffusion layer (drain), 11...
N-type doped polycrystalline silicon layer, 12... Element isolation insulating film, 13... Photoresist, 14... N-type diffusion layer of peripheral transistor, 15... Gate electrode of peripheral transistor.
Claims (1)
ゲート型ＥＰＲＯＭトランジスタ・セルとを含んで成り
、前記隣接するＥＰＲＯＭトランジスタ・セルは浮遊ゲ
ート多結晶シリコン層に対するトレンチ溝分離膜によっ
て互いに分離され、チャンネル領域と浮遊ゲート多結晶
シリコン層とが自己整合的に形成されることを特徴とす
る不揮発性ＭＯＳ半導体記憶装置。a semiconductor substrate and floating gate EPROM transistor cells disposed adjacently on the semiconductor substrate, the adjacent EPROM transistor cells being separated from each other by a trench isolation layer for the floating gate polycrystalline silicon layer; A nonvolatile MOS semiconductor memory device characterized in that a channel region and a floating gate polycrystalline silicon layer are formed in a self-aligned manner.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63241406A JPH0287677A (en) | 1988-09-26 | 1988-09-26 | Non-volatile mos semiconductor memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63241406A JPH0287677A (en) | 1988-09-26 | 1988-09-26 | Non-volatile mos semiconductor memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0287677A true JPH0287677A (en) | 1990-03-28 |
Family
ID=17073811
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63241406A Pending JPH0287677A (en) | 1988-09-26 | 1988-09-26 | Non-volatile mos semiconductor memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0287677A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6060358A (en) * | 1997-10-21 | 2000-05-09 | International Business Machines Corporation | Damascene NVRAM cell and method of manufacture |
| JP2002252291A (en) * | 2001-02-27 | 2002-09-06 | Mitsubishi Electric Corp | Nonvolatile semiconductor memory device and its fabrication method |
| JP2002313962A (en) * | 2001-04-11 | 2002-10-25 | Mitsubishi Electric Corp | Nonvolatile semiconductor storage device |
-
1988
- 1988-09-26 JP JP63241406A patent/JPH0287677A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6060358A (en) * | 1997-10-21 | 2000-05-09 | International Business Machines Corporation | Damascene NVRAM cell and method of manufacture |
| JP2002252291A (en) * | 2001-02-27 | 2002-09-06 | Mitsubishi Electric Corp | Nonvolatile semiconductor memory device and its fabrication method |
| JP2002313962A (en) * | 2001-04-11 | 2002-10-25 | Mitsubishi Electric Corp | Nonvolatile semiconductor storage device |
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