JPH028227U - - Google Patents
Info
- Publication number
- JPH028227U JPH028227U JP8570888U JP8570888U JPH028227U JP H028227 U JPH028227 U JP H028227U JP 8570888 U JP8570888 U JP 8570888U JP 8570888 U JP8570888 U JP 8570888U JP H028227 U JPH028227 U JP H028227U
- Authority
- JP
- Japan
- Prior art keywords
- timer
- selection
- time data
- storage means
- repeat
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Measurement Of Predetermined Time Intervals (AREA)
- Electronic Switches (AREA)
Description
第１図は本考案の一実施例を示す電子腕時計の
外観図、第２図は第１図の腕時計の表示パネルの
表示例を示す図、第３図は第１図に示した電子腕
時計の回路構成図、第４図は第３図に示した回路
構成図におけるＲＡＭ９の内容を表わす図、第５
図は全体の処理フローチヤート、第６図はキー処
理フローチヤート、第７図はタイマ処理フローチ
ヤートである。
４……キー入力部、５……表示部、６……ＲＯ
Ｍアドレス制御部、７……演算回路、８……ＲＯ
Ｍ、９……ＲＡＭ、１６……ブザー、ＳＷ１……
モード切換スイツチ、ＳＷ２……スタート・スト
ツプスイツチ、ＳＷ３……リピート切換スイツチ
、Ｒ……繰り返しモードフラグ、Ｎａ，Ｎｂ……
タイマデータフラグ。
Fig. 1 is an external view of an electronic wristwatch showing an embodiment of the present invention, Fig. 2 is a view showing an example of the display panel of the wristwatch shown in Fig. 1, and Fig. 3 is an external view of the electronic wristwatch shown in Fig. 1. A circuit configuration diagram, FIG. 4 is a diagram showing the contents of RAM 9 in the circuit configuration diagram shown in FIG.
This figure is an overall processing flowchart, FIG. 6 is a key processing flowchart, and FIG. 7 is a timer processing flowchart. 4...Key input section, 5...Display section, 6...RO
M address control unit, 7... Arithmetic circuit, 8... RO
M, 9...RAM, 16...Buzzer, SW1...
Mode changeover switch, SW2...Start/stop switch, SW3...Repeat changeover switch, R...Repeat mode flag, Na, Nb...
Timer data flag.
Claims (1)
憶手段と、単発タイマ及び繰り返しタイマのいず
れか一方を選択する選択手段と、 前記複数の記憶手段に記憶されているタイマ時
間データを用いて前記選択手段による選択に基づ
き単発タイマ動作又は繰り返しタイマ動作を実行
させる制御手段とを具備したことを特徴とするタ
イマ装置。[Claims for Utility Model Registration] A plurality of storage means each storing timer time data, selection means for selecting either a single timer or a repeat timer, and timer time data stored in the plurality of storage means. and control means for executing a single timer operation or a repeated timer operation based on the selection by the selection means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8570888U JPH028227U (en) | 1988-06-30 | 1988-06-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8570888U JPH028227U (en) | 1988-06-30 | 1988-06-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH028227U true JPH028227U (en) | 1990-01-19 |
Family
ID=31310361
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8570888U Pending JPH028227U (en) | 1988-06-30 | 1988-06-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH028227U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1176536A (en) * | 1998-07-29 | 1999-03-23 | Sankyo Kk | Game machine |
-
1988
- 1988-06-30 JP JP8570888U patent/JPH028227U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1176536A (en) * | 1998-07-29 | 1999-03-23 | Sankyo Kk | Game machine |