JPH0275593U - - Google Patents
Info
- Publication number
- JPH0275593U JPH0275593U JP15305088U JP15305088U JPH0275593U JP H0275593 U JPH0275593 U JP H0275593U JP 15305088 U JP15305088 U JP 15305088U JP 15305088 U JP15305088 U JP 15305088U JP H0275593 U JPH0275593 U JP H0275593U
- Authority
- JP
- Japan
- Prior art keywords
- correction
- signal
- counter
- generated
- reference signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Electric Clocks (AREA)
Description
第１図は本考案の一実施例に係る時計の修正回
路の回路図、第２図は第１図に示す修正回路を含
む時計の回路構成を示す図、第３図Ａ及びＢはタ
イムチヤートである。
２……基準信号発生器、８……時刻カウンタ、
２２……表示部、Ｍ，Ｈ……修正スイツチ、３０
，３２……修正回路、３４……第１のカウンタ、
４８……修正モード切換回路、５４……修正信号
発生回路、６０……第２のカウンタ、７０……リ
セツト回路。
Fig. 1 is a circuit diagram of a correction circuit of a watch according to an embodiment of the present invention, Fig. 2 is a diagram showing the circuit configuration of a watch including the correction circuit shown in Fig. 1, and Figs. 3A and B are time charts. It is. 2...Reference signal generator, 8...Time counter,
22... Display unit, M, H... Correction switch, 30
, 32... correction circuit, 34... first counter,
48... Correction mode switching circuit, 54... Correction signal generation circuit, 60... Second counter, 70... Reset circuit.
Claims (1)
時刻カウンタと、 この時刻カウンタで計時された時刻を表示する
表示部と、 各時刻桁に対応する修正スイツチと、 この修正スイツチのオン操作により前記時刻カ
ウンタに修正信号を供給する修正回路と、 から成る時計において、 前記修正回路が、 前記修正スイツチのオン操作時でかつカウント
値が設定値以外の時のみ前記基準信号発生器から
の基準信号をカウントし、そのカウント値が設定
値となつた時に信号を出力すると共にカウントを
停止する第１のカウンタと、 この第１のカウンタからの出力信号発生時のみ
動作可能となり、この後の修正スイツチのオフ操
作に応答して修正可能信号を出力する修正モード
切換回路と、 この修正モード切換回路からの修正可能信号及
び前記修正スイツチのオン操作信号により修正信
号を発生する修正信号発生回路と、 前記第１のカウンタの出力信号発生時でかつカ
ウント値が設定値以外の時のみ前記基準信号発生
器からの基準信号のカウントを行ない、このカウ
ント値が設定値になつた時にカウントを停止する
と共に前記第１のカウンタのカウント値をクリア
する出力信号を発生する第２のカウンタと、 前記修正モード切換回路からの修正可能信号発
生時でかつ修正スイツチからのオン操作信号発生
時あるいは修正スイツチからのオン操作信号非発
生時でかつ前記第１のカウンタの出力信号非発生
時にのみ前記第２のカウンタをリセツトするリセ
ツト回路と、 から成ることを特徴とする時計の修正回路。[Claims for Utility Model Registration] A reference signal generator that generates a reference signal, a time counter that receives this reference signal and counts each time digit, and a display section that displays the time measured by the time counter; A timepiece comprising: a correction switch corresponding to each time digit; and a correction circuit that supplies a correction signal to the time counter when the correction switch is turned on; a first counter that counts the reference signal from the reference signal generator only when the value is other than the set value, and outputs a signal and stops counting when the counted value reaches the set value; a correction mode switching circuit that becomes operable only when an output signal is generated from the counter and outputs a correction enable signal in response to a subsequent OFF operation of the correction switch; a correction signal generating circuit that generates a correction signal in response to an ON operation signal of the first counter; and a correction signal generation circuit that counts the reference signal from the reference signal generator only when the output signal of the first counter is generated and the count value is other than the set value. , a second counter that stops counting when the count value reaches a set value and generates an output signal that clears the count value of the first counter; and when a correction enable signal is generated from the correction mode switching circuit. and a reset circuit that resets the second counter only when the on-operation signal is generated from the correction switch or when the on-operation signal is not generated from the correction switch and when the output signal of the first counter is not generated. A clock correction circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15305088U JPH0275593U (en) | 1988-11-26 | 1988-11-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15305088U JPH0275593U (en) | 1988-11-26 | 1988-11-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0275593U true JPH0275593U (en) | 1990-06-08 |
Family
ID=31428538
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15305088U Pending JPH0275593U (en) | 1988-11-26 | 1988-11-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0275593U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016031273A (en) * | 2014-07-29 | 2016-03-07 | カシオ計算機株式会社 | Electronic clock |
| JP2016520189A (en) * | 2013-04-24 | 2016-07-11 | ウーテーアー・エス・アー・マニファクチュール・オロロジェール・スイス | How to operate an electronic device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5124200A (en) * | 1974-08-21 | 1976-02-26 | Omron Tateisi Electronics Co | Noriaibasuteino jikokuhyojisochi |
| JPS5199566A (en) * | 1975-02-27 | 1976-09-02 | Citizen Watch Co Ltd |
-
1988
- 1988-11-26 JP JP15305088U patent/JPH0275593U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5124200A (en) * | 1974-08-21 | 1976-02-26 | Omron Tateisi Electronics Co | Noriaibasuteino jikokuhyojisochi |
| JPS5199566A (en) * | 1975-02-27 | 1976-09-02 | Citizen Watch Co Ltd |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016520189A (en) * | 2013-04-24 | 2016-07-11 | ウーテーアー・エス・アー・マニファクチュール・オロロジェール・スイス | How to operate an electronic device |
| JP2016031273A (en) * | 2014-07-29 | 2016-03-07 | カシオ計算機株式会社 | Electronic clock |