JPH027182B2 - - Google Patents
Info
- Publication number
- JPH027182B2 JPH027182B2 JP59227800A JP22780084A JPH027182B2 JP H027182 B2 JPH027182 B2 JP H027182B2 JP 59227800 A JP59227800 A JP 59227800A JP 22780084 A JP22780084 A JP 22780084A JP H027182 B2 JPH027182 B2 JP H027182B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- external lead
- region
- metal
- silicon substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 31
- 229910052751 metal Inorganic materials 0.000 claims description 27
- 239000002184 metal Substances 0.000 claims description 27
- 239000008188 pellet Substances 0.000 claims description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 15
- 150000002739 metals Chemical class 0.000 claims description 5
- 238000010292 electrical insulation Methods 0.000 claims description 2
- 238000000605 extraction Methods 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/492—Bases or plates or solder therefor
- H01L23/4924—Bases or plates or solder therefor characterised by the materials
- H01L23/4926—Bases or plates or solder therefor characterised by the materials the materials containing semiconductor material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】
［産業上の利用分野］
この発明は、半導体装置の外部引出し電極、特
に半導体ペレツトの一主面側に２つの互いに異な
る領域が複数に島状に分割されて配置されこの共
通領域に設けたそれぞれの電極金属と電気的接続
を図つて外部へ引き出す外部引出し電極の構造を
改良した半導体装置に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention provides an external extraction electrode of a semiconductor device, in particular, a semiconductor pellet in which two different regions are divided into a plurality of islands and arranged on one main surface side of the semiconductor pellet. The present invention relates to a semiconductor device having an improved structure of external lead-out electrodes that are electrically connected to respective electrode metals provided in this common area and drawn out to the outside.
［従来の技術］
電力用トランジスタ、ダーリトントランジス
タ、ゲート・ターン・オフ・サイリスタ（GTO）
特大容量の半導体装置では、一般に半導体ペレツ
トの一主面側に２つの互いに異なる領域が島状に
分割されて形成され互いに入り組んだ複雑なパタ
ーン形状となり、この領域上の電極金属も微細か
つ複雑な形状となつている。かかる電極金属には
これらと電気的に接続される外部引出し電極が設
けられるが、前記のように電極金属が微細かつ複
雑な形状をしているために一般に次のような方策
がとられている。[Prior art] Power transistors, Darliton transistors, gate turn-off thyristors (GTO)
In a semiconductor device with an extra large capacity, two mutually different regions are generally formed on one main surface of a semiconductor pellet divided into islands, resulting in a complicated pattern shape that is intricate with each other, and the electrode metal on these regions is also fine and complicated. It has a shape. These electrode metals are provided with external lead-out electrodes that are electrically connected to them, but since the electrode metals have minute and complicated shapes as mentioned above, the following measures are generally taken. .
複数に分割された複雑なパターン形状の電極
金属に直接外部引出し電極を取付けることは困
難であるために、アルミ（Al）線、金線
（Au）を用いてワイヤボンデイグ法、超音波
法、熱圧着法等により各島間を電気的に接続
し、いずれか１つの島から集中的に外部へ引出
すための外部引出し電極を設けている。 Since it is difficult to directly attach an external lead electrode to an electrode metal with a complex pattern divided into multiple parts, wire bonding method, ultrasonic method, and thermocompression bonding method using aluminum (Al) wire and gold wire (Au) are used. Each island is electrically connected by a method or the like, and an external extraction electrode is provided for intensively extracting the energy from any one island to the outside.
一導電型領域上の島パターン形状に合わせて
金属板を微細加工し、この金属板を介して外部
引出し電極を取付けている。 A metal plate is microfabricated to match the shape of the island pattern on the one conductivity type region, and an external extraction electrode is attached via this metal plate.
［発明が解決しようとする問題点］
上記の場合、分割された島の数が多くなれば
なるほど、配線用のワイヤの数が多くなり、信頼
性の問題や１つの半導体ペレツト内に複数の半導
体装置を作り込んであるものにあつては互いのワ
イヤ間を電気的に接続しなければならず、一層全
体の構成を複雑化、組立作業の煩雑化等を避けら
れないという問題点があつた。[Problems to be Solved by the Invention] In the above case, as the number of divided islands increases, the number of wiring wires increases, leading to reliability problems and problems with multiple semiconductors in one semiconductor pellet. In the case of devices that are built-in, it is necessary to electrically connect the wires to each other, which inevitably makes the overall configuration even more complicated and the assembly work more complicated. .
また、上記の場合まず、金属板の前記パター
ン形状に合わせた微細加工がきわめて困難であ
り、さらに組立時に両パターンの位置合せが難し
く、極端な場合には位置ずれによる短絡事故等も
招来するという問題点があつた。 In addition, in the above case, firstly, it is extremely difficult to perform microfabrication to match the pattern shape of the metal plate, and furthermore, it is difficult to align both patterns during assembly, and in extreme cases, short circuit accidents due to misalignment may occur. There was a problem.
この発明は上記のような問題点を解消るために
なされたもので、半導体ペレツトの一主面上の２
つの互いに異なる導電型領域から容易に取り出す
ことができる外部引出し電極構造を有する半導体
装置を堤供することを目的とするものである。 This invention was made to solve the above-mentioned problems.
It is an object of the present invention to provide a semiconductor device having an external extraction electrode structure that can be easily taken out from two mutually different conductivity type regions.
［問題点を解決するための手段］
この発明にかかる半導体装置は、半導体ペレツ
トの一主面側に露出した２つの互いに異なる導電
型領域に対して１枚のシリコン基板から成る外部
引出し電極板を設け、上記半導体ペレツトの一主
面側に載置したものである。[Means for Solving the Problems] A semiconductor device according to the present invention includes an external lead electrode plate made of one silicon substrate for two regions of different conductivity types exposed on one main surface side of a semiconductor pellet. and placed on one main surface side of the semiconductor pellet.
［作 用］
外部引出し電極板としてのシリコン基板内にＰ
−Ｎ接合を作り込み互いに絶縁しつつ１枚のシリ
コン基板により、半導体ペレツトの一主面側の互
いに異なる領域から電極を引き出す。[Function] P in the silicon substrate as an external lead electrode plate.
Electrodes are drawn out from different regions on one main surface side of the semiconductor pellet using a single silicon substrate while forming -N junctions and insulating them from each other.
［実施例］
第１図は、本発明に係る半導体装置を概略的に
示した断面図である。[Example] FIG. 1 is a cross-sectional view schematically showing a semiconductor device according to the present invention.
同図において、半導体ペレツト１には、熱拡散
法等により、例えば電力用トランジスタではコレ
クタ領域２、ベース領域３、このベース領域３内
に互いに分離された島状のエミツタ領域４が形成
されている。 In the figure, a semiconductor pellet 1 has a collector region 2, a base region 3, and an island-shaped emitter region 4 separated from each other in the base region 3, for example, in a power transistor, formed by thermal diffusion method or the like. .
こうして半導体ペレツト１の一主面側ではベー
ス領域３とエミツタ領域４とが同一平面上に互い
に入り組んだ形で現われる。この同一平面上のベ
ース領域３およびエミツタ領域上にはそれぞれ金
属電極５，６が設けられ、また反対主面側のコレ
クタ領域上にも金属電極７が設けられる。 In this way, on one main surface side of the semiconductor pellet 1, the base region 3 and the emitter region 4 appear on the same plane in a mutually intertwined manner. Metal electrodes 5 and 6 are provided on the base region 3 and emitter region on the same plane, respectively, and a metal electrode 7 is also provided on the collector region on the opposite main surface side.
上記エミツタ領域４の金属電極６上に外部引出
し電極板７が設けられるこの外部引出し電極板
７′の素材はシリコン基材から成り、ベース領域
３およびエミツタ領域４の金属電極５，６のパタ
ーン形状に合せた形状に形成れる。 An external extraction electrode plate 7 is provided on the metal electrode 6 of the emitter area 4. The material of this external extraction electrode plate 7' is made of a silicon base material, and the pattern shape of the metal electrodes 5 and 6 of the base area 3 and the emitter area 4 is It can be formed into a shape to suit.
すなわち、外部引出電極板７′は、低抵抗のシ
リコン基板から成り、例えば比抵抗３〜15／1000
Ω・cm厚さ300μｍの型シリコン基板を用い、通
常のフオト・リソ技術、選択拡散法等によりベー
ス領域３に対応する位置にＰ型拡散領域８を形成
し、次いで、このＰ型拡散領域８内にN+拡散領
域９を作り込む。N+拡散領域９は電極板７′内で
すべて連結されている。 That is, the external lead electrode plate 7' is made of a low-resistance silicon substrate, and has a specific resistance of 3 to 15/1000, for example.
Using a type silicon substrate with a thickness of 300 μm in Ωcm, a P-type diffusion region 8 is formed at a position corresponding to the base region 3 by ordinary photolithography technology, selective diffusion method, etc., and then this P-type diffusion region 8 is An N + diffusion region 9 is created inside. The N + diffusion regions 9 are all connected within the electrode plate 7'.
このＰ−Ｎ接合の作り込みはエミツタ領域４と
絶縁分離した外部引出し電極を形成するためであ
る。 The purpose of creating this P-N junction is to form an external lead electrode that is insulated and separated from the emitter region 4.
シリコン基板から成る外部引出電極板７′の一
部には段差１０が設けられこの段差１０のN+領
域９上に設けた電極１１からリード線１２等を引
出す。ベース電極はベース領域４−電極金属６−
電極金属１４−電極板７′のN+領域−電極金属１
５の経路で外部と接する。 A step 10 is provided in a part of the external lead electrode plate 7' made of a silicon substrate, and a lead wire 12 and the like are led out from an electrode 11 provided on the N + region 9 of the step 10. The base electrode is the base region 4 - electrode metal 6 -
Electrode metal 14 - N + area of electrode plate 7' - Electrode metal 1
Contact with the outside through route 5.
上記のベース領域３、エミツタ領域４の上の金
属電極５，６のパターン形状に合せてシリコン基
板から成る外部引出し電極板７′の表面上にも金
属電極１３，１４が形成されこれらの金属電極
５，１３および６，１４がそれぞれ例えばすず−
鉛（Sn−Pb）系低温ソルダを介して重ね合せ零
囲気炉等を通して外部引出し電極板７′と半導体
ペレツト１とを一体的に接着する。 Metal electrodes 13 and 14 are also formed on the surface of the external lead electrode plate 7' made of a silicon substrate in accordance with the pattern shape of the metal electrodes 5 and 6 on the base region 3 and emitter region 4, and these metal electrodes 5, 13 and 6, 14 are each, for example, tin-
The external lead electrode plate 7' and the semiconductor pellet 1 are integrally bonded together using a lead (Sn--Pb)-based low-temperature solder in a stacked zero-air furnace or the like.
なお、外部引出し電極板７′はその外側に配置
される銅等から成る電極ポスト（図示せず）に接
着若しくは圧接される。 Note that the externally drawn electrode plate 7' is bonded or pressed to an electrode post (not shown) made of copper or the like and arranged on the outside thereof.
この発明は上記のように外部引出し電極板７′
をシリコン基板で構成したものであるが、使用す
るシリコン基板の厚さが200〜300μｍ程度と簿い
ために抵抗率の点からは実用上殆んど問題がな
い。 As described above, this invention provides an external extraction electrode plate 7'.
is constructed from a silicon substrate, but since the thickness of the silicon substrate used is approximately 200 to 300 μm, there is practically no problem in terms of resistivity.
すなわち、比抵抗1.2×10-2Ω／cm、厚さ300μ
ｍの単位断面積（cm2）当りの抵抗率は3.6×10-4
Ω程度であり、殆んど問題はない。 That is, specific resistance 1.2×10 -2 Ω/cm, thickness 300μ
The resistivity per unit cross-sectional area (cm 2 ) of m is 3.6×10 -4
It is about Ω, so there is almost no problem.
また、この抵抗分が電力用トランジスタ、ダー
リントントランジスタ等において一種のバランス
抵抗となつて特定個所への電流集中を防ぎ、半導
体装置の電気的特性を改善できる効果がある。 In addition, this resistance acts as a kind of balance resistance in power transistors, Darlington transistors, etc., and prevents current concentration at specific locations, thereby improving the electrical characteristics of the semiconductor device.
さらに従来の１個所又は複数個所から引出すも
にあつては、電極金属のパターン形状が複雑な場
合には各電極金属と導通領域との間に横方向抵抗
が生じ電流特性を落す原因ともなつていたが、上
記の実施例の場合、全電極と金属接触するので、
そのようなこともない。 Furthermore, in the case of conventional devices that are drawn from one or multiple locations, if the pattern of the electrode metal is complex, lateral resistance occurs between each electrode metal and the conductive region, causing a drop in current characteristics. However, in the case of the above example, since all electrodes are in metal contact,
There is no such thing.
また、ベース領域３、エミツタ領域４の外部引
出し電極を同一のシリコン基板によつて形成して
いるが、ベースエミツタ間の耐圧は、例えば20V
程度あれば足り、したがつてこの実施例のような
Ｐ−Ｎ接合の作り込みにより両者の絶縁分離が十
分可能である。 Furthermore, although the external lead electrodes of the base region 3 and emitter region 4 are formed of the same silicon substrate, the withstand voltage between the base and emitter is, for example, 20V.
Therefore, it is possible to sufficiently insulate and separate the two by forming a P-N junction as in this embodiment.
なお、上記の実施例では電力用トランジスタを
例にして説明したが、勿論他の半導体装置、例え
ばGTOにも適用できるし、また１つの半導体ペ
レツト内に複数の半導体装置を作り込んだような
ものにも利用できる。さらにシリコン基板から成
る外部引出し電極も必ずしも一体的である必要な
はく複数に分割して使用することができる。 Although the above embodiment is explained using a power transistor as an example, it can of course be applied to other semiconductor devices, such as GTO, and also to devices in which multiple semiconductor devices are fabricated in one semiconductor pellet. It can also be used for Furthermore, the external lead electrode made of a silicon substrate is not necessarily integral, but can be divided into a plurality of pieces for use.
［発明の効果］
この発明は、上記のように半導体ペレツトの一
主面上に２つの異なる導電型領域を有するものの
外部引出し電極として同一のシリコン基板を使用
し内部のＰ−Ｎ接合によつて電気的に絶縁するよ
うにしたので半導体装置の構成が簡単となり、さ
らに外部引出し電極をシリコン基板で形成するよ
うにしたので、半導体ペレツトの金属電極が複雑
なパターン形状をしていてもフオト・リソ技術、
エツチング処理技術により容易に微細加工がで
き、前記パターン形状に合せた形状の外部引出し
電極を容易に形成することができる。しかもこの
場合に形成された外部引出し電極が全面で半導体
ペレツトの電極金属に接続されるために従来のよ
うに横抵抗を生じさせず、電力用トランジスタ、
ダーリントントランジスタでは全エミツタ領域か
ら効率良く電流が集められ、したがつてこれによ
り、電気的特性が改善され、また、GTO等のサ
イリスタではサージ耐量が向上する等の効果があ
る。[Effects of the Invention] The present invention has two different conductivity type regions on one main surface of a semiconductor pellet as described above, but uses the same silicon substrate as an external lead electrode and uses an internal P-N junction. Electrical insulation simplifies the structure of the semiconductor device, and since the external lead electrodes are formed on a silicon substrate, even if the metal electrodes of the semiconductor pellet have a complicated pattern, they can be easily used in photolithography. technology,
Microfabrication can be easily performed using etching processing technology, and an external lead-out electrode having a shape matching the pattern shape can be easily formed. Moreover, since the external lead electrode formed in this case is connected to the electrode metal of the semiconductor pellet over the entire surface, lateral resistance does not occur as in the conventional case, and the power transistor,
Darlington transistors efficiently collect current from the entire emitter region, which improves electrical characteristics, and thyristors such as GTOs have effects such as improved surge resistance.
第１図は、この発明の一実施例を示す半導体装
置の概略構造の断面図である。図において、１は
半導体ペレツト、２はコレクタ領域、３はベース
領域、４はエミツタ領域、５，６は金属電極、
７′はシリコン基板から成る外部引出し電極板、
８はＰ型領域、９はN+領域、１３，１４は金属
電極である。
FIG. 1 is a cross-sectional view of a schematic structure of a semiconductor device showing an embodiment of the present invention. In the figure, 1 is a semiconductor pellet, 2 is a collector region, 3 is a base region, 4 is an emitter region, 5 and 6 are metal electrodes,
7' is an external lead electrode plate made of a silicon substrate;
8 is a P type region, 9 is an N + region, and 13 and 14 are metal electrodes.
Claims (1)
つの導電型領域が形成されこの領域上に電極金属
が設けられさらにこれらの電極金属上にそれぞれ
外部引出し電極が設けられる半導体装置におい
て、前記外部引出し電極を互いに異なる２つの導
電型領域に対して電気的に絶縁するために内部に
Ｐ−Ｎ接合を設けた一枚のシリコン基板で構成し
た電極板を前記半導体ペレツトの一主面側上に載
置したことを特徴とする半導体装置。1 Different 2 parts on one main surface side of the semiconductor pellet
In a semiconductor device in which two conductivity type regions are formed, electrode metals are provided on these regions, and external lead electrodes are provided respectively on these electrode metals, the external lead electrodes are electrically connected to two different conductivity type regions. 1. A semiconductor device, characterized in that an electrode plate made of a single silicon substrate with a P-N junction provided therein for electrical insulation is placed on one main surface side of the semiconductor pellet.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59227800A JPS61107753A (en) | 1984-10-31 | 1984-10-31 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59227800A JPS61107753A (en) | 1984-10-31 | 1984-10-31 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61107753A JPS61107753A (en) | 1986-05-26 |
| JPH027182B2 true JPH027182B2 (en) | 1990-02-15 |
Family
ID=16866582
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59227800A Granted JPS61107753A (en) | 1984-10-31 | 1984-10-31 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61107753A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0418074U (en) * | 1990-06-05 | 1992-02-14 |
-
1984
- 1984-10-31 JP JP59227800A patent/JPS61107753A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0418074U (en) * | 1990-06-05 | 1992-02-14 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61107753A (en) | 1986-05-26 |
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