JPH0266991A - Surface mounting ceramic substrate - Google Patents

Surface mounting ceramic substrate

Info

Publication number
JPH0266991A
JPH0266991A JP21879088A JP21879088A JPH0266991A JP H0266991 A JPH0266991 A JP H0266991A JP 21879088 A JP21879088 A JP 21879088A JP 21879088 A JP21879088 A JP 21879088A JP H0266991 A JPH0266991 A JP H0266991A
Authority
JP
Japan
Prior art keywords
black
overglaze
ceramic
ceramic substrate
components
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21879088A
Other languages
Japanese (ja)
Inventor
Takao Oiwa
大岩 隆夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Radio Co Ltd
Original Assignee
Japan Radio Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Japan Radio Co Ltd filed Critical Japan Radio Co Ltd
Priority to JP21879088A priority Critical patent/JPH0266991A/en
Publication of JPH0266991A publication Critical patent/JPH0266991A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0201Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To decrease the temperature difference between components as far as possible and to prevent excessive heating by providing a black overglaze part around a part whose radiated energy absorbing rate is low on a ceramic circuit substrate. CONSTITUTION:A black overglaze part 7 is provided around the mounting part of a white ceramic chip carrier 4. Thus, the energy absorbing rate of infrared rays is improved. In this way, temperature difference between the part 7 and a QFP 3 is eliminated by the radiated heat from the components and heat conduction from the black overglaze part 7. Solderging can be performed at the uniform temperature. A highly reliable double-mounting type substrate can be obtained.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は表面実装部品を搭載したセラミックス回路基板
に関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a ceramic circuit board on which surface-mounted components are mounted.

(従来の技術とその課題) セラミックス回路基板に表面実装部品を半田付けする方
法としてはセラミックス回路基板に搭載するICやトラ
ンジスタなどの部品の電極部に相当する該セラミックス
基板のラウンド部にクリーム半田を印刷し、該部品を搭
載し、輻射加熱である赤外線コンベヤー類で加熱し、半
田を溶融させて接続する手法が最も一般的である。
(Prior art and its problems) A method of soldering surface mount components to a ceramic circuit board is to apply cream solder to the round part of the ceramic circuit board, which corresponds to the electrode part of components such as ICs and transistors mounted on the ceramic circuit board. The most common method is to print the parts, mount them, heat them with an infrared conveyor that uses radiation heating, and melt the solder to connect them.

従来80ビンや100ビンの出力端子のある黒色の樹脂
でモールドされたQ F P (Quad F lat
 Package )と白色セラミックスを外囲器とす
るチップキャリアなど被輻射面積の大きな部品を混載す
る場合、半田リフロ一部の加熱に利用されている近赤外
線は輻射エネルギー密度が高く、又色によるエネルギー
吸収が異なるためセラミックス回路基板やセラミックス
を外囲器とした部品よりQFPのパッケージ部のエネル
ギー吸収率が大きい為、他の部品より早く温度が上昇す
る。一方白色セラミックス部品は輻射エネルギー吸収率
がきわめて悪いため、QFPと白色セラミックスを外囲
器とした部品とに温度差が生じる結果搭載部品の半田溶
融時間が違って来る。このためQFPは過度の加熱状態
となり樹脂モールドとセラミックス回路基板との熱膨張
差により残存歪が大となり、熱履歴を加えた場合接合部
分の剥離など不具合を発生することがあった。
Conventionally, QF P (Quad F lat
When mounting components with a large radiated area, such as a chip carrier with a white ceramic envelope, the near-infrared rays used to heat parts of the solder reflow have a high radiant energy density, and energy absorption due to color Since the QFP package has a higher energy absorption rate than a ceramic circuit board or a component with a ceramic envelope, the temperature rises faster than other components. On the other hand, since white ceramic parts have extremely poor radiant energy absorption rate, there is a temperature difference between the QFP and the part whose envelope is made of white ceramic, resulting in a difference in the solder melting time of the mounted parts. For this reason, the QFP becomes excessively heated, resulting in large residual strain due to the difference in thermal expansion between the resin mold and the ceramic circuit board, and when thermal history is applied, problems such as peeling of the bonded portion may occur.

第2図は従来の両面実装セラミックス基板の断面図を示
す。セラミックス基板(1)上に厚膜により回路及び部
品半田付ラウンド(2)(5)が印刷焼成により構成さ
れその後ソルダーストップも兼て、オーバーグレーズ(
6)が印刷焼成される。該基板上にクリーム半田を印刷
し、QFP(3)や白色セラミックを外囲器とするチッ
プキャリア(4)その他の部品を搭載して赤外線加熱コ
ンベヤー炉で赤外線輻射加熱し、クリーム半田を溶融し
て半田付を行う。
FIG. 2 shows a cross-sectional view of a conventional double-sided mounting ceramic substrate. Rounds (2) and (5) for soldering circuits and components are printed and fired using a thick film on the ceramic substrate (1), and then an overglaze (
6) is printed and fired. Cream solder is printed on the board, QFP (3), a chip carrier (4) with a white ceramic envelope, and other parts are mounted, and the cream solder is melted by infrared radiant heating in an infrared heating conveyor furnace. soldering.

この場合、加熱は輻射方式であり、材質、表面賦況、色
相などによって輻射エネルギー吸収率が非常に違ってく
る為、個々に昇温状態の違いが発生する。能動素子をパ
ッケージしているエポキシ樹脂は黒色で要路面が無光沢
であることにより白色セラミックチップキャリア(4)
よりも早く昇温し過加熱となる。このためモールド内の
能動素子に過度の熱歪が加わったり基板とモールド樹脂
の熱膨張歪がより大きくなり、半田接合部に残存歪が発
生し信頼性を低下させる原因となっている。
In this case, heating is done by radiation, and since the radiant energy absorption rate varies greatly depending on the material, surface condition, hue, etc., the heating state differs from case to case. The epoxy resin that packages the active elements is black and the main surface is matte, making it a white ceramic chip carrier (4).
The temperature rises faster than that, resulting in overheating. For this reason, excessive thermal strain is applied to the active elements in the mold, and thermal expansion strain between the substrate and the mold resin becomes larger, and residual strain occurs in the solder joint, causing a decrease in reliability.

(課題を解決するための手段) 本発明はこれらの欠点を解決するために、セラミックス
回路基板の輻射エネルギー吸収率の低い部品の周囲に黒
色のオーバークレーズ部を設けることにより、赤外線加
熱部から放射される全波長を効率良く吸収させ、QFP
などの黒色樹脂モールドが吸収するエネルギーとほぼ等
しくさせることによって部品間の温度差をできるだけ減
少させ過度の加熱を防止するとともに熱歪の小さい信頼
性の高い半田接合状態を持つことのできる基板の提供に
ある。
(Means for Solving the Problems) In order to solve these drawbacks, the present invention provides a black overcraze portion around the parts of the ceramic circuit board that have a low radiant energy absorption rate, thereby reducing the amount of radiation emitted from the infrared heating section. QFP efficiently absorbs all the wavelengths
To provide a board that reduces the temperature difference between parts as much as possible to prevent excessive heating by making the energy almost equal to that absorbed by a black resin mold such as, and has a highly reliable solder joint state with little thermal distortion. It is in.

以下図面により詳細に説明する。This will be explained in detail below with reference to the drawings.

(実施例) 第1図は本発明による断面を示す白色セラミックチップ
キャリア(4)搭載部の周囲に黒色オーバーグレーズ(
7)を設け、赤外線のエネルギー吸収率を改善すること
により、該部品の輻射熱と黒色オーバーグレーズ部から
の熱伝導により、Q F P (3)との温度差をなく
し均一な温度で半田付を行うことができ、信頼性の高い
両面搭載基板を提供することが可能となった。
(Example) Figure 1 shows a cross section of a white ceramic chip carrier (4) according to the present invention, with a black overglaze (
7) and improves the infrared energy absorption rate, the radiant heat of the component and the heat conduction from the black overglaze part eliminates the temperature difference with Q F P (3) and allows soldering at a uniform temperature. This makes it possible to provide a highly reliable double-sided mounting board.

(発明の効果) 以上述べたように、本発明ではエネルギー吸収率の低い
部品の周囲に黒色のオーバーグレーズ部を設けたためQ
FPなどの黒色樹脂モールドが吸収するエネルギーとほ
ぼ等しい熱吸収率としたため、部品間の温度差を減少さ
せることができ、樹脂モールドとセラミックス回路基板
との熱膨張差がなくなり、接合部分の剥離がなくなり信
頼性の高い基板を提゛供できる。
(Effect of the invention) As described above, in the present invention, the black overglaze portion is provided around the parts with low energy absorption rate.
Since the heat absorption rate is almost equal to the energy absorbed by black resin molds such as FP, it is possible to reduce the temperature difference between parts, eliminate the difference in thermal expansion between the resin mold and the ceramic circuit board, and prevent peeling of the joint part. Therefore, it is possible to provide a highly reliable board.

【図面の簡単な説明】[Brief explanation of the drawing]

1・・・セラミックス基板、2・・・半田付ラウンド、
3・・・QFP、4・・・白色セラミックチップキャリ
ア、5・・・半田付ラウンド、6・・・オーバーグレー
ズ、7・・・黒色オーバーグレーズ。 11Z’ニアζツンス悉恢 第1図 第2図 手続ネ甫正帯(方式) 1)明細書の図面の簡単な説明の欄で第5頁第15行目
に記載の「4、図面の簡単な説明」の次の行に以下の文
を挿入する。 「第1図は本発明による表面実装セラミックス基板の一
実施例を示す断面図、第2図は従来の表面実装セラミッ
クス基板の例を示す断面図である。」 昭和63年特許願第218790号 2、発明の名称 表面実装セラミックス基板 3、補正をする者 事件との関係
1...Ceramics board, 2...Soldering round,
3...QFP, 4...White ceramic chip carrier, 5...Soldered round, 6...Overglaze, 7...Black overglaze. 11Z'Nia ζ Tuns 悉恢Fig. 1 Fig. 2 Procedure Neho Seibai (Method) 1) In the brief explanation section of the drawings in the specification, see ``4. Insert the following sentence on the line next to "Explanation". "FIG. 1 is a sectional view showing an example of a surface mount ceramic substrate according to the present invention, and FIG. 2 is a sectional view showing an example of a conventional surface mount ceramic substrate." 1988 Patent Application No. 218790 2 , Name of the invention Surface-mounted ceramic substrate 3, Relationship with the case of the person making the amendment

Claims (1)

【特許請求の範囲】[Claims] 厚膜材料による回路パターンを有するセラミックス基板
上に輻射エネルギー吸収率の良い黒色樹脂モールドした
IC、トランジスタ等と輻射エネルギー吸収率の悪い白
色セラミックスを外囲器とレたチップキャリア等の表面
実装部品を半田接着する場合において、前記白色セラミ
ックスを外囲器としたチップキャリアの周囲の前記回路
パターン以外の白色部分に黒色の絶縁性厚膜材料を被覆
したことを特徴とする表面実装セラミックス基板。
Surface-mounted parts such as ICs, transistors, etc. molded in black resin with good radiant energy absorption on a ceramic substrate with a circuit pattern made of thick film material, and chip carriers with an envelope made of white ceramic with poor radiant energy absorption. A surface mount ceramic substrate characterized in that, in the case of solder bonding, a white part other than the circuit pattern around the chip carrier having the white ceramic as an envelope is coated with a black insulating thick film material.
JP21879088A 1988-09-01 1988-09-01 Surface mounting ceramic substrate Pending JPH0266991A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21879088A JPH0266991A (en) 1988-09-01 1988-09-01 Surface mounting ceramic substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21879088A JPH0266991A (en) 1988-09-01 1988-09-01 Surface mounting ceramic substrate

Publications (1)

Publication Number Publication Date
JPH0266991A true JPH0266991A (en) 1990-03-07

Family

ID=16725415

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21879088A Pending JPH0266991A (en) 1988-09-01 1988-09-01 Surface mounting ceramic substrate

Country Status (1)

Country Link
JP (1) JPH0266991A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5584633A (en) * 1994-05-10 1996-12-17 General Binding Corporation Binder element conveying mechanism

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5584633A (en) * 1994-05-10 1996-12-17 General Binding Corporation Binder element conveying mechanism

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