JPH0266938A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0266938A JPH0266938A JP21941288A JP21941288A JPH0266938A JP H0266938 A JPH0266938 A JP H0266938A JP 21941288 A JP21941288 A JP 21941288A JP 21941288 A JP21941288 A JP 21941288A JP H0266938 A JPH0266938 A JP H0266938A
- Authority
- JP
- Japan
- Prior art keywords
- film
- boron
- substrate
- layer
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 238000000034 method Methods 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 17
- 239000010703 silicon Substances 0.000 claims abstract description 17
- 150000002500 ions Chemical class 0.000 claims abstract description 8
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 7
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 2
- 239000012535 impurity Substances 0.000 abstract description 27
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 21
- 229910052796 boron Inorganic materials 0.000 abstract description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 16
- 239000002019 doping agent Substances 0.000 abstract description 9
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 4
- 238000009792 diffusion process Methods 0.000 description 21
- 238000010438 heat treatment Methods 0.000 description 12
- 235000012431 wafers Nutrition 0.000 description 12
- 230000015572 biosynthetic process Effects 0.000 description 7
- 239000007789 gas Substances 0.000 description 7
- 238000000605 extraction Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 230000005540 biological transmission Effects 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000005465 channeling Effects 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- ZOCHARZZJNPSEU-UHFFFAOYSA-N diboron Chemical compound B#B ZOCHARZZJNPSEU-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- ZFXYFBGIUFBOJW-UHFFFAOYSA-N theophylline Chemical compound O=C1N(C)C(=O)N(C)C2=C1NC=N2 ZFXYFBGIUFBOJW-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔概 要〕
電極層や不純物拡散層の形成方法に関し、極めて浅い不
純物拡散層や薄い電極層を同時に、または、別個に形成
することを目的とし、単結晶シリコン層、多結晶シリコ
ン層、アモルファスシリコン層、または、該シリコン層
が混在した層からなる半導体基板を常温で、且つ、ノン
バイアス状態とし、該半導体基板上に電子サイクロトロ
ン共鳴プラズマによって励起したイオンを被着してドー
パントフィルムを形成し、次いで、熱処理して前記シリ
コン層の全部または一部に不純物を拡散する工程が含ま
れてなることを特徴とする。[Detailed Description of the Invention] [Summary] Regarding the method for forming an electrode layer or an impurity diffusion layer, the purpose is to form an extremely shallow impurity diffusion layer or a thin electrode layer simultaneously or separately. A semiconductor substrate consisting of a polycrystalline silicon layer, an amorphous silicon layer, or a layer in which these silicon layers are mixed is kept at room temperature and in a non-biased state, and ions excited by electron cyclotron resonance plasma are deposited on the semiconductor substrate. The method is characterized in that it includes the steps of forming a dopant film using heat treatment, and then performing heat treatment to diffuse impurities into all or part of the silicon layer.
ゲート電極を設けたモストランジスタの形成途中工程に
おいて、ゲー）−電極、ソース領域、およびドレイン領
域を同時に上記方法で形成することを特徴とする。The present invention is characterized in that during the process of forming a MOS transistor provided with a gate electrode, a gate electrode, a source region, and a drain region are simultaneously formed by the above method.
ヘース引出し電極を設けたバイポーラトランジスタの形
成途中工程において、ヘース引出し電極およびヘース領
域を同時に上記方法で形成することを特徴とする。The present invention is characterized in that, in a step during the formation of a bipolar transistor provided with a heat source lead electrode, the heat source lead electrode and the heat source region are simultaneously formed by the above-described method.
本発明は半導体装置の製造方法にかかり、特に電極層や
不純物拡散層の形成方法に関する。The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming an electrode layer and an impurity diffusion layer.
ＩＣなど半導体装置の性能向上のためには一層の微細デ
バイスの形成が望まれている。In order to improve the performance of semiconductor devices such as ICs, it is desired to form even finer devices.
一般に、半導体装置は半導体基板に選択的に不純物拡散
層を形成してデバイス素子を形成しているが、その不純
物拡散方法として従前には固体あるいは気体を拡散源と
した筒温加熱による熱拡散法が用いられていた。しかし
、最近では制御性の良いイオン注入法が汎用され、ある
いは、熱拡散法とイオン注入法との両方が併用されてい
る。Generally, in semiconductor devices, device elements are formed by selectively forming an impurity diffusion layer on a semiconductor substrate, and the impurity diffusion method used up until now has been thermal diffusion using cylinder temperature heating using a solid or gas as a diffusion source. was used. However, recently, ion implantation methods with good controllability have been widely used, or both thermal diffusion methods and ion implantation methods have been used in combination.
しかし、制御性の良いイオン注入法においても、注入後
に不純物を活性化し、ダメージを回復するための高温ア
ニールが必要で、そのため、注入イオンの再分布が起こ
り、また、結晶方位によってはチャンネリング現象も起
こって、浅い接合を均一に形成することは困難である。However, even with ion implantation methods that have good controllability, high-temperature annealing is required to activate impurities and recover damage after implantation, resulting in redistribution of implanted ions and, depending on crystal orientation, channeling phenomenon. This also makes it difficult to uniformly form shallow junctions.
また、チャンネリング現象を低減させるために、垂直方
向より７°傾斜させた方向からイオン注入をおこなう方
法も採られているが、ゲート電極などを設けた段差部で
は影部分ができると云う不具合が生じる。従って、従来
の熱拡散法やイオン注入法では深さ方向に０．１〜０．
２μｍあるいはそれ以下の浅い不純物拡散層を制御性良
く形成することは困難であった。In addition, in order to reduce the channeling phenomenon, a method has been adopted in which ions are implanted from a direction tilted by 7 degrees from the vertical direction, but this method has the problem of creating shadows in the step part where the gate electrode etc. are provided. arise. Therefore, in the conventional thermal diffusion method or ion implantation method, the depth is 0.1 to 0.
It has been difficult to form a shallow impurity diffusion layer of 2 μm or less with good controllability.
そこで、発明者らは電子サイクロトロン共鳴（Ｅ ＣＲ
； Ｅｌｅｃｔｒｏｎ Ｃｙｃｌｏｔｒｏｎ Ｒｅ５ｏ
ｎａｎｃｅ）プラズマによってドーパントガス（Ｄｏｐ
ａｎｔ Ｇａ５）を励起して反応室に供給し、供給され
たドーパントガスによって常温で、且つ、ノンバイアス
な半導体基板上にドーパントフィルムを成長し、しかる
後、酸素フリー雰囲気の低温度において熱処理して不純
物を拡散する製造方法を提案した。Therefore, the inventors used electron cyclotron resonance (E CR
; Electron Cyclotron Re5o
dopant gas (Dop) by plasma
ant Ga5) is excited and supplied to the reaction chamber, a dopant film is grown on the semiconductor substrate at room temperature and without bias using the supplied dopant gas, and then heat treated at low temperature in an oxygen-free atmosphere. We proposed a manufacturing method that diffuses impurities.
第３図はその製造方法を適用するＥＣＲプラスマ処理装
置の断面図で、２１はプラズマ生成室、２２は反応室、
２３はロードロック室２２４はマイクロ波電源、２５は
導波管、２６はアルミナ透過窓、２７はガス供給０．２
８はマグネットコイル５２９はウェハー（被処理基板）
、３０は分子ターボポンプ、 ３Ｌ ３２はメカニカル
ポンプである。装置全体はＥ ＣＲ’７’ラズマを生成
するためのプラズマ生成室２１．ドーパントフィルムを
成長するための反応室２２．ウェハー２９を反応室２２
に搬入・搬出するためのロードロック室２３から構成さ
れており、導波管２５からプラズマ生成室２１への接続
部外周にはマグネットコイル２８が配置されて、生成イ
オンをウェハーに到達させるように発散磁界が形成され
ている。FIG. 3 is a cross-sectional view of an ECR plasma processing apparatus to which the manufacturing method is applied, in which 21 is a plasma generation chamber, 22 is a reaction chamber,
23 is a load lock chamber 224 is a microwave power source, 25 is a waveguide, 26 is an alumina transmission window, and 27 is a gas supply 0.2
8 is a magnet coil 529 is a wafer (substrate to be processed)
, 30 is a molecular turbo pump, and 3L 32 is a mechanical pump. The entire apparatus includes a plasma generation chamber 21 for generating ECR'7' lasma. Reaction chamber 22 for growing the dopant film. The wafer 29 is placed in the reaction chamber 22.
It consists of a load lock chamber 23 for loading and unloading the wafer into the wafer, and a magnet coil 28 is placed around the outer periphery of the connection from the waveguide 25 to the plasma generation chamber 21 to allow generated ions to reach the wafer. A diverging magnetic field is formed.
マイクロ波透過窓は高純度アルミナ製の透過窓２６を使
用して、プラズマ生成室に酸素が混入しないように図っ
ており、酸素の混入し易い石英製の透過窓は用いない。As the microwave transmission window, a transmission window 26 made of high-purity alumina is used to prevent oxygen from entering the plasma generation chamber, and a transmission window made of quartz, which is easily contaminated with oxygen, is not used.
同様の理由で装置全体の容器壁も石英製でなく、アルミ
ニウムで作成し、且つ、プラズマ生成室は１００℃以上
にならないように工夫し、且つ、ウェハー２９も１００
°Ｃ以上に加熱されないように冷却させる。For the same reason, the container wall of the entire apparatus is made of aluminum instead of quartz, and the plasma generation chamber is designed to not exceed 100°C, and the wafer 29 is also made of 100°C.
Allow to cool to avoid heating above °C.
プラズマ励起用マイクロ波の周波数を２．４５ＧＨｚと
して、例えば、マグネットコイルはこの周波数２、４５
ＧＨｚに対して磁束密度８７５ガウス（ガス供給側）
、３００ガウス（生成室開口側）にする。そうすると、
荷電粒子（イオン）は発散磁場内で円運動しつつ、その
円運動エネルギーが角運動を保存したまま発散磁場方向
の運動エネルギーに変換されて磁力線方向に加速され、
ウェハーに到達して膜が成長する。その成膜の際、ウェ
ハーは常温でノンバイアス状態にあるために、基板にダ
メージを与えることなく低速でソフトに成長膜（ドーパ
ントフィルム）が被着する利点がある。For example, if the frequency of the microwave for plasma excitation is 2.45 GHz, the magnet coil is set at this frequency of 2.45 GHz.
Magnetic flux density 875 Gauss for GHz (gas supply side)
, 300 Gauss (on the opening side of the generation chamber). Then,
Charged particles (ions) move in a circular motion within a divergent magnetic field, and the circular kinetic energy is converted into kinetic energy in the direction of the divergent magnetic field while preserving its angular motion, and is accelerated in the direction of the magnetic field lines.
The film reaches the wafer and grows. During film formation, since the wafer is in a non-biased state at room temperature, there is an advantage that the grown film (dopant film) can be deposited slowly and softly without damaging the substrate.
このように構成されたＥＣＲプラズマ処理装置によって
、例えば、ガス供給口２７がらジボラン（Ｂ２Ｈ６）１
〜５％含有したアルゴン（Ａｒ）ガス３０ｃｃ ７分を
流入して、チャンバ（室）内を圧力０゜ＩＰａ （パス
カル）に保持し、ＥＣＲプラズマの照射を１０秒ないし
数十秒おこなう。そうすると、プラズマ生成室１１にお
いて励起されたボロンが反応室１２に導かれ、低速でウ
ェハーに到達して数十ないし数百人の原子状のボロンフ
ィルムを成長する。With the ECR plasma processing apparatus configured in this way, for example, diborane (B2H6) 1
30 cc of argon (Ar) gas containing ~5% is flowed in for 7 minutes, the pressure inside the chamber is maintained at 0° IPa (Pascal), and ECR plasma irradiation is performed for 10 seconds to several tens of seconds. Then, the boron excited in the plasma generation chamber 11 is guided to the reaction chamber 12, reaches the wafer at a low speed, and grows a boron film of tens to hundreds of atoms.
しかる後、減圧気中などの酸素フリー雰囲気の低温度（
９００℃以下）において熱処理して不純物拡散層を形成
する。そうすれば、不純物濃度１０！コ〜１０ ”／
ｃａｔ、深さ０．１μｍ前後の高濃度で浅い不純物拡散
層を形成することが可能である。After that, it is heated to a low temperature (
An impurity diffusion layer is formed by heat treatment at a temperature of 900° C. or lower. If you do that, the impurity concentration will be 10! Ko~10”/
It is possible to form a highly concentrated and shallow impurity diffusion layer with a depth of about 0.1 μm.
本発明はこのような不純物拡散方法を適用して極めて浅
い不純物拡散層や薄い電極層を同時に、または、別個に
形成することを目的とした半導体装置の製造方法を提案
するものである。The present invention proposes a method for manufacturing a semiconductor device that uses such an impurity diffusion method to simultaneously or separately form extremely shallow impurity diffusion layers and thin electrode layers.
その目的は、単結晶シリコン層１多結晶シリコン層、ア
モルファスシリコン層８ または、該シリコン層が混在
した層からなる半導体基板を常温で、且つ、ノンバイア
ス状態とし、該半導体基板上に電子サイクロトロン共鳴
プラズマによって励起したイオンを被着してドーパント
フィルムを形成し、次いで、熱処理して前記シリコン層
の全部または一部に不純物を拡散する工程が含まれる製
造方法によって達成される。The purpose is to bring a semiconductor substrate consisting of a single crystal silicon layer 1, a polycrystalline silicon layer 8, an amorphous silicon layer 8, or a mixture of these silicon layers to a non-biased state at room temperature, and to generate electron cyclotron resonance on the semiconductor substrate. This is accomplished by a manufacturing method that includes depositing plasma-excited ions to form a dopant film, followed by heat treatment to diffuse impurities into all or part of the silicon layer.
例えば、ゲート電極を設けたモストランジスタの形成途
中工程において、ゲート電極９ ソース領域、およびド
レイン領域を同時に形成する。For example, in the process of forming a MOS transistor provided with a gate electrode, the gate electrode 9, the source region, and the drain region are formed at the same time.
また、ベース引出し電極を設けたバイポーラトランジス
タの形成途中工程において、ベース引出し電極およびベ
ース領域を同時に形成する。Further, in a process during the formation of a bipolar transistor provided with a base extraction electrode, the base extraction electrode and the base region are formed simultaneously.
即ち、本発明は、上記したシャロージヤンクション（ｓ
ｈａｌｌｏｉｖ ｊｕｎｃｔｉｏｎ ；浅い接合）を形
成する不純物拡散方法を適用して、不純物拡散層は勿論
のこと、薄い電極層をも同時に、または、別々に形成し
、半導体デバイスを微細化させてＩＣを高性能化するも
のである。That is, the present invention provides the above-mentioned shallow junction (s
Applying an impurity diffusion method that forms a halloiv junction (shallow junction), not only an impurity diffusion layer but also a thin electrode layer can be formed simultaneously or separately, miniaturizing semiconductor devices and increasing the performance of ICs. It is something that becomes.
以下、図面を参照して実施例によって詳細に説明する。 Hereinafter, embodiments will be described in detail with reference to the drawings.
第１図ｆａｔ〜（Ｃ１は本発明にかかる形成方法（１）
の工程順断面図で、ゲート電極、ソース領域、ドレイン
領域を同時に形成するモストランジスタの形成途中工程
図である。Figure 1 fat~ (C1 is the formation method (1) according to the present invention)
FIG. 2 is a cross-sectional view showing a step in the process of forming a MOS transistor in which a gate electrode, a source region, and a drain region are simultaneously formed.
第１図（ａ）参照；まず、ｎ型シリコン基板１に公知の
ＬＯＣＯ３法によってフィールド絶縁膜２を形成し、膜
厚２００人程人程ゲート絶縁膜３を生成した後、膜厚４
０００人程度０多結晶シリコン膜をＣＶＤ（化学気相成
長）法で被着し、この多結晶シリコン膜をパターンニン
グして多結晶シリコン膜からなるゲート電極４を形成す
る。ここに、多結晶シリコン膜はノンドープ膜である。Refer to FIG. 1(a); First, a field insulating film 2 is formed on an n-type silicon substrate 1 by the well-known LOCO3 method, and a gate insulating film 3 with a film thickness of about 200 cm is formed.
A polycrystalline silicon film of approximately 1,000 yen is deposited by CVD (chemical vapor deposition), and this polycrystalline silicon film is patterned to form a gate electrode 4 made of the polycrystalline silicon film. Here, the polycrystalline silicon film is a non-doped film.
第１図（ｂｌ参照；次いで、前記したＥＣＲプラズマ処
理装置（第３図参照）に基板を載置し、上記した電子サ
イクロトロン共鳴プラズマ法によって膜厚数百人のボロ
ンフィルム５を成長する。FIG. 1 (see BL; see BL; next, the substrate is placed on the ECR plasma processing apparatus described above (see FIG. 3), and a boron film 5 with a thickness of several hundred thick is grown by the electron cyclotron resonance plasma method described above.
第１図（Ｃ１参照；次いで、酸素フリー雰囲気中、例え
ば、減圧度４ Ｔｏｒｒ程度の窒素（Ｎ２）中において
９００℃、１０分間の熱処理をおこなう。そうすると、
ゲート電極としての多結晶シリコン膜に硼素（Ｂ）が拡
散して高濃度に硼素を含有した低抵抗なゲート電極４が
形成されると同時に、露出したｎ型シリコン基板１にも
ボロンフィルムから硼素が拡散して、浅い接合を有する
ｐ型のソース領域６およびドレイン領域７が形成され、
そのソース・ドレイン領域の接合深さは０．２μｍ程度
になる。なお、この熱処理の際にボロンフィルムは殆ど
飛散するが、念のため熱処理後に弗酸洗浄をおこなう。FIG. 1 (See C1; Next, heat treatment is performed at 900° C. for 10 minutes in an oxygen-free atmosphere, for example, nitrogen (N2) at a reduced pressure of about 4 Torr. Then,
At the same time, boron (B) is diffused into the polycrystalline silicon film serving as the gate electrode to form a gate electrode 4 containing a high concentration of boron and having low resistance. is diffused to form p-type source region 6 and drain region 7 having shallow junctions,
The junction depth of the source/drain regions is approximately 0.2 μm. Although most of the boron film is scattered during this heat treatment, hydrofluoric acid cleaning is performed after the heat treatment just to be sure.
その後、カバー絶縁膜をＣＶＤ法で被着してリフロー（
再溶融）をおこなう。しかし、リフロー温度は熱処理温
度と同様の９００℃であるから、接合深さが変化するこ
とはない。After that, a cover insulating film is deposited using the CVD method and reflowed (
remelting). However, since the reflow temperature is 900° C., which is the same as the heat treatment temperature, the bonding depth does not change.
なお、この実施例において、ボロンフィルムとｎ型シリ
コンＭ＋、との間に膜厚約１００人の５ｉ０２膜を介在
させても構わない。In this example, a 5i02 film having a thickness of about 100 wafers may be interposed between the boron film and the n-type silicon M+.
このようなモストランジスタの形成法によれば、。According to the method of forming such a MOS transistor.
ゲート長０．７μｍ、拡散深さ０．２μｍの微細デバイ
スを形成することができ、従来のイオン注入法によって
形成していたゲート長１．０μｍ、拡散深さ０．３５μ
ｍのデバイス素子に比べて一層微細化される。It is possible to form fine devices with a gate length of 0.7 μm and a diffusion depth of 0.2 μm, compared to the conventional ion implantation method with a gate length of 1.0 μm and a diffusion depth of 0.35 μm.
It is further miniaturized compared to the device element of m.
次に、第２図（ａｌ〜（Ｃ）は本発明にかかる形成方法
（ＩＴ）の工程順断面図で、ベース引出し電極、ヘース
領域を同時に形成するバイポーラトランジスタの形成途
中工程図である。Next, FIGS. 2(al) to 2(C) are cross-sectional views in the order of steps of the formation method (IT) according to the present invention, which are process views during the formation of a bipolar transistor in which a base extraction electrode and a heath region are simultaneously formed.
第２図ｆａｌ参照；本図はｐ型シリコン基板１１上にｎ
＋型型埋面層１２介してｎ型９９３７層１３をエピタキ
シャル成長し、その上に選択的にベース形成領域を窓開
けした５ｉ０２膜１４が設けられて、更にその上に単結
晶シリコン膜１５と多結晶シリコン膜１６からなるエピ
ポリ層を成長させた工程断面図である。なお、単結晶シ
リコン膜１５および多結晶シリコンＪＩＱ１６はノンド
ープ膜である。Refer to Figure 2 fal; this figure shows an n
An n-type 9937 layer 13 is epitaxially grown through a +-type buried layer 12, and a 5i02 film 14 with a selectively opened base formation region is provided thereon, and a monocrystalline silicon film 15 and a polygonal silicon film 14 are further formed on it. FIG. 3 is a cross-sectional view showing the process of growing an epipoly layer made of crystalline silicon film 16. Note that the single crystal silicon film 15 and the polycrystalline silicon JIQ 16 are non-doped films.
第２図（ｂ）参照；次いで、その単結晶シリコン膜１５
と多結晶シリコン膜１６からなるエビポリ層の上に前記
した電子サイクロトロン共鳴プラズマ法によって膜厚数
百人のボロンフィルム１７を成長する。See FIG. 2(b); Next, the single crystal silicon film 15
A boron film 17 with a thickness of several hundred thick is grown on the polycrystalline layer 16 made of polycrystalline silicon film 16 by the electron cyclotron resonance plasma method described above.
第２図ｆｃ）参照；次いで、減圧度４Ｔｏｒｒ程度の窒
素（Ｎ２）中において９００°Ｃ１１０分間の熱処理を
おこない、単結晶シリコン膜１５に硼素を拡散させてｐ
型ベース領域１５′とし、且つ、多結晶シリコン膜１６
に高濃度に硼素を含有させて低抵抗なペース引出し電極
１６′を形成する。この時、ボロンフィルムは殆ど消失
するが、熱処理後に表面を軽く弗酸洗浄おこなう。See Figure 2 fc); Next, heat treatment is performed at 900°C for 110 minutes in nitrogen (N2) at a reduced pressure of about 4 Torr to diffuse boron into the single crystal silicon film 15.
A mold base region 15' and a polycrystalline silicon film 16
A low-resistance paste extraction electrode 16' is formed by containing boron at a high concentration. At this time, most of the boron film disappears, but after the heat treatment, the surface is lightly washed with hydrofluoric acid.
上記のようなバイポーラトランジスタの形成法を用いれ
ば、浅い接合をもつヘース領域と微細なベース引出し電
極を同時に形成できて、バイポーラデバイス素子が更に
微細化され、ＩＣの高性能化に役立つ。By using the method for forming a bipolar transistor as described above, it is possible to simultaneously form a base region having a shallow junction and a fine base lead electrode, which further miniaturizes the bipolar device element and helps improve the performance of the IC.
上記の実施例のように、低加速エネルギーで被着させる
電子サイクロトロン共鳴プラズマ法を適用すれば、浅い
接合をもつ不純物拡散層のみならず、ゲート電極やベー
ス引出し電極のような導電層をも高濃度に不純物を含有
させて低抵抗化することができる。As in the above example, if the electron cyclotron resonance plasma method is applied to deposit with low acceleration energy, not only impurity diffusion layers with shallow junctions but also conductive layers such as gate electrodes and base extraction electrodes can be formed. The resistance can be lowered by including impurities in the concentration.
なお、請求項に「シリコン層の全部または一部に不純物
を拡散する」と記載しているが、例えば、第１図に説明
した実施例においてｎ型シリコン基板Ｉにソース・ドレ
イン領域６．７を形成するのが一部に不純物を拡散する
ことを意味し、多結晶シリコン膜からなるゲート電極４
はシリコン層の全部に不純物を拡散することを意味して
いる。Although the claims state that "impurities are diffused into all or part of the silicon layer," for example, in the embodiment illustrated in FIG. This means that impurities are diffused into a part of the gate electrode 4 made of a polycrystalline silicon film.
means that impurities are diffused throughout the silicon layer.
上記例は不純物拡散層と電極層とを同時に形成する実施
例で説明したが、多結晶シリコンの電極層のみに高濃度
に不純物を拡散させて低抵抗化し、その結果として電極
層を微細化することができることは当然である。また、
最近、多結晶シリコン膜の他に、アモルファスシリコン
膜が用いられて、例えば、エミッタ電極として使用され
ているが、そのようなアモルファスシリコン膜にも本発
明を適用して高濃度に不純物を含有させ、低抵抗化する
ことかできる。The above example was explained as an example in which the impurity diffusion layer and the electrode layer are formed simultaneously, but it is also possible to diffuse impurities at a high concentration only in the polycrystalline silicon electrode layer to lower the resistance, and as a result, the electrode layer is made finer. Of course it can be done. Also,
Recently, in addition to polycrystalline silicon films, amorphous silicon films have been used, for example, as emitter electrodes, and the present invention can also be applied to such amorphous silicon films to contain impurities at a high concentration. , it is possible to lower the resistance.
なお、本発明によれば常温のウェハー（被処理基板）上
にボロンフィルムを成長するために、予めレジスト膜を
マスクした状態で選択的にボロンフィルムを成長させる
工程を採ることも可能になる。According to the present invention, in order to grow a boron film on a wafer (substrate to be processed) at room temperature, it is also possible to adopt a step of selectively growing a boron film with a resist film masked in advance.
なお、上記はボロンフィルムを実施例とした説明である
が、砒素、燐などｎ型のドーパントフィルムにも適用で
きることは云うまでもない。Although the above description is based on a boron film as an example, it goes without saying that the present invention can also be applied to n-type dopant films such as arsenic and phosphorus.
以上の説明から明らかなように、本発明によれば極めて
浅い不純物拡散層や低抵抗化した電極層を制御性良く微
細に形成でき、半導体デバイスの微細化、率いては、デ
バイスの性能向上に顕著に役立つものである。As is clear from the above explanation, according to the present invention, extremely shallow impurity diffusion layers and low-resistance electrode layers can be formed finely with good controllability, which contributes to the miniaturization of semiconductor devices and, ultimately, to the improvement of device performance. It is extremely helpful.
第１図は本発明にかかる形成方法（１）の工程順断面図
、
第２図は本発明にかかる形成方法（ＩＩ）の工程順断面
図、
第３図はＥＣＲプラズマ処理装置の断面図である。
図において、
１はｎ型シリコン基板、２はフィールド絶縁膜、３はゲ
ート絶縁膜、 ４はゲート電礪、５はボロンフィル
ム、 ６はソース領域、７はドレイン領域、
１１はｐ型シリコン基板、１２はｎ＋型埋没層、１３は
ｎ型シリコン層、 １４は５ｉ０２膜、１５は単結晶シ
リコン膜、１５“はベース領域、１６は多結晶シリコン
膜、１６“はベース引出し電極、１７はボロンフィルム
、
２１はプラズマ生成室、 ２２は反応室、２３はロード
ロ、り室、 ２４はマイクロ波電源、２５は導波管、
２６はアルミナ透過窓、２７はガス供給口、
２８はマグネットコイル、２９はウェハー（被処理
基板）、
３０は分子ターボポンプ、
３１３２はメカニカルポンプ
を示している。FIG. 1 is a step-by-step cross-sectional view of the forming method (1) according to the present invention, FIG. 2 is a step-by-step cross-sectional view of the forming method (II) according to the present invention, and FIG. 3 is a cross-sectional view of an ECR plasma processing apparatus. be. In the figure, 1 is an n-type silicon substrate, 2 is a field insulating film, 3 is a gate insulating film, 4 is a gate electrode, 5 is a boron film, 6 is a source region, 7 is a drain region, 11 is a p-type silicon substrate, 12 is an n+ type buried layer, 13 is an n-type silicon layer, 14 is a 5i02 film, 15 is a single crystal silicon film, 15" is a base region, 16 is a polycrystalline silicon film, 16" is a base extraction electrode, and 17 is a boron film. , 21 is a plasma generation chamber, 22 is a reaction chamber, 23 is a loading chamber, 24 is a microwave power source, 25 is a waveguide,
26 is an alumina transmission window, 27 is a gas supply port,
28 is a magnet coil, 29 is a wafer (substrate to be processed), 30 is a molecular turbo pump, and 3132 is a mechanical pump.
Claims (3)
ァスシリコン層、または、該シリコン層が混在した層か
らなる半導体基板を常温で、且つ、ノンバイアス状態と
し、該半導体基板上に電子サイクロトロン共鳴プラズマ
によつて励起したイオンを被着してドーパントフィルム
を形成し、次いで、熱処理して前記シリコン層の全部ま
たは一部に不純物を拡散する工程が含まれてなることを
特徴とする半導体装置の製造方法。(1) A semiconductor substrate consisting of a single crystal silicon layer, a polycrystal silicon layer, an amorphous silicon layer, or a layer in which these silicon layers are mixed is kept at room temperature and in a non-biased state, and an electron cyclotron resonance plasma is applied to the semiconductor substrate. manufacturing a semiconductor device, comprising the steps of: depositing ions excited by Method.
ジスタの形成途中工程であつて、ゲート電極、ソース領
域、およびドレイン領域を同時に形成することを特徴と
する請求項１記載の半導体装置の製造方法。(2) The method for manufacturing a semiconductor device according to claim 1, characterized in that the step is an intermediate step in forming a MOS transistor in which the semiconductor substrate is provided with a gate electrode, and the gate electrode, the source region, and the drain region are formed at the same time. .
ポーラトランジスタの形成途中工程であって、ベース引
出し電極およびベース領域を同時に形成することを特徴
とする請求項１記載の半導体装置の製造方法。(3) The method of manufacturing a semiconductor device according to claim 1, wherein the step is a step in the middle of forming a bipolar transistor in which the semiconductor substrate is provided with a base lead-out electrode, and the base lead-out electrode and the base region are formed at the same time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21941288A JPH0266938A (en) | 1988-08-31 | 1988-08-31 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21941288A JPH0266938A (en) | 1988-08-31 | 1988-08-31 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0266938A true JPH0266938A (en) | 1990-03-07 |
Family
ID=16734998
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21941288A Pending JPH0266938A (en) | 1988-08-31 | 1988-08-31 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0266938A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5077563A (en) * | 1986-04-10 | 1991-12-31 | Ngk Insulators, Ltd. | Thermally printing head operable with electrically resistive layer provided on printt film or ribbon or on recording medium |
| US5656511A (en) * | 1989-09-04 | 1997-08-12 | Canon Kabushiki Kaisha | Manufacturing method for semiconductor device |
| US5753530A (en) * | 1992-04-21 | 1998-05-19 | Seiko Instruments, Inc. | Impurity doping method with diffusion source of boron-silicide film |
| US6489207B2 (en) | 1998-05-01 | 2002-12-03 | International Business Machines Corporation | Method of doping a gate and creating a very shallow source/drain extension and resulting semiconductor |
-
1988
- 1988-08-31 JP JP21941288A patent/JPH0266938A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5077563A (en) * | 1986-04-10 | 1991-12-31 | Ngk Insulators, Ltd. | Thermally printing head operable with electrically resistive layer provided on printt film or ribbon or on recording medium |
| US5656511A (en) * | 1989-09-04 | 1997-08-12 | Canon Kabushiki Kaisha | Manufacturing method for semiconductor device |
| US5753530A (en) * | 1992-04-21 | 1998-05-19 | Seiko Instruments, Inc. | Impurity doping method with diffusion source of boron-silicide film |
| US6489207B2 (en) | 1998-05-01 | 2002-12-03 | International Business Machines Corporation | Method of doping a gate and creating a very shallow source/drain extension and resulting semiconductor |
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