JPH0265349U - - Google Patents
Info
- Publication number
- JPH0265349U JPH0265349U JP14448488U JP14448488U JPH0265349U JP H0265349 U JPH0265349 U JP H0265349U JP 14448488 U JP14448488 U JP 14448488U JP 14448488 U JP14448488 U JP 14448488U JP H0265349 U JPH0265349 U JP H0265349U
- Authority
- JP
- Japan
- Prior art keywords
- ceramic substrate
- tab
- lead
- lead pad
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims 4
- 239000000463 material Substances 0.000 claims 1
- 238000007789 sealing Methods 0.000 claims 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は本考案のチツプキヤリアの一実施例の
縦断面図、第２図および第３図は第１図に示す実
施例を多層配線基板に実装した状態を示す側面図
、第４図、第５図および第６図は従来のチツプキ
ヤリアの断面図である。
１……セラミツク基板、２……リード用パツド
、３……ＴＡＢ ＩＣ、４……リード、５……内
部配線、６……入出力用ピン、７……キヤツプ、
８……接着剤、９……ヒートシンク、１０……多
層配線基板、１１……半田付け部、１２……スル
ーホール、１３……入出力用端子。
FIG. 1 is a vertical sectional view of an embodiment of the chip carrier of the present invention, FIGS. 2 and 3 are side views showing the embodiment shown in FIG. 1 mounted on a multilayer wiring board, and FIGS. 5 and 6 are cross-sectional views of conventional chip carriers. 1... Ceramic board, 2... Lead pad, 3... TAB IC, 4... Lead, 5... Internal wiring, 6... Input/output pin, 7... Cap,
8... Adhesive, 9... Heat sink, 10... Multilayer wiring board, 11... Soldering portion, 12... Through hole, 13... Input/output terminal.
Claims (1)
に被せられ熱伝導性の良好な材料からなる封止用
のキヤツプと、このキヤツプのダイが接着されフ
エイスダウンで実装されたＴＡＢ ＩＣと、前記
セラミツク基板の表面に設けられ前記ＴＡＢ Ｉ
Ｃのリードが接続されるリード用パツドと、この
リード用パツドと内部配線により接続され前記セ
ラミツク基板の裏面に設けられた入出力用ピンと
を含むことを特徴とするチツプキヤリア。 A ceramic substrate, a sealing cap made of a material with good thermal conductivity and placed over the surface of the ceramic substrate, a TAB IC to which the die of the cap is bonded and mounted face-down, and the surface of the ceramic substrate. provided in the TAB I
A chip carrier comprising: a lead pad to which a C lead is connected; and an input/output pin connected to the lead pad by internal wiring and provided on the back surface of the ceramic substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14448488U JPH0265349U (en) | 1988-11-04 | 1988-11-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14448488U JPH0265349U (en) | 1988-11-04 | 1988-11-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0265349U true JPH0265349U (en) | 1990-05-16 |
Family
ID=31412238
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14448488U Pending JPH0265349U (en) | 1988-11-04 | 1988-11-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0265349U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013098328A (en) * | 2011-10-31 | 2013-05-20 | Shinko Electric Ind Co Ltd | Semiconductor device |
-
1988
- 1988-11-04 JP JP14448488U patent/JPH0265349U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013098328A (en) * | 2011-10-31 | 2013-05-20 | Shinko Electric Ind Co Ltd | Semiconductor device |
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