JPH0265163A - Metallic substrate for integrated circuit - Google Patents
Metallic substrate for integrated circuitInfo
- Publication number
- JPH0265163A JPH0265163A JP21527488A JP21527488A JPH0265163A JP H0265163 A JPH0265163 A JP H0265163A JP 21527488 A JP21527488 A JP 21527488A JP 21527488 A JP21527488 A JP 21527488A JP H0265163 A JPH0265163 A JP H0265163A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- insulating layer
- ceramic layer
- metal substrate
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 20
- 239000000919 ceramic Substances 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 7
- 229910003460 diamond Inorganic materials 0.000 claims abstract description 5
- 239000010432 diamond Substances 0.000 claims abstract description 5
- 229910052582 BN Inorganic materials 0.000 claims abstract description 4
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 claims abstract description 4
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims abstract description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 4
- 229910052751 metal Inorganic materials 0.000 claims description 28
- 239000002184 metal Substances 0.000 claims description 28
- 239000000463 material Substances 0.000 abstract description 8
- 238000000151 deposition Methods 0.000 abstract description 4
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 3
- 239000004020 conductor Substances 0.000 abstract description 3
- 239000012535 impurity Substances 0.000 abstract description 3
- 229920005989 resin Polymers 0.000 abstract description 2
- 239000011347 resin Substances 0.000 abstract description 2
- 230000008021 deposition Effects 0.000 abstract 2
- 230000005855 radiation Effects 0.000 abstract 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 9
- 239000011889 copper foil Substances 0.000 description 7
- 230000017525 heat dissipation Effects 0.000 description 6
- 238000004806 packaging method and process Methods 0.000 description 6
- 229920003002 synthetic resin Polymers 0.000 description 6
- 239000000057 synthetic resin Substances 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- 238000007740 vapor deposition Methods 0.000 description 5
- 239000010949 copper Substances 0.000 description 4
- 238000010292 electrical insulation Methods 0.000 description 4
- 238000007743 anodising Methods 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000000696 magnetic material Substances 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000005536 corrosion prevention Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
Landscapes
- Insulated Metal Substrates For Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、例えばハイブリッドＩＣのための集積回路用
金属基板に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a metal substrate for an integrated circuit, for example for a hybrid IC.
［従来の技術］
従来のハイブリッドＩＣに用いられる一般的な金属基板
の構成を第２図に示す。図に示すように、従来の金属基
板１は、１〜２ ｍｍ厚のアルミニウム板１１の表面に
エポキシ樹脂あるいはガラスエポキシ樹脂等の電気絶縁
層１３を数十〜数百μｍ厚程度に形成し、さらにその電
気絶縁層１３の上に数十μｍ厚程度の銅箔１４を形成し
てなるものである。場合によっては、アルミニウム板１
１の表面にあらかじめ陽極酸化処理により２０μｍ厚程
度０アルマイト層１２を形成する。そして、エツチング
等により銅箔１４に必要な電気回路を施し、その電気回
路上に小信号トランジスタ・チップ２、パワートランジ
スタ・チップ３、抵抗４等の半導体素子等を搭載接合し
ている。なお図中、５はパワートランジスタ・チップ３
用の銅ヒートシンク、１５は必要に応じて銅箔１４の電
気回路上に施されたニッケルメッキ層である。[Prior Art] FIG. 2 shows the structure of a general metal substrate used in a conventional hybrid IC. As shown in the figure, the conventional metal substrate 1 includes an electrically insulating layer 13 made of epoxy resin or glass epoxy resin formed on the surface of an aluminum plate 11 with a thickness of 1 to 2 mm to a thickness of several tens to hundreds of μm. Furthermore, a copper foil 14 having a thickness of several tens of micrometers is formed on the electrical insulating layer 13. In some cases, aluminum plate 1
An alumite layer 12 having a thickness of approximately 20 μm is formed on the surface of the substrate 1 by anodizing treatment in advance. Then, a necessary electric circuit is formed on the copper foil 14 by etching or the like, and semiconductor elements such as a small signal transistor chip 2, a power transistor chip 3, a resistor 4, etc. are mounted and bonded onto the electric circuit. In the figure, 5 is the power transistor chip 3.
The copper heat sink 15 is a nickel plating layer applied on the electrical circuit of the copper foil 14 as required.
［発明が解決しようとする課題］
従来の金属基板は、上記のようにアルマイト層１２、電
気絶縁層１３．及び電気導体層（銅箔）１４の３層構造
であるが、最下層のアルマイト層１２は周知のように湿
式の陽極酸化処理にて作製され、処理コストが高いうえ
に平坦度が数μｍにもなって良質のものを得難いという
問題がある。[Problems to be Solved by the Invention] As described above, the conventional metal substrate has the alumite layer 12, the electrical insulating layer 13 . The alumite layer 12, which is the lowest layer, is produced by wet anodizing, which is expensive and has a flatness of only a few μm. The problem is that it is difficult to obtain high-quality products.
また、簡単な構造の金属基板、あるいは他の材質の金属
板、例えば銅板を使用するものにあっては、上記アルマ
イト層を省略して電気絶縁層１３と銅箔１４の２層構造
としているが、この場合は高い電気絶縁性、絶縁耐圧を
得るために合成樹脂等からなる電気絶縁層１３が厚くな
る。電気絶縁層が厚くなると、合成樹脂のために熱伝導
性が悪くなって放熱性が低下し、半導体素子等の実装密
度を高めることが困難となる。このように電気絶縁層の
厚さは、一方では高い電気的特性（電気絶縁性、絶縁耐
圧等）を保証しなければならないが、他方ではあまり厚
くすると放熱性が損なわれ実装密度の向上に支障がある
という矛盾を含んでいるものである。In addition, in the case of a metal substrate with a simple structure or a metal plate made of another material, such as a copper plate, the alumite layer is omitted and a two-layer structure consisting of the electrical insulating layer 13 and the copper foil 14 is used. In this case, the electrical insulating layer 13 made of synthetic resin or the like is thick in order to obtain high electrical insulation and dielectric strength. When the electrical insulating layer becomes thicker, thermal conductivity deteriorates due to the synthetic resin, and heat dissipation performance decreases, making it difficult to increase the packaging density of semiconductor elements and the like. In this way, the thickness of the electrical insulating layer must, on the one hand, ensure high electrical properties (electrical insulation, dielectric strength, etc.), but on the other hand, if it is too thick, heat dissipation will be impaired, which will hinder the improvement of packaging density. This includes the contradiction that there is.
本発明は、上記の従来の課題を解決するため、合成樹脂
等の電気絶縁層をできるだけ薄く形成し、しかもその厚
さが薄くても高い電気的特性を十分に保証することがで
き、かつ高放熱性、高実装密度が得られるようにした集
積回路用金属基板を得ることを目的とするものである。In order to solve the above-mentioned conventional problems, the present invention can form an electrically insulating layer made of synthetic resin or the like as thin as possible, and can sufficiently guarantee high electrical characteristics even if the thickness is thin. The object of the present invention is to obtain a metal substrate for integrated circuits that provides heat dissipation and high packaging density.
［課題を解決するための手段］
本発明に係る集積回路用金属基板は、金属板の表面に合
成樹脂等の電気絶縁層及びその上に銅箔等の電気導体層
を形成したものにおいて、金属板と電気絶縁層の間にア
ルミナ、窒化アルミニウム、炭化ケイ素系、ダイヤモン
ドまたは立方晶窒化ホウ素からなる高熱伝導性セラミッ
クス層を蒸着し、電気絶縁層の厚さを薄くしたものであ
る。蒸着法としてはＰＶＤ法またはＣＶＤ法がとられる
。金属板には一般にＡＩ、Ｃｕ系の材料が用いられるが
、磁性材料を用いると電磁シールドが可能になる。[Means for Solving the Problems] A metal substrate for an integrated circuit according to the present invention is a metal substrate having an electrically insulating layer such as a synthetic resin on the surface and an electrically conductive layer such as copper foil formed thereon. A highly thermally conductive ceramic layer made of alumina, aluminum nitride, silicon carbide, diamond, or cubic boron nitride is deposited between the plate and the electrically insulating layer to reduce the thickness of the electrically insulating layer. A PVD method or a CVD method is used as the vapor deposition method. Generally, AI or Cu-based materials are used for the metal plate, but electromagnetic shielding becomes possible when a magnetic material is used.
［作 用］
本発明による金属基板は、金属板の表面に蒸着された高
熱伝導性セラミックス層により、それ自体が高い電気絶
縁性、絶縁耐圧を有し、ハイブリッドＩＣ等で要求され
る電気的条件を十分に満たす。そのうえに蒸着により該
セラミックス層を形成するので、該セラミックス層中に
不純物が混入することがほとんどなく、その平坦度もき
わめて高い。したがって、該セラミックス層の上に形成
される樹脂等の電気絶縁層の厚さを薄くすることができ
、かつ該セラミックス層は高熱伝導性を有するため放熱
性が高く、実装密度を高めることが可能となる。[Function] The metal substrate according to the present invention has high electrical insulation properties and dielectric strength voltage due to the highly thermally conductive ceramic layer deposited on the surface of the metal plate, and meets the electrical conditions required for hybrid ICs, etc. fully satisfy. Moreover, since the ceramic layer is formed by vapor deposition, impurities are hardly mixed into the ceramic layer, and its flatness is extremely high. Therefore, the thickness of the electrically insulating layer such as resin formed on the ceramic layer can be made thinner, and since the ceramic layer has high thermal conductivity, it has high heat dissipation and can increase the packaging density. becomes.
［実施例］ 以下、本発明の一実施例を図により説明する。[Example] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
第１図はこの実施例の拡大断面図であり、金属基板ＩＡ
は、最下層に高熱伝導性セラミックス層１６を有し、こ
のセラミックス層１６はＰＶＤ法またはＣＶＤ法により
金属板１１の表面に蒸着して形成される。そして、セラ
ミックス層１６の上に電気絶縁層１３を、さらにその上
に電気導体層１４としての銅箔を形成したものである。FIG. 1 is an enlarged sectional view of this embodiment, in which the metal substrate IA
has a highly thermally conductive ceramic layer 16 as the lowermost layer, and this ceramic layer 16 is formed by vapor deposition on the surface of the metal plate 11 by a PVD method or a CVD method. Then, an electrically insulating layer 13 is formed on the ceramic layer 16, and a copper foil as an electrically conductive layer 14 is further formed on the electrically insulating layer 13.
セラミックス層１６の厚さは１０μｍ程度であり、それ
自体で高電気絶縁性、高絶縁耐圧を有するので、合成樹
脂、ガラス等からなる電気絶縁層１３を薄くすることが
でき、その厚さは３０μｍ程度で十分である。The thickness of the ceramic layer 16 is about 10 μm, and since it has high electrical insulation properties and high dielectric strength voltage by itself, the electrical insulating layer 13 made of synthetic resin, glass, etc. can be made thin, and its thickness is 30 μm. It is enough.
高熱伝導性セラミックス層１６として用いられる材料は
、アルミナ（Ａ１２０３）、窒化アルミニウム（ＡＩＮ
）、ベリリア添加の炭化ケイ素（ＳｉＣ−Ｂｅｄ）、ダ
イヤモンドまたは立方晶窒化ホウ素（ｃ−ＢＮ）であり
、その平坦度は、例えばプラズマＣＶＤ法、レーザＰＶ
Ｄ法で蒸着することにより、０，２〜０．５μｍ程度に
することができた。また、蒸着によるためセラミックス
層１６中に不純物が混入することがほとんどなく、純度
がきわめて高い。さらに、蒸着にょる成膜速度は例えば
レーザＰＶＤ法ではＡ Ｉ ２０ ａで数十μｍ／ｓｉ
ｎときわめて高く、高速の被膜処理が可能である。The materials used for the highly thermally conductive ceramic layer 16 are alumina (A1203), aluminum nitride (AIN
), beryllia-doped silicon carbide (SiC-Bed), diamond or cubic boron nitride (c-BN), and its flatness is determined by, for example, plasma CVD, laser PV
By vapor depositing using method D, the thickness could be reduced to about 0.2 to 0.5 μm. Further, since the ceramic layer 16 is vapor-deposited, almost no impurities are mixed into the ceramic layer 16, and the purity is extremely high. Furthermore, the film formation rate by vapor deposition is, for example, several tens of μm/si at A I 20 a in the laser PVD method.
n, which is extremely high, and high-speed coating processing is possible.
上記材料の諸特性は第１表のとおりである。The properties of the above materials are shown in Table 1.
第１表
エポキシ樹脂の場合、熱伝導率は０．１〜ＩＷ／ｍ−に
であるので、上記材料の熱伝導率はそれぞれきわめて高
いことがわかる。しかも比抵抗が高いので電気絶縁性、
絶縁耐圧が高い。このようにセラミックス層１６は高熱
伝導性を有するため、この金属基板ＩＡにおいては放熱
性が良くなり、その結果、半導体素子等の実装密度を高
めることができる。また、熱膨張係数が金属板１１と大
きく異なる場合（例えばダイヤモンド）、セラミックス
層１６と金属板１１との間にさらに緩衝のための中間層
を入れるようにしてもよい。In the case of the epoxy resins in Table 1, the thermal conductivities are from 0.1 to IW/m-, so it can be seen that the thermal conductivities of the above materials are extremely high. Moreover, it has high specific resistance, so it is electrically insulating.
High dielectric strength. Since the ceramic layer 16 has high thermal conductivity in this manner, the metal substrate IA has good heat dissipation, and as a result, the packaging density of semiconductor elements and the like can be increased. Further, if the coefficient of thermal expansion is significantly different from that of the metal plate 11 (for example, diamond), an intermediate layer for buffering may be further inserted between the ceramic layer 16 and the metal plate 11.
金属板１１の材質はとくに限定されない。一般にＡｌ、
Ｃｕ系の材料が用いられるが、磁性材料を用いると電磁
シールドが可能になる。また、Ａｌ板の場合、従来のよ
うに陽極酸化処理を行う必要はないが、防食のためそれ
を行ってもむろん差し支えない。The material of the metal plate 11 is not particularly limited. Generally Al,
Although a Cu-based material is used, electromagnetic shielding becomes possible by using a magnetic material. In addition, in the case of an Al plate, it is not necessary to perform anodizing treatment as in the past, but it is of course possible to perform it for corrosion prevention.
［発明の効果］
以上のように本発明の金属基板は、金属板の表面に、ま
ず高熱伝導性セラミックス層を蒸着し、その上に合成樹
脂等の電気絶縁層及び銅箔等の電気導体層を形成したも
のであるので、セラミックス層の蒸着によってその成膜
速度は速く、平坦度も高いものが得られる。また、該セ
ラミックス層の有する高電気的特性、高熱伝導性のため
、該セラミックス層の上に形成される電気絶縁層の厚さ
を薄くすることができ、この結果放熱性が向上し、半導
体素子等の実装密度を大巾に向上させることができ、ハ
イブリッドＩＣ等に利用して大なる実効がある。[Effects of the Invention] As described above, in the metal substrate of the present invention, a highly thermally conductive ceramic layer is first deposited on the surface of the metal plate, and then an electrically insulating layer such as a synthetic resin and an electrically conductive layer such as a copper foil are applied thereon. Since the ceramic layer is formed by vapor deposition, the film formation rate is fast and a film with high flatness can be obtained. In addition, due to the high electrical properties and high thermal conductivity of the ceramic layer, the thickness of the electrical insulating layer formed on the ceramic layer can be reduced, which improves heat dissipation and improves the semiconductor device. It is possible to greatly improve the packaging density of semiconductor devices, etc., and it is very effective when used in hybrid ICs and the like.
第１図は本発明の一実施例を示す拡大断面図、第２図は
従来例の拡大断面図である。
ＩＡ・・・金属基板 １１・・・金属板１３・・
・電気絶縁層 １４・・・電気導体層１６・・・高
熱伝導性セラミックス層
＋ Ａ ： ４： ／Ｍｉｂ】−及
１６：高究告イ云厚・）生ヤラミッフヌ３會代理人 弁
理士 佐々木 宗 治FIG. 1 is an enlarged sectional view showing one embodiment of the present invention, and FIG. 2 is an enlarged sectional view of a conventional example. IA...Metal board 11...Metal plate 13...
・Electrical insulating layer 14...Electrical conductor layer 16...Highly thermally conductive ceramic layer + A: 4: /Mib】- and 16: High-level investigation Iyun Atsushi ・) Sei Yaramifunu 3 Association agent Patent attorney So Sasaki Osamu
Claims (3)
層を形成したものにおいて、前記金属板と電気絶縁層の
間に高熱伝導性セラミックス層を蒸着し、電気絶縁層の
厚さを薄くしたことを特徴とする集積回路用金属基板。(1) In a metal plate with an electrically insulating layer formed on the surface and an electrically conductive layer formed thereon, a highly thermally conductive ceramic layer is deposited between the metal plate and the electrically insulating layer to reduce the thickness of the electrically insulating layer. A metal substrate for integrated circuits characterized by its thinness.
炭化ケイ素系、ダイヤモンドまたは立方晶窒化ホウ素か
らなることを特徴とする請求項１に記載の集積回路用金
属基板。(2) The highly thermally conductive ceramic layer is aluminum nitride,
The metal substrate for an integrated circuit according to claim 1, characterized in that it is made of silicon carbide, diamond, or cubic boron nitride.
Ｄ法により蒸着したことを特徴とする請求項１に記載の
集積回路用金属基板。(3) Highly thermally conductive ceramic layer by PVD or CV
2. The metal substrate for an integrated circuit according to claim 1, wherein the metal substrate is deposited by method D.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21527488A JPH0265163A (en) | 1988-08-31 | 1988-08-31 | Metallic substrate for integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21527488A JPH0265163A (en) | 1988-08-31 | 1988-08-31 | Metallic substrate for integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0265163A true JPH0265163A (en) | 1990-03-05 |
Family
ID=16669599
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21527488A Pending JPH0265163A (en) | 1988-08-31 | 1988-08-31 | Metallic substrate for integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0265163A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103066036A (en) * | 2012-12-30 | 2013-04-24 | 杨渊翔 | Active heat dissipation substrate |
-
1988
- 1988-08-31 JP JP21527488A patent/JPH0265163A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103066036A (en) * | 2012-12-30 | 2013-04-24 | 杨渊翔 | Active heat dissipation substrate |
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