JPH0263229A - Burst signal communication equipment - Google Patents
Burst signal communication equipmentInfo
- Publication number
- JPH0263229A JPH0263229A JP63213555A JP21355588A JPH0263229A JP H0263229 A JPH0263229 A JP H0263229A JP 63213555 A JP63213555 A JP 63213555A JP 21355588 A JP21355588 A JP 21355588A JP H0263229 A JPH0263229 A JP H0263229A
- Authority
- JP
- Japan
- Prior art keywords
- data
- modulator
- signal
- burst signal
- data signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004891 communication Methods 0.000 title claims abstract description 16
- 230000005540 biological transmission Effects 0.000 claims abstract description 15
- 230000008054 signal transmission Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 1
Landscapes
- Time-Division Multiplex Systems (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はディジタル通信装置に関し、特にバースト信号
が可変長である場合に対応して、チャネルの利用効率を
向上させる為の技術に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital communication device, and particularly to a technique for improving channel utilization efficiency when a burst signal has a variable length.
多数の局が同一の搬送波を共有し１時分割にデータ信号
を交換するディジタル通信システム（例えば、衛星通信
システム）では、伝送効率の向上が最大の課題のひとつ
となる。従来は。In digital communication systems (eg, satellite communication systems) in which a large number of stations share the same carrier wave and exchange data signals on a time-division basis, improving transmission efficiency is one of the biggest challenges. conventionally.
この課題の解決策としてスロットアロノ１方式を採用し
ていた。As a solution to this problem, the slot Arono 1 system was adopted.
第３図は、この方式を実現する為のバースト信号通信装
置を示す。第３図を参照して、データ信号Ｓ１に、アド
レス付加回路４で発生した発信元と発信先を識別可能と
する為のアドレス情報をアドレス付加回路Ｆ３にて付加
する。更に、同期語バッファＦ６で発生した受信側との
同期を確立する為の同期語を、アドレス付加回路Ｆ３の
出力に同期語付加回路Ｆ５で付加してデータ信号Ｓ３を
得る。このデータ信号Ｓ３を変調器Ｆ７によって変調す
ることで最終的に発信すべきデータ信号Ｆ４が得られる
。FIG. 3 shows a burst signal communication device for realizing this method. Referring to FIG. 3, an address adding circuit F3 adds address information generated by an address adding circuit 4 to the data signal S1 so that the source and destination can be identified. Further, a synchronization word generated in the synchronization word buffer F6 for establishing synchronization with the receiving side is added to the output of the address addition circuit F3 by a synchronization word addition circuit F5 to obtain a data signal S3. By modulating this data signal S3 with a modulator F7, a data signal F4 to be finally transmitted is obtained.
上述した従来のディジタル通信装置により伝送効率は改
善できる。しかし１本来必要とされる以外の信号、いわ
ゆるヘッダ部が受信信号に占める割合が大きいため、チ
ャネルの利用効率が悪いという欠点がある。つまり、タ
イムシェアリングシステムにおける短パケツトデータ信
号の場合はともかくとして、パッチ処理におけるデータ
信号の如く、数パケットにも及ぶ場合。Transmission efficiency can be improved by the conventional digital communication device described above. However, since a signal other than what is originally required, the so-called header portion, occupies a large proportion of the received signal, there is a drawback that channel utilization efficiency is poor. In other words, apart from the case of a short packet data signal in a time sharing system, it also applies to cases of several packets, such as a data signal in patch processing.
各パケット毎にヘッダ部を付加する必要がある。It is necessary to add a header to each packet.
このことは、チャネルの利用効率の面からは非常に無駄
なことである。This is extremely wasteful in terms of channel utilization efficiency.
本発明は、このような問題点を鑑みてなされたもので、
その課題は、従来のスロットアロハ方式を採用しつつ、
へ、ダ部をできる限り付加しないで、チャネルの利用効
率を高めることにある。The present invention was made in view of these problems.
The challenge was to adopt the traditional slot Aloha method while
The objective is to increase the efficiency of channel use by adding as few additional sections as possible.
本発明は多数の局が同一の搬送波を共有し。 The present invention allows multiple stations to share the same carrier.
時分割にデータ信号を交換するディジタル通信システム
に於いて、特に可変長のデータ信号を交換するようなシ
ステムの場合に、送信装置に。In digital communication systems that exchange data signals on a time-division basis, especially in systems that exchange variable length data signals, for transmitting equipment.
データ長を検出して送信動作を制御する機能を付与する
ものである。This provides a function to detect the data length and control the transmission operation.
即ち１本発明のバースト信号通信装置は、送信部が、送
信データの送信元と受信元を示す為のアドレス情報を付
加するアドレス付加回路と。That is, one aspect of the burst signal communication device of the present invention includes an address adding circuit in which a transmitter adds address information for indicating a source and a receiver of transmission data.
受信部との同期を確立する為の同期語を付加する同期語
付加回路とを有し、加えてデータ信号中のデータ長を示
す部分を検出し、送信バッファ及び変調器に対してバー
スト信号の送信動作を制御する信号を出力する可変デー
タ対応変調器制御回路を有し、該可変データ対応変調器
制御回路からの制御により、可変長バースト信号の送信
を可能としたことを特徴とする。It has a synchronization word addition circuit that adds a synchronization word to establish synchronization with the receiving section, and also detects the part indicating the data length in the data signal and sends the burst signal to the transmission buffer and modulator. The present invention is characterized in that it has a variable data compatible modulator control circuit that outputs a signal for controlling a transmission operation, and is capable of transmitting a variable length burst signal under control from the variable data compatible modulator control circuit.
以下爺日
〔実施例〕
以下１本発明におけるバースト信号通信装置の一実施例
を図面を参照して説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [Embodiment] Hereinafter, one embodiment of a burst signal communication device according to the present invention will be described with reference to the drawings.
第１図は本発明におけるバースト信号通信装置の一実施
例を示す。尚、第３図に示す従来の装置と同一構成部分
には同一の符号を付してあり、この部分の説明は省略す
る。但し、データ信号Ｓ１に関しては２本発明ではデー
タ信号の最初にデータ長を示す信号が付加されている。FIG. 1 shows an embodiment of a burst signal communication device according to the present invention. Components that are the same as those of the conventional device shown in FIG. 3 are denoted by the same reference numerals, and a description of these parts will be omitted. However, regarding the data signal S1, in the present invention, a signal indicating the data length is added to the beginning of the data signal.
データ信号Ｓ１を受は取ると、可変データ対応変調器制
御回路Ｆ２において、データ信号Ｓ１のデータ長を示す
部分を検出し、送信バッファＦ１と変調器Ｆ７に対して
送信動作を制御する為の制御信号Ｓ２を出力することに
よって。When the data signal S1 is received, the variable data compatible modulator control circuit F2 detects a portion indicating the data length of the data signal S1, and controls the transmission buffer F1 and modulator F7 to control the transmission operation. By outputting signal S2.
アドレスと同期語を付加された後、変調器Ｆ７で変調さ
れたデータ信号Ｓ４を送信している。After adding an address and a synchronization word, a data signal S4 modulated by a modulator F7 is transmitted.
尚、送信バッフ７Ｆ１は、可変データ対応変調器制御回
路Ｆ２においてデータ長を検出している期間中、データ
信号を保持する為のものである。Note that the transmission buffer 7F1 is for holding the data signal during the period when the data length is being detected in the variable data compatible modulator control circuit F2.
なお、データ信号が数パケットにも及ぶ場合には、第２
図に示す如く、バースト間にもデータを送信する。Note that if the data signal spans several packets, the second
As shown in the figure, data is also transmitted between bursts.
以上説明したよう、に本発明は、ディジタル通信装置に
可変データ対応変調器制御回路を具備することにより、
１個のデータ信号につき１個のヘッダ部を付加すれば良
い。また、データ信号が数パケットにも及ぶ場合には、
バースト間にもデータを送信することができる為、チャ
ネルの利用効率の向上と（・う過大な効果を上げること
ができる。As explained above, the present invention provides a digital communication device with a variable data compatible modulator control circuit, thereby achieving
It is sufficient to add one header section to one data signal. Also, if the data signal spans several packets,
Since data can be transmitted even between bursts, it is possible to improve channel utilization efficiency and increase efficiency.
第１図は本発明のバースト信号通信装置の一実施例のプ
ロ、り構成図であり、第２図は本発明のデータ信号の構
成図であり、第３図は従来のバースト信号通信装置の一
実施例のブロック構成図である。
Ｐｌ：送信バッファ、Ｆ２：可変データ対応変調器制御
回路、Ｆ３ニアドレス付加回路。
Ｆ４ニアドレスバッファ、Ｆ５：同期語付加回路、Ｆ６
：同期語バッファ、Ｆ７：変調器。FIG. 1 is a block diagram of an embodiment of a burst signal communication device of the present invention, FIG. 2 is a block diagram of a data signal of the present invention, and FIG. 3 is a block diagram of a conventional burst signal communication device. FIG. 2 is a block configuration diagram of an embodiment. Pl: transmission buffer, F2: variable data compatible modulator control circuit, F3 near address addition circuit. F4 Near address buffer, F5: Synchronization word addition circuit, F6
: Sync word buffer, F7: Modulator.
Claims (1)
アドレス情報を付加するアドレス付加回路と、受信部と
の同期を確立する為の同期語を付加する同期語付加回路
とを有するバースト信号通信装置において、データ信号
中のデータ長を示す部分を検出し、送信バッファ及び変
調器に対してバースト信号の送信動作を制御する信号を
出力する可変データ対応変調器制御回路を有し、該可変
データ対応変調器制御回路からの制御により、可変長バ
ースト信号の送信を可能としたことを特徴とするバース
ト信号通信装置。1. The transmitter has an address adding circuit that adds address information to indicate the sender and receiver of the transmission data, and a synchronization word addition circuit that adds a synchronization word to establish synchronization with the receiver. A burst signal communication device includes a variable data compatible modulator control circuit that detects a portion indicating a data length in a data signal and outputs a signal for controlling a burst signal transmission operation to a transmission buffer and a modulator, A burst signal communication device characterized in that a variable length burst signal can be transmitted under control from the variable data compatible modulator control circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63213555A JP2871699B2 (en) | 1988-08-30 | 1988-08-30 | Burst signal communication device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63213555A JP2871699B2 (en) | 1988-08-30 | 1988-08-30 | Burst signal communication device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0263229A true JPH0263229A (en) | 1990-03-02 |
| JP2871699B2 JP2871699B2 (en) | 1999-03-17 |
Family
ID=16641146
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63213555A Expired - Lifetime JP2871699B2 (en) | 1988-08-30 | 1988-08-30 | Burst signal communication device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2871699B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010124492A (en) * | 2010-02-10 | 2010-06-03 | Sony Corp | Wireless transmission method and wireless transmission apparatus |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6020414A (en) * | 1983-07-15 | 1985-02-01 | 株式会社日立製作所 | Contact inserting device |
| JPS61100046A (en) * | 1984-10-22 | 1986-05-19 | Mitsubishi Electric Corp | Loop transmission method |
-
1988
- 1988-08-30 JP JP63213555A patent/JP2871699B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6020414A (en) * | 1983-07-15 | 1985-02-01 | 株式会社日立製作所 | Contact inserting device |
| JPS61100046A (en) * | 1984-10-22 | 1986-05-19 | Mitsubishi Electric Corp | Loop transmission method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010124492A (en) * | 2010-02-10 | 2010-06-03 | Sony Corp | Wireless transmission method and wireless transmission apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2871699B2 (en) | 1999-03-17 |
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