JPH0260192A - Printed board device - Google Patents
Printed board deviceInfo
- Publication number
- JPH0260192A JPH0260192A JP21206788A JP21206788A JPH0260192A JP H0260192 A JPH0260192 A JP H0260192A JP 21206788 A JP21206788 A JP 21206788A JP 21206788 A JP21206788 A JP 21206788A JP H0260192 A JPH0260192 A JP H0260192A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- layer
- soldering
- melting point
- low melting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910000679 solder Inorganic materials 0.000 claims abstract description 70
- 238000005476 soldering Methods 0.000 claims abstract description 23
- 230000008018 melting Effects 0.000 claims abstract description 17
- 238000002844 melting Methods 0.000 claims abstract description 17
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 8
- 239000011889 copper foil Substances 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 6
- 238000004806 packaging method and process Methods 0.000 abstract 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 14
- 238000007747 plating Methods 0.000 description 5
- 239000006071 cream Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000005496 eutectics Effects 0.000 description 3
- 239000000155 melt Substances 0.000 description 3
- 239000000654 additive Substances 0.000 description 2
- 229910052797 bismuth Inorganic materials 0.000 description 2
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000004381 surface treatment Methods 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 229910052793 cadmium Inorganic materials 0.000 description 1
- BDOSMKKIYDKNTQ-UHFFFAOYSA-N cadmium atom Chemical compound [Cd] BDOSMKKIYDKNTQ-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
- 239000000230 xanthan gum Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
［発明の目的１
（産業上の利用分野）
この発明は、半田付けの前処理工程として、半田付りラ
ンド表面に半田を用いた表面処理を行うプリント基板装
置に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention 1 (Industrial Field of Application) The present invention relates to a printed circuit board device that performs surface treatment using solder on the surface of a soldering land as a pre-treatment step for soldering.
（従来の技術）
プリント基板の製造工程において、回路部品を実装する
段階での半田付けの信頼性を畠めるため、前処理工程と
して、プリント基板の銅箔による半田付はランドに、予
め半田を塗布している。(Prior art) In the manufacturing process of printed circuit boards, in order to ensure the reliability of soldering at the stage of mounting circuit components, as a pretreatment process, soldering with copper foil on printed circuit boards is performed by applying solder to the land in advance. is applied.
このような表面処理を半田レベラー処理と称し、略して
ＨＡＬ処理と呼んでいる。ｌ−Ｉ Ａ Ｌ処理によって
形成する半ＯＩは、略３５［μｌ１１１の厚みでよく、
これは下層の銅、箔と等しいかそれ以下の厚みである。Such surface treatment is called solder leveler treatment, or HAL treatment for short. The half-OI formed by the l-I AL process may have a thickness of about 35 [μl111,
This is equal to or less than the thickness of the underlying copper or foil.
従来、プリントＵ板のト１ΔＬ処理に用いる半田は、錫
（Ｓｎ ）６３％、鉛（Ｐｂ）３７％の共晶半日１を用
いている。Conventionally, the solder used for the t1ΔL treatment of printed U boards is eutectic half-day 1 containing 63% tin (Sn) and 37% lead (Pb).
上記組成の共晶半田を用いたＨＡＬ処理は、共晶１′田
の溶融温度が１８３℃であることから、ＨＡｍ処理用半
田槽温度を、半田の流動性を加味し、２３０〜２４０℃
に設定するのが一般的である。In HAL processing using eutectic solder with the above composition, since the melting temperature of eutectic 1' solder is 183°C, the solder bath temperature for HAM processing is set to 230 to 240°C, taking into account the fluidity of the solder.
It is common to set it to .
しかしながら、上記のような半田槽の温度であると、第
３図に示すように、適正な厚みで形成さ゛れる半田層３
４の下層に、厚いＳｎ拡散層３３が生じてしまう。However, if the temperature of the solder bath is as described above, the solder layer 3 formed with an appropriate thickness as shown in FIG.
A thick Sn diffusion layer 33 is formed under the layer 4.
即ち、第３図において、３１は絶縁基板、３２は銅箔に
よる了田付はランドであり、半「１付はランド３２の表
面側を、Ｆ１ΔＬ処理用半田槽に付けると、半田付はラ
ンド３２の表面に、半田層３４より厚くＳｎ拡散層３３
が形成される。That is, in FIG. 3, 31 is an insulating board, 32 is a land that is attached with copper foil, and when the surface side of the land 32 is attached to the solder bath for F1ΔL processing, the solder is attached to the land 32. On the surface of the Sn diffusion layer 33, which is thicker than the solder layer 34,
is formed.
このようなＳｎ拡散層３３は、半田温度が高いほど、ま
た、半田付は時間が長くなるほど、成長する傾向にあり
、厚みを増してしまう。そして、このＳｎ拡散層３３の
厚みが増すほど、実装段階での半田付けの際、再溶融温
度を高めなければならない。実装段階での半田槽温度が
高いと、例えば面実装部品等が位置ずれを起こし、半Ｉ
Ｉ付Ｇノの信頼性が低下する。Such Sn diffusion layer 33 tends to grow and becomes thicker as the soldering temperature becomes higher and the soldering time becomes longer. As the thickness of this Sn diffusion layer 33 increases, the remelting temperature must be increased during soldering at the mounting stage. If the temperature of the solder bath during the mounting stage is high, for example, surface mount components may become misaligned, resulting in half-I
The reliability of G with I decreases.
また、１−ＩＡＬ処理や実装段階での半０】槽温度が＾
いと、プリント基板が反りを起こし、半田付はランドの
パターン切れを招いて、更に半田付けの信頼性を低下さ
せてしまう。In addition, the tank temperature at 1-IAL processing and mounting stage is half zero.
Otherwise, the printed circuit board will warp and the soldering pattern will break, further reducing the reliability of the soldering.
（発明が解決しＪ、うどする課題）
このように、ＨＡ Ｌ処理を行う従来のプリント基板は
、１」Ａ Ｌ処理の段階での半田槽ｆｆ１度が高いため
に、銅箔表面にＳｎ拡散層３３を成長させてしまう。こ
の３ｎ拡散層３３が厚いと、実装段階での半田槽温度を
上げなければならず、所定温石以上に上げると、面実装
部品が不用意に移動したり、プリント基板が反りを起こ
してしまう。(Problems to be Solved and Improved by the Invention) As described above, conventional printed circuit boards subjected to HAL processing have a high solder bath ff1 degree at the 1" AL processing stage, which causes Sn diffusion on the surface of the copper foil. This causes layer 33 to grow. If the 3n diffusion layer 33 is thick, the temperature of the solder bath must be increased during the mounting stage, and if the temperature is increased above a predetermined temperature, the surface-mounted components may move inadvertently or the printed circuit board may warp.
この発明は上記問題点を除去し、３ｎ拡散層を生ずるこ
となく、半田付ｔノ信頼性の高いプリント基板装置の提
供を［ｉ的とする。The present invention aims to eliminate the above-mentioned problems and provide a printed circuit board device with high soldering reliability without producing a 3N diffusion layer.
［発明の構成］
（課題を解決するための手段）
この発明は、半田付はランド表面を半田レベラー処理す
るプリント基板装置において、前記半田レベラー処理用
半田として低融点半田を用いる。[Structure of the Invention] (Means for Solving the Problems) According to the present invention, a low melting point solder is used as the solder for the solder leveler treatment in a printed circuit board device in which the land surface is treated with a solder leveler.
（作用）
このような半田を用いることで、１−１へＬ処理時の半
田槽温度を２００℃以下にして、３ｎ拡散層の成長を軽
減する。このため、実装段階での半田槽Ｎ＋Ｕを下げる
ことができ、それに応じて半田が溶融している０４問が
短くなって、面実装部品の半田イ１け性を向上する。ま
た、基板の反りを防止づることができる。(Function) By using such a solder, the temperature of the solder bath during the 1-1 L process is set to 200° C. or less, thereby reducing the growth of the 3n diffusion layer. Therefore, the solder tank N+U at the mounting stage can be lowered, and accordingly, the number of times during which the solder is melted is shortened, improving the solderability of surface-mounted components. Further, it is possible to prevent the substrate from warping.
（実施例）
以下、この発明を実施例について図面に基づき説明する
。(Example) The present invention will be described below with reference to the drawings.
第１図はこの発明に係るプリント基板装置の一実施例の
構成を説明する構成図である。FIG. 1 is a configuration diagram illustrating the configuration of an embodiment of a printed circuit board device according to the present invention.
第１図において、１０はこの発明によるプリント基板装
置、１１は絶縁基板、１２は絶Ｆ＆基板１１上に印刷に
よって形成した半田付はランドである。In FIG. 1, 10 is a printed circuit board device according to the present invention, 11 is an insulating substrate, and 12 is a soldering land formed by printing on the F & board 11. In FIG.
この実施例によるプリント基板装＠１０は、上記半田付
はランド１２の表面に、低融点半田を用いた半田メツキ
層１５を形成したちのＣある。In the printed circuit board assembly @10 according to this embodiment, the soldering process is performed by forming a solder plating layer 15 using a low melting point solder on the surface of the land 12.
上記低融点半田による半田メツキＥ４１５は、半田イ１
けランド１２の表面に形成される３ｎ拡散層１３と、そ
の上層に形成される崖田層１４とから成る。Solder plating E415 using the above low melting point solder is solder I1.
It consists of a 3n diffusion layer 13 formed on the surface of the free land 12, and a cliff layer 14 formed on top of the 3n diffusion layer 13.
このように、１１ＡＬ処理用半田として低融点半田を用
いることで、１−１Ａ Ｌ処理半田４ｆ！温痕を、従来
のｆＡ ＦｆＩにり低く、例えば２００℃以下に設定す
ることができる。ＨＡＬ処理半田槽渇度が、上記の温度
程度に低いと、３ｎ拡散層１３は、はとんど形成されず
、極めて薄くすることができる。In this way, by using a low melting point solder as the 11AL processing solder, the 1-1AL processing solder 4f! The heat mark can be set lower than that of the conventional fA FfI, for example, at 200° C. or lower. When the HAL processing solder bath dryness is as low as the above-mentioned temperature, the 3n diffusion layer 13 is hardly formed and can be made extremely thin.
こうして、Ｓｎ拡散層１３の厚みが薄いと、実装段階に
おける半田槽温度を従来より下げても、低融点の半田層
１４が容易に溶融し、半田の諾れ性が向モして、半田付
けの信頼性を畠める。In this way, if the Sn diffusion layer 13 is thin, even if the solder bath temperature at the mounting stage is lower than before, the low melting point solder layer 14 will easily melt, improving solder acceptability, and soldering Establish reliability.
また、この発明による半田メツキ層１５は、低融点半田
が素材であるので、例えばりフロー半田付は方法を用い
て半田付けを行う場合に、クリーム半田より先に、半田
メツキ層１５が溶融し、銅箔に対づる半８１溶融時１１
−１を短縮することができる。半Ｉｎ溶融時間が短くな
ると、半田付けの困難性が比較的高い面実装部品を、確
実に半田付けすることができる。Furthermore, since the solder plating layer 15 according to the present invention is made of low melting point solder, for example, when soldering is performed using a flow soldering method, the solder plating layer 15 melts before the cream solder. , 11 when half 81 melts against copper foil
-1 can be shortened. When the half-In melting time is shortened, surface mount components that are relatively difficult to solder can be reliably soldered.
第２図は、面実装部品１６をこの発明により１−１ΔＬ
処即したプリント基板装置１０に取イ４けた場合の、接
続状態を示寸。１１は絶ｎ基板、１２は半田付ｔノラン
ド、１３１よＳｎ拡散層、１７はクリーム半田、１８は
面実装部品１６の電極である。融点の低い半０１層１４
は、クリーム半田１７より先に溶融、し、クリーム半田
１７との融合を促す。これにより、銅箔に対重るする半
田溶融時間が短くなり、面実装部品１Ｇが不用意に移動
する距離が少なくなって、面突′＠部品の半ＩＩＩ （
＝Ｉけ性能を向上するようになる。FIG. 2 shows a surface mount component 16 of 1-1ΔL according to the present invention.
This figure shows the connection state when there are 4 digits on the printed circuit board device 10. Reference numeral 11 designates a soldering board, 12 a soldering board, 131 an Sn diffusion layer, 17 cream solder, and 18 an electrode of the surface mount component 16. Semi-01 layer 14 with low melting point
melts before the cream solder 17 and promotes fusion with the cream solder 17. As a result, the melting time of the solder applied to the copper foil is shortened, and the distance that the surface mount component 1G has to move inadvertently is reduced.
= Improved performance.
更に、１」Ａシ処理半田層温度が低い効果は、プリント
基板の反りを生じないことである。このため、銅箔パタ
ーンが不用意に切断することがなくなる。Furthermore, the effect of the low temperature of the 1"A solder layer is that the printed circuit board does not warp. This prevents the copper foil pattern from being accidentally cut.
また、低融点半田としては、５ｎ−Ｐｂ系半田に、例え
ば所定Ｒのビスマス（Ｂｉ）を添加して得られる。そし
て、このビスマス等の添加物を加減することで、５０℃
〜１６０℃にも、融点が低下された半田を作ることがで
きる。また、上記添加物は、カドミウム、インジウム等
でもよい。Further, the low melting point solder can be obtained by adding bismuth (Bi) of a predetermined R to 5n-Pb solder, for example. By adjusting the amount of additives such as bismuth, it is possible to
Solder with a lowered melting point can be produced even at ~160°C. Further, the additive may be cadmium, indium, or the like.
［発明の効果］
以上説明したようにこの発明によれば、ｌ−Ｉ Ａ Ｌ
処理時における３ｎ拡散層の成長を軽減し、実装段階で
の半田付は性を向上する効果がある。[Effect of the invention] As explained above, according to this invention, l-I A L
The growth of the 3n diffusion layer during processing is reduced, and soldering at the mounting stage has the effect of improving performance.
第１図はこの発明に係るプリント基板装置の一実施例を
示−４構成図、第２図はこの発明により面実装部品を取
付けた状態を示り説明図、第３図は従来のプリント基板
装置を示づ構成図である。
１１・・・絶縁基板、
１２・・・半田イー１けランド、
１３・・・３ｎ拡ａ層、
１４・・・半田層、
１５・・・半田メツキ層、
１６・・・面実装部品。Fig. 1 is a configuration diagram showing one embodiment of a printed circuit board device according to the present invention, Fig. 2 is an explanatory diagram showing a state in which surface-mounted components are attached according to the present invention, and Fig. 3 is a conventional printed circuit board. FIG. 2 is a configuration diagram showing the device. DESCRIPTION OF SYMBOLS 11... Insulating board, 12... Solder E1 land, 13... 3N expansion layer, 14... Solder layer, 15... Solder plating layer, 16... Surface mount component.
Claims (1)
基板装置において、前記半田レベラー処理用半田として
低融点半田を用いたことを特徴とするプリント基板装置
。1. A printed circuit board device in which a surface of a soldering land is treated with a solder leveler, characterized in that a low melting point solder is used as the solder for the solder leveler treatment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21206788A JPH0260192A (en) | 1988-08-26 | 1988-08-26 | Printed board device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21206788A JPH0260192A (en) | 1988-08-26 | 1988-08-26 | Printed board device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0260192A true JPH0260192A (en) | 1990-02-28 |
Family
ID=16616319
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21206788A Pending JPH0260192A (en) | 1988-08-26 | 1988-08-26 | Printed board device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0260192A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6902098B2 (en) * | 2001-04-23 | 2005-06-07 | Shipley Company, L.L.C. | Solder pads and method of making a solder pad |
-
1988
- 1988-08-26 JP JP21206788A patent/JPH0260192A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6902098B2 (en) * | 2001-04-23 | 2005-06-07 | Shipley Company, L.L.C. | Solder pads and method of making a solder pad |
| US6927492B2 (en) | 2001-04-23 | 2005-08-09 | Shipley Company, L.L.C. | Solder pads and method of making a solder pad |
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