JPH0258236B2 - - Google Patents
Info
- Publication number
- JPH0258236B2 JPH0258236B2 JP9626181A JP9626181A JPH0258236B2 JP H0258236 B2 JPH0258236 B2 JP H0258236B2 JP 9626181 A JP9626181 A JP 9626181A JP 9626181 A JP9626181 A JP 9626181A JP H0258236 B2 JPH0258236 B2 JP H0258236B2
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- layer
- multilayer ceramic
- substrate
- green sheet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004020 conductor Substances 0.000 claims description 32
- 239000000758 substrate Substances 0.000 claims description 24
- 239000000919 ceramic Substances 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 10
- 238000010304 firing Methods 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 238000003475 lamination Methods 0.000 description 4
- 238000007639 printing Methods 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Description
【発明の詳細な説明】
本発明は、焼成時における収縮による基板上導
体層の変形および精度のばらつきを防止する多層
セラミツク基板の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a multilayer ceramic substrate that prevents deformation of conductor layers on the substrate and variations in accuracy due to shrinkage during firing.
従来、IC等の実装用多層セラミツク基板はア
ルミナ基板上に導体配線層、絶縁層を交互に印刷
する方法によつて多層構造が実現されていた。 Conventionally, the multilayer structure of multilayer ceramic substrates for mounting ICs and the like has been achieved by alternately printing conductive wiring layers and insulating layers on an alumina substrate.
この方法では、多層の印刷ごとに焼成を行なわ
なければならず、作業性の面でも経済性の面でも
欠点があり、さらに微細パターンの設計が困難で
層数も５層以下の積層しか出来なかつた。さらに
近年、コンピユータ、通信、民生機器等々の高性
能化や小型化に伴つて配線密度の高いLSI実装用
の多層セラミツク基板を要望する声が日に日に高
まつている。 This method requires baking after each multilayer printing, which has drawbacks in terms of both workability and economy.Furthermore, it is difficult to design fine patterns, and the number of layers can only be laminated with five or less layers. Ta. Furthermore, in recent years, with the increasing performance and miniaturization of computers, communications, consumer equipment, etc., the demand for multilayer ceramic substrates for LSI mounting with high wiring density is increasing day by day.
そこで、前記欠点を解決し、かつ、配線密度の
高いLSIの実装用多層セラミツク基板の製造方法
としてグリーンシート積層法による多層セラミツ
ク基板が最も注目されている。 Therefore, a multilayer ceramic substrate using the green sheet lamination method is attracting the most attention as a method for manufacturing a multilayer ceramic substrate for LSI mounting with high wiring density and solving the above-mentioned drawbacks.
第１図にグリーンシート積層法によつて形成さ
れた多層セラミツク基板の断面図を模式的に示
す。一般にグリーンシート積層法による多層セラ
ミツク基板の製造は、先ず厚み0.01〜0.2mmのグ
リーンシート１の上にスクリーン印刷法等によ
り、例えば金・白金・モリブデン若しくはタング
ステンなど、又はこれらの一種類以上を含む導体
配線層２を印刷し、さらには0.2mm以下の径をも
つスルーホール３に上下導体配線層間の導通が可
能になるように導体を埋める。そしてこれらの印
刷されたグリーンシートを積層し熱圧着した後、
焼成せしめることによつて多層セラミツク基板が
作られていた。 FIG. 1 schematically shows a cross-sectional view of a multilayer ceramic substrate formed by the green sheet lamination method. Generally, in manufacturing a multilayer ceramic substrate by the green sheet lamination method, first, a green sheet 1 having a thickness of 0.01 to 0.2 mm is coated with a material such as gold, platinum, molybdenum, or tungsten, or one or more of these, by screen printing or the like. A conductor wiring layer 2 is printed, and furthermore, a conductor is filled in the through hole 3 having a diameter of 0.2 mm or less so as to enable conduction between the upper and lower conductor wiring layers. After stacking these printed green sheets and bonding them with heat,
Multilayer ceramic substrates were made by firing.
しかしながら、従来のこのグリーンシート積層
法においては、焼成時における各グリーンシート
の収縮率が不均一であること、および導体とセラ
ミツクとの収縮率が本質的に異なつていること、
さらに導体パターン密度の不均一等に起因して基
板最上面の導体層の変形および寸法精度のばらつ
きが発生する欠点があり、塔載する微細なLSI、
IC等のピン位置と正確に一致しない場合が生じ、
それが多層セラミツク基板の製造における歩留り
を低下させていた。 However, in this conventional green sheet lamination method, the shrinkage rate of each green sheet during firing is uneven, and the shrinkage rates of the conductor and ceramic are essentially different.
Furthermore, due to non-uniform conductor pattern density, deformation of the conductor layer on the top surface of the board and variations in dimensional accuracy occur.
There may be cases where the pin position does not match the pin position of the IC etc.
This has lowered the yield in manufacturing multilayer ceramic substrates.
本発明の目的は、このような従来法の欠点であ
る、焼成時の収縮による基板最上面の導体層の変
形および寸法精度のばらつきを防止せしめた多層
セラミツク基板の製造方法を提供することにあ
る。 An object of the present invention is to provide a method for manufacturing a multilayer ceramic substrate that prevents deformation of the conductor layer on the top surface of the substrate and variations in dimensional accuracy due to shrinkage during firing, which are disadvantages of the conventional method. .
本発明によれば、導体層を形成した所定枚数の
グリーンシートを重ね、さらにその上にスルーホ
ールを設けたグリーンシートを重ねて熱圧着して
焼成し、その焼成された積層体最上層に導体層を
形成しその導体層を焼成することを特徴とする多
層セラミツク基板の製造方法が得られる。 According to the present invention, a predetermined number of green sheets each having a conductor layer formed thereon are stacked, and then a green sheet provided with a through hole is further stacked on top of the green sheets, thermocompression-bonded and fired, and the conductor is placed on the top layer of the fired laminate. A method for manufacturing a multilayer ceramic substrate is obtained, which is characterized by forming layers and firing the conductive layer.
以下本発明について図面を用いて説明する。 The present invention will be explained below with reference to the drawings.
第２図は、本発明の一実施例を説明するための
切り欠き断面斜視図である。スルーホールの開い
たグリーンシート１上に導体配線層２を印刷した
ものを積層する。このとき基板最上部に導体配線
層を印刷していないスルーホールの開いたグリー
ンシート１１を積層する。導体物質として例えば
Au，Al，Ag，Pt，Ｗ，Pd，Cu，Ni，Cr、若し
くはMo等々の単体又はこれらを１以上含む合金
が好都合である。 FIG. 2 is a cutaway sectional perspective view for explaining one embodiment of the present invention. A printed conductor wiring layer 2 is laminated on a green sheet 1 having through holes. At this time, a green sheet 11 with through-holes on which no conductor wiring layer is printed is laminated on the top of the substrate. For example, as a conductive material
Au, Al, Ag, Pt, W, Pd, Cu, Ni, Cr, Mo, etc. alone or alloys containing one or more of these are convenient.
この積層体を焼成するのであるが、この時、各
グリーンシートの収縮率が不均一であること、お
よび導体とセラミツクとの収縮率が本質的に異な
つていること、さらに導体パターン密度の不均一
等により、基板には長さ方向の形状の変形、ひず
みが発生する危険性がある。当然基板最上層にお
いても同様であり長さ方向の形状の変形、ひずみ
が発生する危険性がある。 This laminate is fired, but at this time, the shrinkage rates of each green sheet are uneven, the shrinkage rates of the conductor and ceramic are essentially different, and the conductor pattern density is uneven. As a result, there is a risk that the board may be deformed or distorted in the length direction. Naturally, the same applies to the uppermost layer of the substrate, and there is a risk that deformation and distortion of the shape in the length direction may occur.
一般に基板最上層は、例えばIC、LSI等のチツ
プを塔載・ボンデイングしたり、また外部との接
続に利用したりするための層であり、普通ランド
状の導体層が形成されることになる。そこで下部
導体層とスルーホールを介して接続される最上部
導体層の各ランドの形状は一般に基板内部の導体
配線パターンに比して面積的には大きく取ること
が可能なため、最上部導体層を形成していない焼
成基板の長さ方向の形状の変形・ひずみ、すなわ
ち、ある程度の範囲内で収縮率のばらつきを考慮
して設計することが十分可能である。 Generally, the top layer of a board is a layer for mounting and bonding chips such as ICs and LSIs, and is also used for connection with the outside, and usually a land-shaped conductor layer is formed. . Therefore, since the shape of each land of the top conductor layer that is connected to the bottom conductor layer via a through hole can generally be larger in area compared to the conductor wiring pattern inside the board, the top conductor layer It is fully possible to design by taking into consideration the deformation and strain in the shape of the fired substrate in the length direction, that is, the variation in shrinkage rate within a certain range.
次にこの焼成された基板最上層に第３図に示す
ごとく収縮による長さ方向の形状の変形・ひずみ
を考慮して導体層２１を印刷し、焼成する。この
焼成は導体を焼成するためだけのものでこの段階
では基板の収縮は起らないため、印刷された基板
最上層の導体層精度は印刷による精度範囲内にあ
り、非常に精度のよいチツプ搭載面（基板最上
層）をもつ多層セラミツク基板が得られることに
なる。 Next, as shown in FIG. 3, a conductor layer 21 is printed on the uppermost layer of the fired substrate, taking into account the deformation and distortion of the shape in the longitudinal direction due to shrinkage, and is fired. This firing is only to fire the conductor, and the board does not shrink at this stage, so the accuracy of the conductor layer on the top layer of the printed board is within the accuracy range of printing, and the chip is mounted with very high precision. A multilayered ceramic substrate with a surface (top layer of the substrate) will be obtained.
このように、一般焼成した基板に導体を印刷し
さらに導体を焼成させる本発明の多層セラミツク
基板の製造方法を採用することにより、基板最上
層とそれより下部層との導体の接続を考慮して基
板最上層の導体パターンを余裕をもたせて設計す
ることで厳密な基板の収縮率のコントロールを必
要としないとも、IC、LSI等の塔載面（基板最上
層）の位置精度を十分良好にすることが出来るよ
うになつた。 In this way, by employing the method of manufacturing a multilayer ceramic board of the present invention in which a conductor is printed on a conventionally fired board and then fired, the connection of the conductor between the uppermost layer of the board and the lower layer can be taken into consideration. By designing the conductor pattern on the top layer of the board with enough margin, the positioning accuracy of the mounting surface (top layer of the board) for ICs, LSIs, etc. can be made sufficiently high even if strict control of the shrinkage rate of the board is not required. Now I can do it.
第１図は多層セラミツク基板の断面図、第２図
及び第３図は本発明の実施例を説明するための多
層セラミツク基板の切り欠き斜視断面図である。
図において、１はセラミツクグリーンシート、
２は導体配線層、３はスルーホール、１１は導体
印刷をしていないスルーホールの開いたセラミツ
クグリーンシート、２１は基板焼成後印刷した導
体層である。
FIG. 1 is a sectional view of a multilayer ceramic substrate, and FIGS. 2 and 3 are cutaway perspective sectional views of the multilayer ceramic substrate for explaining an embodiment of the present invention. In the figure, 1 is a ceramic green sheet;
2 is a conductor wiring layer, 3 is a through hole, 11 is a ceramic green sheet with through holes without conductor printing, and 21 is a conductor layer printed after firing the substrate.
Claims (1)
を重ね、さらにその上にスルーホールを設けたグ
リーンシートを重ねて熱圧着して焼成し、その焼
成された積層体最上層に導体層を形成しその導体
層を焼成することを特徴とする多層セラミツク基
板の製造方法。1 A predetermined number of green sheets on which a conductor layer has been formed are stacked, and then a green sheet with through-holes is placed on top of the green sheets, thermocompression bonded and fired, and a conductor layer is formed on the top layer of the fired laminate. A method for manufacturing a multilayer ceramic substrate, characterized by firing a conductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9626181A JPS57209891A (en) | 1981-06-22 | 1981-06-22 | Manufacture of multilayer ceramic substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9626181A JPS57209891A (en) | 1981-06-22 | 1981-06-22 | Manufacture of multilayer ceramic substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57209891A JPS57209891A (en) | 1982-12-23 |
| JPH0258236B2 true JPH0258236B2 (en) | 1990-12-07 |
Family
ID=14160230
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9626181A Granted JPS57209891A (en) | 1981-06-22 | 1981-06-22 | Manufacture of multilayer ceramic substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57209891A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06105832B2 (en) * | 1989-03-27 | 1994-12-21 | 日本碍子株式会社 | Ceramic multilayer wiring board and manufacturing method thereof |
-
1981
- 1981-06-22 JP JP9626181A patent/JPS57209891A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57209891A (en) | 1982-12-23 |
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