JPH0257626U - - Google Patents
Info
- Publication number
- JPH0257626U JPH0257626U JP13770988U JP13770988U JPH0257626U JP H0257626 U JPH0257626 U JP H0257626U JP 13770988 U JP13770988 U JP 13770988U JP 13770988 U JP13770988 U JP 13770988U JP H0257626 U JPH0257626 U JP H0257626U
- Authority
- JP
- Japan
- Prior art keywords
- amplifier
- input
- unbalanced circuit
- whose
- buffer amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Testing Electric Properties And Detecting Electric Faults (AREA)
- Networks Using Active Elements (AREA)
Description
第１図はこの考案の一実施例を示すブロツク図
、第２図はこの考案による平衡−不平衡変換器の
外観の一例を示す斜視図、第３図は従来の技術を
説明するための接続図である。
１Ａ，１Ｂ……入力増幅器、２Ａ，２Ｂ……可
変遅延回路、３Ａ，３Ｂ……バツフア増幅器、４
……電池。
Fig. 1 is a block diagram showing an embodiment of this invention, Fig. 2 is a perspective view showing an example of the external appearance of a balanced-unbalanced converter according to this invention, and Fig. 3 shows connections for explaining the conventional technology. It is a diagram. 1A, 1B...Input amplifier, 2A, 2B...Variable delay circuit, 3A, 3B...Buffer amplifier, 4
……battery.
Claims (1)
力増幅器と、この入力増幅器の出力側に設けられ
たバツフア増幅器と、上記演算増幅器及びバツフ
ア増幅器を動作させる電池と、から成る平衡−不
平衡変換器。 A balanced-unbalanced circuit consisting of an input amplifier whose input is a differential input and whose output is an unbalanced circuit, a buffer amplifier provided on the output side of this input amplifier, and a battery that operates the operational amplifier and buffer amplifier. converter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13770988U JPH0257626U (en) | 1988-10-21 | 1988-10-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13770988U JPH0257626U (en) | 1988-10-21 | 1988-10-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0257626U true JPH0257626U (en) | 1990-04-25 |
Family
ID=31399380
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13770988U Pending JPH0257626U (en) | 1988-10-21 | 1988-10-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0257626U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5191710A (en) * | 1974-12-30 | 1976-08-11 | ||
| JPS5731219A (en) * | 1980-07-31 | 1982-02-19 | Fujitsu Ltd | Balance-to-unbalance converting circuit |
-
1988
- 1988-10-21 JP JP13770988U patent/JPH0257626U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5191710A (en) * | 1974-12-30 | 1976-08-11 | ||
| JPS5731219A (en) * | 1980-07-31 | 1982-02-19 | Fujitsu Ltd | Balance-to-unbalance converting circuit |