JPH0254951A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0254951A JPH0254951A JP20699488A JP20699488A JPH0254951A JP H0254951 A JPH0254951 A JP H0254951A JP 20699488 A JP20699488 A JP 20699488A JP 20699488 A JP20699488 A JP 20699488A JP H0254951 A JPH0254951 A JP H0254951A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- layer
- film
- titanium nitride
- line width
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 239000010410 layer Substances 0.000 abstract description 27
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 abstract description 15
- 229910000881 Cu alloy Inorganic materials 0.000 abstract description 13
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 11
- 229910000838 Al alloy Inorganic materials 0.000 abstract description 9
- 239000011229 interlayer Substances 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052751 metal Inorganic materials 0.000 abstract description 5
- 239000002184 metal Substances 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 3
- 230000004888 barrier function Effects 0.000 abstract description 2
- 239000000463 material Substances 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 abstract 2
- 239000011248 coating agent Substances 0.000 abstract 2
- 238000000576 coating method Methods 0.000 abstract 2
- 239000011247 coating layer Substances 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 238000003475 lamination Methods 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 7
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910000676 Si alloy Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、半導体装置における配線の構造並びにその形
状に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure and shape of wiring in a semiconductor device.
［従来の技術］
従来の半導体装置では、一般にその配線はアルミニウム
・シリコン合金単層でできており、その膜厚もｙ ｏ
ｏ ｏ Ｋ１度であった。しかし近年の微細化の進展に
より、コンタクト抵抗の低減やエレクトロマイグレーシ
ョン耐性の向上環が必要となってきており、これらを改
善するために、従来前述のように単層酵造であった金属
配線を多層構造化し、例えば第３図のように、最下層に
バリアメタルとして第１の窒化チタン層３０３を１００
０人形成し、シリコン基板３ｏ１とアルミニウム・銅合
金層５０４との直接接触を避け、シリコンとアルミニウ
ムとの反応を防止した後に、主配線として、従来のアル
ミニウム・シリコン合金よりもエレクトロマイグレーシ
ョン耐圧が大キいアルミニウム・銅合金３０４を７００
０Ｘ形成し、さらにその上に、キャップメタルとして第
２の窒化チタンＪｉ３ｏｓを１ｏｏｏＸ形成し、アルミ
ニウム・銅合金３０４中でアルミニウム結晶が局部的に
太き（成長する、いわゆるヒルロックを防止するととも
に、アルミニウム・銅合金層３０４表面での強い光の反
射防止することが必要不可欠となってきていた。このと
き、寸法制御精度をよくする必要上、エツチングはドラ
イエツチングで行なっており、しかも単一条件で５層を
同時に異方的にエツチングし、その形状は垂直になって
いた。[Prior Art] In conventional semiconductor devices, the wiring is generally made of a single layer of aluminum-silicon alloy, and the film thickness is also yo
o o K1 degree. However, with the recent progress in miniaturization, it has become necessary to reduce contact resistance and improve electromigration resistance. For example, as shown in FIG.
After avoiding direct contact between the silicon substrate 3o1 and the aluminum/copper alloy layer 504 and preventing the reaction between silicon and aluminum, it is used as the main wiring, which has a higher electromigration withstand voltage than the conventional aluminum/silicon alloy. Hard aluminum/copper alloy 304 to 700
On top of that, a second titanium nitride Ji3os is formed as a cap metal to prevent so-called hillocks, where aluminum crystals locally thicken (grow) in the aluminum-copper alloy 304, and to - It has become essential to prevent the reflection of strong light on the surface of the copper alloy layer 304. At this time, in order to improve the precision of dimensional control, etching is performed by dry etching, and moreover, it is necessary to perform etching under a single condition. Five layers were etched anisotropically at the same time, and their shapes were vertical.
［発明が解決しようとする課題］
しかしながら、前述の従来技術では、ドライエツチング
により異方的にエツチングしているために、その形状は
垂直になっており、後工程の層間絶縁膜（酸化珪素膜３
０６）及び第２の配線（第２のアルミニウム・銅合金層
６０７）を形成する場合などにおいて、被覆性が劣化し
、配線層間の絶縁耐圧が低下したり、第２の配線が短絡
したり、断線することがあり、歩留シ及び信頼性が低下
する場合があった。[Problems to be Solved by the Invention] However, in the above-mentioned conventional technology, since etching is performed anisotropically by dry etching, the shape is vertical, and the interlayer insulating film (silicon oxide film) 3
06) and when forming the second wiring (second aluminum/copper alloy layer 607), the coverage may deteriorate, the dielectric strength between the wiring layers may decrease, the second wiring may be short-circuited, Wires may break, resulting in lower yield and reliability.
本発明は、このような課題を解決するもので、その目的
とするところは、後工程の層間絶縁膜やさらにその上層
の配線層の被覆性を向上させ、絶縁耐圧の劣化や上層の
配線の短絡や断線を防止することのできるような形状を
有する２層以上の導電膜よりなる構造の配線を提供する
ところにある［課題な解決するための手段］
本発明は、少なくとも２層以上の導電膜より構成される
積層構造を有する配線の形状において、最上層の導電膜
の線幅が、その下層の導電膜の線幅よりも小さいことを
特徴とする。The present invention is intended to solve these problems, and its purpose is to improve the coverage of the interlayer insulating film in the subsequent process and the wiring layer above it, thereby preventing deterioration of dielectric strength voltage and the wiring layer in the upper layer. [Means for Solving Problems] The present invention provides a wiring structure consisting of two or more layers of conductive films having a shape that can prevent short circuits and disconnections. In the shape of a wiring having a laminated structure composed of films, the line width of the uppermost conductive film is smaller than the line width of the lower conductive film.
［実施例］
第１図は、本発明の半導体装置の一実施例を示す主要断
面図であり、以下、第１図に基づき詳細に説明していく
。[Embodiment] FIG. 1 is a main cross-sectional view showing an embodiment of a semiconductor device of the present invention, and a detailed explanation will be given below based on FIG. 1.
第１の配線はバリアメタルの窒化チタン１０５、主配線
材のアルミニウム・銅合金１０４．キャップメタルの窒
化チタン１０５０５層より構成されており、最上層の窒
化チタン１０５の線幅はその下のアルミニウム・銅合金
１０４や窒化チタン１０３０線幅よりも小さくなってお
り、この様な形状になっていることにより、層間絶縁膜
１０６や第２の配線１０７の被覆性は良（なり、層間絶
縁膜の絶縁耐圧の劣化もないし、第２の配線の断線や短
絡する事もない。The first wiring is titanium nitride 105 as a barrier metal, and aluminum/copper alloy 104 as the main wiring material. It is composed of a layer of titanium nitride 10505 as a cap metal, and the line width of the top layer titanium nitride 105 is smaller than the line width of the aluminum-copper alloy 104 and titanium nitride 1030 below, resulting in this shape. As a result, the coverage of the interlayer insulating film 106 and the second wiring 107 is good (there is no deterioration in the dielectric strength of the interlayer insulating film, and there is no disconnection or short circuit of the second wiring).
さらに、本発明の実施例における工程断面図を第２図（
α）〜Ｃ６）に示し、以下工程順に詳細に説明していく
。Furthermore, FIG. 2 (
The steps are shown in α) to C6), and will be explained in detail in the order of the steps below.
まず最初に、第２図（ｃＬ）に示したように、半導体基
板２０１上方の酸化珪素膜２０２上に第１の窒化チタン
膜２０５を１ｏｏｏＸ、アルミニウム・銅合金膜２０４
を７０００Ｘ、第２の窒化チタン膜２０５を１ｏｏｏｉ
、連続的に形成する。First, as shown in FIG. 2(cL), a first titanium nitride film 205 is deposited at 1oooX on a silicon oxide film 202 above a semiconductor substrate 201, and an aluminum/copper alloy film 204 is deposited.
7000X, second titanium nitride film 205 at 1oooi
, forming continuously.
次に、第２図（ｂ）のように、配線となるように設計さ
れた部分に７オトレジスト２０６によりパターンを形成
する。Next, as shown in FIG. 2(b), a pattern is formed using a 7-photoresist 206 in a portion designed to become a wiring.
次に、第２図（Ｃ）のように、フォトレジスト２０６を
マスクとして第２の窒化チタン膜２０５を等方的にエツ
チングする。このとき、エツチングはドライエツチング
によって行なっており、その条件は、ＯＦ、＝９０ｓｃ
ｃｍ、０２ ＝１０ｓｃｃｍ 、１５Ｐａ、２００Ｗで
、この条件下では、窒化チタンは容易に等方的にエツチ
ングされ、エツチング時間を過剰にすることにより、第
２の窒化チタン２０５の線幅を７ナトレジスト２０６０
線幅よりも小さ（することができる。また、このエツチ
ング条件下ではアルミニウム・銅合金は全くエツチング
されない。Next, as shown in FIG. 2C, the second titanium nitride film 205 is isotropically etched using the photoresist 206 as a mask. At this time, the etching was performed by dry etching, and the conditions were: OF, = 90sc
cm, 02 = 10 sccm, 15 Pa, 200 W. Under these conditions, titanium nitride is easily etched isotropically, and by excessive etching time, the line width of the second titanium nitride 205 is reduced to 7.
(can be smaller than the line width. Also, under these etching conditions, the aluminum-copper alloy is not etched at all.
引続き、第２図（ｔＬ）のように、アルミニウム・銅合
金膜２０４、及び第１の窒化チタン膜２０５を連続的に
エツチングする。このときのエツチング条件は、反応ガ
スが、ＢＯＩ３＝１００ｃｃ、Ｃ１，＝５０ｃｃ、０２
＝５ｃｃ、圧力が６Ｐａ、ＲＩＰ電力が８００Ｗである
。Subsequently, as shown in FIG. 2 (tL), the aluminum-copper alloy film 204 and the first titanium nitride film 205 are continuously etched. The etching conditions at this time are that the reaction gas is BOI3=100cc, C1,=50cc, 02
=5cc, pressure is 6Pa, and RIP power is 800W.
最後に、第２図（ｅ）のように、フォトレジスト２０６
を除去し、配線が形成される。Finally, as shown in FIG. 2(e), the photoresist 206
is removed and wiring is formed.
なお本実施例においては、３層の導電膜より成る配線の
構造について示しているが、２層構造でも、４層以上の
構造でも同様の効果が期待できる［発明の効果コ
以上述べたように、本発明によれば、２層以上の導電膜
より成る多層構造の配線において、最上層の導電膜の線
幅がその下の導電膜の線幅よりも小さ（することにより
、後工程において形成される眉間絶縁膜や配線層の被覆
性を改善し、眉間絶縁膜の絶縁耐圧を向上させるととも
に、その上に形成される配線の断線や短絡を防止するこ
とができるという効果を有し、これにより高歩留りで高
信頼性の半導体装置を造ることができるようになった。Although this example shows a wiring structure consisting of three layers of conductive films, the same effect can be expected with a two-layer structure or a structure with four or more layers. According to the present invention, in a wiring having a multilayer structure consisting of two or more layers of conductive films, the line width of the uppermost conductive film is smaller than the line width of the conductive film below it (by doing so, it is possible to form the conductive film in a later process). It has the effect of improving the coverage of the glabella insulating film and wiring layer, increasing the dielectric strength of the glabella insulating film, and preventing disconnection and short circuits of the wiring formed thereon. This has made it possible to manufacture high-yield, highly reliable semiconductor devices.
第１図は、本発明の半導体装置の一実施例を示す主要断
面図。
第２図（α）〜（ｅ）は、本発明の半導体装置の製造工
程を示す断面図。
第３図は、従来の半導体装置を示す主要断面図１０１．
２０１．５０１・・・・・・シリコン基板１０２．２０
２．！５０２・・・・・・第１の酸化珪素膜１０３．２
０３，５０３・・・・・・第１の窒化チタン層
１０４．２０４，５０４・・・・・・第１のアルミニウ
ム・銅合金層
５．３０５・・・・・・第２の窒化チタン膜層
６・・・・・・・・・・・・・・・・・・第２の酸化珪
素膜（層間絶縁膜）
７・・・・・・・・・・・・・・・・・・第２のアルミ
ニウム・銅合金
・・・・・・・・・・・・・・・・・・フォトレジスト
以上FIG. 1 is a main sectional view showing an embodiment of a semiconductor device of the present invention. FIGS. 2(α) to 2(e) are cross-sectional views showing the manufacturing process of the semiconductor device of the present invention. FIG. 3 is a main cross-sectional view 101. showing a conventional semiconductor device.
201.501...Silicon substrate 102.20
2. ! 502...First silicon oxide film 103.2
03,503...First titanium nitride layer 104.204,504...First aluminum/copper alloy layer 5.305...Second titanium nitride film layer 6・・・・・・・・・・・・・・・・・・Second silicon oxide film (interlayer insulating film) 7・・・・・・・・・・・・・・・・・・2 Aluminum/copper alloy・・・・・・・・・・・・・・・More than photoresist
Claims (1)
有する半導体装置において、最上層の導電膜の線幅が、
その下層の導電膜の線幅よりも小さいことを特徴とする
半導体装置。In a semiconductor device having a stacked structure composed of at least two or more conductive films, the line width of the uppermost conductive film is
A semiconductor device characterized in that the line width is smaller than that of an underlying conductive film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20699488A JPH0254951A (en) | 1988-08-19 | 1988-08-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20699488A JPH0254951A (en) | 1988-08-19 | 1988-08-19 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0254951A true JPH0254951A (en) | 1990-02-23 |
Family
ID=16532426
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20699488A Pending JPH0254951A (en) | 1988-08-19 | 1988-08-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0254951A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0587695U (en) * | 1992-04-24 | 1993-11-26 | 眞幸 小川 | Signal device |
| US5363003A (en) * | 1991-06-06 | 1994-11-08 | Nippon Densan Corporation | Motor and circuitry for protecting same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61242039A (en) * | 1985-04-19 | 1986-10-28 | Nec Corp | Semiconductor device |
| JPS6242434A (en) * | 1985-08-19 | 1987-02-24 | Nec Corp | Manufacture of semiconductor device |
| JPS62104141A (en) * | 1985-10-31 | 1987-05-14 | New Japan Radio Co Ltd | Semiconductor device |
-
1988
- 1988-08-19 JP JP20699488A patent/JPH0254951A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61242039A (en) * | 1985-04-19 | 1986-10-28 | Nec Corp | Semiconductor device |
| JPS6242434A (en) * | 1985-08-19 | 1987-02-24 | Nec Corp | Manufacture of semiconductor device |
| JPS62104141A (en) * | 1985-10-31 | 1987-05-14 | New Japan Radio Co Ltd | Semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5363003A (en) * | 1991-06-06 | 1994-11-08 | Nippon Densan Corporation | Motor and circuitry for protecting same |
| JPH0587695U (en) * | 1992-04-24 | 1993-11-26 | 眞幸 小川 | Signal device |
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