JPH025439A - Semiconductor substrate - Google Patents
Semiconductor substrateInfo
- Publication number
- JPH025439A JPH025439A JP15553988A JP15553988A JPH025439A JP H025439 A JPH025439 A JP H025439A JP 15553988 A JP15553988 A JP 15553988A JP 15553988 A JP15553988 A JP 15553988A JP H025439 A JPH025439 A JP H025439A
- Authority
- JP
- Japan
- Prior art keywords
- inas
- layer
- type
- xas
- gaas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 19
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 229910000673 Indium arsenide Inorganic materials 0.000 claims abstract description 44
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 claims abstract description 42
- 239000012535 impurity Substances 0.000 claims abstract description 15
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 19
- 230000005669 field effect Effects 0.000 abstract description 15
- 238000000034 method Methods 0.000 abstract description 13
- 230000005533 two-dimensional electron gas Effects 0.000 abstract description 10
- 239000013078 crystal Substances 0.000 description 8
- 230000004907 flux Effects 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000000654 additive Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 229910005542 GaSb Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 125000005842 heteroatom Chemical group 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- UHXUZOCRWCRNSJ-QPJJXVBHSA-N methomyl Chemical compound CNC(=O)O\N=C(/C)SC UHXUZOCRWCRNSJ-QPJJXVBHSA-N 0.000 description 1
- 239000006251 one-dimensional electron gas Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
- H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
- H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、ＩｎＡｓを動作層として用いる二次元電子ガ
ス電界効果トランジスタ用基板の構造に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to the structure of a substrate for a two-dimensional electron gas field effect transistor using InAs as an active layer.
（従来の技術）
ＩｎＡｓは電子の移動度が大きく、超高速デバイス用材
料として注目されている。現在までのところ、ＩｎＡｓ
を動作層に用いたデバイスの報告は少な（、Ａｌ５ｋ１
０．９２Ａ５０．０８／ＩｎＡＳ／ＧａＳｂ構造のホッ
ト エレクトロン トランジスタ（アプライド フィシ
、クス レターズ（Ａｐｐｌ、 Ｐｈｙｓ、 Ｌｅｔｔ
、 ５１（１９８７）９８４））等が数例報告されるに
とどまっている。(Prior Art) InAs has high electron mobility and is attracting attention as a material for ultrahigh-speed devices. To date, InAs
There are few reports of devices using Al5k1 as the operating layer (Al5k1
0.92A50.08/InAS/GaSb structure hot electron transistor (Appl, Phys, Lett
, 51 (1987) 984)) have been reported.
方、表面ポテンシャルを制御して動作する電界効果トラ
ンジスタへの応用は、伝導帯付近に存在する高密度の界
面準位の為、実用化が阻まれている。On the other hand, practical application to field-effect transistors that operate by controlling the surface potential is hampered by the high density of interface states that exist near the conduction band.
（発明が解決しようとする問題）
ｌｎＡｓの表面は、伝導帯付近に存在する高密度の表面
準位の為、電子が溜まりｎ形を示すことが一般に知られ
ている。加えて、その高密度の表面準位の為、ＡＵ等の
金属層を１ｎＡｓ表面に形成した場合はショットキー接
合とは成らず、オーミックな接合となる。従って、Ｇａ
Ａｓの場合と異なり、１ｎＡｓのショットキー接合型電
界効果トランジスタ、いわゆるＭＥＳＦＥＴの実現性は
ない。その他の構造の電界効果トランジスタの動作層に
ＩｎＡｓを用いる場合でも、その準位密度を下げること
は重要である。・メタル／絶縁体／半導体のいわゆるＭ
ＩＳ電界効果トランジスタ、又はメタル／電子供給層／
動作層のいわゆる二次元電子ガス電界効果トランジスタ
を例にとれば、界面準位密度を下げる方法として、それ
ぞれ絶縁体、又は電子供給層用材料として１ｎＡｓと格
子整合する材料を選ぶことが挙げられる。すなわち、例
えばエピタキンヤル成長によりヘテロ界面を形成するこ
とにより、界面において未結合の元素を無くすことであ
る。しかしながら、１ｎＡｓと格子整合するワイド バ
ンド ギャップ材料として、一般に良く使われ、しかも
その性質が良く知られている材料は皆無である。強いて
挙げるならばＡｌＧａＡｓＳｂ系が挙げられるが、蒸気
圧の高いＡｓとｓｂの制御という、非常に高度な結晶成
長技術が必要となる。(Problem to be Solved by the Invention) It is generally known that the surface of lnAs exhibits n-type behavior due to the high density of surface states existing near the conduction band, where electrons accumulate. In addition, due to its high density of surface states, when a metal layer such as AU is formed on the 1nAs surface, a Schottky junction is not formed, but an ohmic junction is formed. Therefore, Ga
Unlike the case of As, there is no possibility of realizing a 1 nAs Schottky junction field effect transistor, so-called MESFET. Even when InAs is used for the active layer of field effect transistors having other structures, it is important to lower the level density.・So-called M for metals/insulators/semiconductors
IS field effect transistor or metal/electron supply layer/
Taking a so-called two-dimensional electron gas field effect transistor as an active layer as an example, one way to lower the interface state density is to select a material that is lattice-matched to 1nAs as an insulator or an electron supply layer material, respectively. That is, by forming a hetero interface by, for example, epitaaxial growth, there are no unbonded elements at the interface. However, there are no materials that are commonly used as wide band gap materials that lattice match with 1nAs, and whose properties are well known. The AlGaAsSb system is a strong choice, but it requires very advanced crystal growth technology to control As and sb, which have high vapor pressures.
本発明の目的は、ＩｎＡｓを動作層として用いる二次元
電子ガス電界効果トランジスタ作成において、Ａ ｌＧ
ａＡｓ５ｂ／ ＩｎＡｓ等の高度な成長技術を必要とせ
す、容易にＩｎＡｓを動作層として用いる二次元電子ガ
ス電界効果トランジスタが作成できる半導体結晶ウェハ
構造を提供することである。The purpose of the present invention is to create a two-dimensional electron gas field effect transistor using InAs as an active layer, using AlG
It is an object of the present invention to provide a semiconductor crystal wafer structure in which a two-dimensional electron gas field effect transistor using InAs as an active layer can be easily fabricated, which requires advanced growth techniques such as aAs5b/InAs.
（問題点を解決するための手段）
本発明の半導体基板の構造は、ＩｎＡｓ基板上に高純度
のＩｎＡｓ層、その上にｐ形不純物を添加したＩｎＡｓ
層、更にその上にＡｌの組成比のＸが０．２２以下のｎ
形ＡｌｘＧａ１−ｘＡＳ層を配したことを特徴とする。(Means for Solving the Problems) The structure of the semiconductor substrate of the present invention includes a high-purity InAs layer on an InAs substrate, and an InAs layer doped with p-type impurities on the InAs substrate.
layer, and further on the layer n, the Al composition ratio X is 0.22 or less.
It is characterized by having an AlxGa1-xAS layer.
本発明の半導体基板の構造は、１ｎＡｓ基板上に高純度
のＩｎＡｓ層、その上にＩｎＡｓやＡｌＧａＡｓに対し
てｐ形不純物となる元素を原子層状に添加した層、更に
その上にＡｌの組成比のＸが０．２２以下のｎ形Ａｌｘ
Ｇａ＋−ｘＡｓ層を配したことを特徴とする。The structure of the semiconductor substrate of the present invention includes a high-purity InAs layer on a 1nAs substrate, a layer doped with an atomic layer of an element that becomes a p-type impurity for InAs or AlGaAs, and an Al composition ratio on top of the layer. n-type Alx with X of 0.22 or less
It is characterized by a Ga+-xAs layer.
（作用）
ＩｎＡｓとＧａＡｓでは格子定数が約６．７％異なって
いる為、ＩｎＡｓ結晶上にＧａＡｓを成長した場合、Ｉ
ｎＡｓ上のＧａＡｓ層にはストレスを緩和する為の転移
や点欠陥等がＩｎＡｓ／ＧａＡｓの界面付近に大量発生
する。(Function) Since the lattice constants of InAs and GaAs differ by approximately 6.7%, when GaAs is grown on an InAs crystal, the I
In the GaAs layer on nAs, a large number of dislocations, point defects, etc. are generated near the InAs/GaAs interface to relieve stress.
従って、ＩｎＡｓ／ＧａＡｓのへテロ界面は、界面準位
密度が高くなる。ＩｎＡｓの界面準位は、伝導帯付近が
最も高濃度である為、１ｎＡｓの界面ポテンシャルは、
はぼ伝導帯に固定され、界面には電子が溜まる。このま
まこのウェハを二次元電子ガス電界効果トランジスタ用
のウェハとして用いたならば、作成したトランジスタは
、いつもＯＮ状態であり、よほど大きなバイアスを印加
しない限り伝導度の変調ができないことは明らかである
。しかし、界面ポテンシャルをなんらかの方法で、でき
ればフラット バンド状態付近まで持ち上げれば、バイ
アスに対する伝導度の変調度としては大きくなる。その
一方法として、ＩｎＡｓ／ＧａＡｓヘテロ界面に、ｐ−
１ｎＡｓ薄膜層を設け、フェルミ レベルを押し上げる
ことが挙げられる。熱平衡時の界面ポテンシャルは、ｐ
−１ｎＡｓ薄膜層の不純物濃度により制御することがで
きる。現在では、分子線成長法等により極薄膜の制御さ
れた成長も可能であり、ｐ−１ｎＡｓ薄膜層の代わりに
、ＩｎＡｓやＧａＡｓに対してｐ形不純物となる元素、
例えばＢｅ等を原子層状にＩｎＡｓ／ＧａＡｓヘテロ界
面に挿入することも容易である。この場合は、電子が走
るＩｎＡｓ層内に不純物が無い為、電子の散乱が少なく
、電子の高移動度化、従ってデバイス性能の向上が期待
できる。Therefore, the InAs/GaAs heterointerface has a high interface state density. Since the interface state of InAs has the highest concentration near the conduction band, the interface potential of 1nAs is
It is fixed in the conduction band, and electrons accumulate at the interface. If this wafer is used as it is as a wafer for a two-dimensional electron gas field effect transistor, it is clear that the fabricated transistor will always be in an ON state and that conductivity cannot be modulated unless a very large bias is applied. However, if the interfacial potential is somehow raised to near the flat band state, the degree of modulation of conductivity with respect to bias will increase. As one method, p-
One example is to increase the Fermi level by providing a 1nAs thin film layer. The interfacial potential at thermal equilibrium is p
It can be controlled by the impurity concentration of the -1nAs thin film layer. Currently, controlled growth of extremely thin films is possible using molecular beam growth, etc., and instead of p-1nAs thin film layers, elements that act as p-type impurities for InAs and GaAs,
For example, it is easy to insert Be or the like into an atomic layer at the InAs/GaAs hetero interface. In this case, since there are no impurities in the InAs layer through which electrons travel, there is less scattering of electrons, and higher electron mobility and therefore improved device performance can be expected.
この場合は、不純物層の面濃度で熱平衡時の界面ポテン
シャルが制御できる。界面ポテンシャルの制御を行うに
はＢｅ層の厚さが１原子層以下であることが望ましい。In this case, the interfacial potential at thermal equilibrium can be controlled by the surface concentration of the impurity layer. In order to control the interfacial potential, it is desirable that the thickness of the Be layer is one atomic layer or less.
更に、ＧａＡｓの代わりにＡｌの組成比のＸが０．２２
以下のｎ形Ａ ｌ ｘＧａ 、−、Ａｓを用いることに
より、ｎ−ＧａＡｓを用いた場合より、より高ｌ農度の
電子を１ｎＡｓ動作層に供給できるようになる。これは
Ｎ Ａ１−ｘＡｓがＧａＡｓより伝導帯の状態密度が大
きいことによる。しかも、Ａｌの組成比のＸを０．２２
以下とすることで、ｎ−Ａｌ、Ｇａ＋−ｘＡｓ中に存在
するＤＸセンタと呼ばれる高１３度の深い準位の悪影響
を防ぐことができる（フィジカル レビｓ −Ｂ（Ｐｈ
ｙｓ、 Ｒｅｖ、 ８１９ （１９７９）１０１５）
） 、 さらに、ＡｌＧａＡｓはＧａＡｓよりバンドギ
ャップが大きいことにより絶縁性が高まり、ゲートのり
−り電流が小さくなることが期待できる。ところで、分
子線成長法により本発明の半導体結晶を作成する場合を
想定すると、蒸発用セルとしては、Ｉｎｔ Ｇａ、Ａｌ
、Ａｓ１８１％ Ｂｅの６本が必要になるが、いずれも
通常のｍ−■族化合物半導体の分子線成長では良く知ら
れたものであり制御性の高い成長が可能となる。Furthermore, the composition ratio of Al instead of GaAs is 0.22.
By using the following n-type A l xGa , -, As, it becomes possible to supply electrons with a higher yield to the 1nAs active layer than when using n-GaAs. This is because N A1-xAs has a higher density of states in the conduction band than GaAs. Moreover, the Al composition ratio X is 0.22
By setting the following, it is possible to prevent the adverse effects of the deep level of high 13 degrees called DX center that exists in n-Al, Ga+-xAs (Physical Levis -B (Ph
ys, Rev. 819 (1979) 1015)
) Furthermore, since AlGaAs has a larger band gap than GaAs, it is expected that the insulation properties will be improved and the gate current will be reduced. By the way, assuming that the semiconductor crystal of the present invention is created by molecular beam growth method, Int Ga, Al
, As181% Be are required, and all of them are well known in the molecular beam growth of ordinary m-■ group compound semiconductors, and highly controllable growth is possible.
（実施例）
実施例１
第１図は、特許請求の範囲１で示された構造を持つ半導
体基板の断面図であり、これを用いて二次元電子ガス電
界効果トラジスタを作成した。(Example) Example 1 FIG. 1 is a cross-sectional view of a semiconductor substrate having the structure shown in Claim 1, and a two-dimensional electron gas field effect transistor was created using this.
ウェハの構造は、１１ １）−１ｎＡｓ基板（厚さ二〜
４００μｍ１ｐ＝１〜２Ｘ１０１８ＣＩ１１−３）、１
２ｐ−１ｎＡｓバツフア層（厚さ：５００人、ｐ＝１×
１０１７ｃｍ−３）、１３ 高純度ＩｎＡｓ層（厚さ：
１００ＯＡ、！添加） 、１４ ｐ−ＩｎＡｓ層（
厚さ＝５０人、１） ” Ｉ Ｘ １０１７ｃｍ−３）
、１５ ｎ−ＧａＡｓ層（厚さ：５００Ａ１ｎ＝ＩＸ
１０１８ｃｍ−３）である。なお、ｐ−１ｎＡｓ層１４
の厚さは５０Ａである必要性はないが、表面ポテンシャ
ル制御と二次元電子伝導のかねあいから考えて２００八
以下が望ましい。このウェハは、分子線成長法により作
成した。成長条件は、基板温度＝４８０°Ｃにて、Ｇａ
フラックス： ４．２Ｘ １０−’Ｔｏｒｒｓ Ｉ ｎ
フラックス：６．１ｘ ｌ Ｏ−’Ｔｏｒｒ１Ａ ｓフ
ラックス：７．６Ｘ１０−’Ｔｏｒｒである。なお、ｐ
形不純物としてはＢｅをｎ形不純物としてはＳｉを用い
た。ところで、この条件で作成した無添加の高純度Ｉｎ
Ａｓ層１３は、通常ｎ形を示し、電子ｌ１度は、１×１
０１１１１ＣＩＩｌ−ａ程度である。これらのデータを
基に計算した熱平均でのバンド図を第２図に示す。ここ
では、界面準位として１ｎＡｓの伝導帯に２×１０口Ｃ
ｌ１１−２を見積もっている。ＧａＡｓ層 １ｎＡｓの
界面に２１ 二次元電子ガスが生じることを計算で確認
できた。実際のデバイスは、ゲート長：２μｍで作成し
た。プロセスは、燐酸系エッチャントを用いたＧａＡｓ
系デバイス用プロセスをＩｎＡｓにおいても条件出しを
行なった上で用いた。ゲート電極にはＡｌを、ソース電
極とドレイン電極にはＡｕＧｅ／Ａｕを蒸着で形成し、
熱処理せずに用いた。トランジスタ特性としては、７７
Ｋにおいて２００ｍ５が得られた。The structure of the wafer is 111)-1nAs substrate (thickness 2~
400μm1p=1~2X1018CI11-3), 1
2p-1nAs buffer layer (thickness: 500 people, p=1×
1017 cm-3), 13 high-purity InAs layer (thickness:
100OA! addition), 14 p-InAs layer (
Thickness = 50 people, 1) ” I x 1017cm-3)
, 15 n-GaAs layer (thickness: 500A1n=IX
1018 cm-3). Note that the p-1nAs layer 14
It is not necessary that the thickness be 50A, but it is desirable to have a thickness of 200A or less in consideration of surface potential control and two-dimensional electron conduction. This wafer was created by molecular beam growth. The growth conditions were: substrate temperature = 480°C, Ga
Flux: 4.2X 10-' Torrs In
Flux: 6.1xl O-'Torr1A s flux: 7.6X10-'Torr. In addition, p
Be was used as the type impurity, and Si was used as the n-type impurity. By the way, additive-free high-purity In produced under these conditions
The As layer 13 normally exhibits n-type, and the electron l1 degree is 1×1
It is about 01111CIIl-a. Figure 2 shows a thermally averaged band diagram calculated based on these data. Here, the interface state is 2×10 C in the conduction band of 1 nAs.
We are estimating l11-2. It was confirmed by calculation that 21 two-dimensional electron gas was generated at the interface of the 1nAs GaAs layer. The actual device was created with a gate length of 2 μm. The process uses GaAs using a phosphoric acid etchant.
The same process for InAs based devices was used after adjusting the conditions. Al is formed on the gate electrode, and AuGe/Au is formed on the source and drain electrodes by vapor deposition.
It was used without heat treatment. The transistor characteristics are 77
200 m5 were obtained at K.
実施例２
実施例１で示したｎ−ＧａＡｓ層１５の代わりに、キャ
リア濃度３ Ｘ １０ ′８ｃｍ−３のｎ−Ａ ｌＧａ
Ａｓを５００Ａ形成させた。成長時のＡｌフラックスは
１．３×１０−７Ｔｏｒｒ、他の成長条件及びデバイス
の作成方法は全て実施例１と同様である。トランジスタ
特性は７７にで２５０ｍ５であった。Example 2 Instead of the n-GaAs layer 15 shown in Example 1, n-AlGa with a carrier concentration of 3 x 10'8 cm-3 was used.
500A of As was formed. The Al flux during growth was 1.3 x 10-7 Torr, and all other growth conditions and device fabrication methods were the same as in Example 1. The transistor characteristics were 77mm and 250m5.
実施例３
第３図は、特許請求の範囲２で示された構造を持つ半導
体基板の断面図であり、これを用いて一次元電子ガス電
界効果トランジスタを作成した。Example 3 FIG. 3 is a cross-sectional view of a semiconductor substrate having the structure shown in claim 2, and a one-dimensional electron gas field effect transistor was created using this.
ウェハの構造は、３１ ｐ−１ｎＡｓ基板（厚さ二〜
４００μｍｓ ｐ＝ １〜２Ｘ １０１８ｃｍ−’）
、３２ｐ−１ｎＡｓバツフア層（厚さ二５００人、ｐ＝
１×１０ ”ｃｍ−３） 、３３ 高純度ＩｎＡｓ層
（厚さ： １０００人、無添加）、３４ Ｂｅ原子層
（厚さ〜ｌ／ｌ０００原子層、５ Ｘ １０ ｌ２ｃｍ
−２） 、３５ ｏ−ＧａＡｓ層（厚さ： ５００Ａ
Ｎ ｎ：ｌＸ１０”ｃｍ−’）である。このウェハは、
分子線成長法により作成した。The structure of the wafer is a 31p-1nAs substrate (thickness 2~
400μms p=1~2X 1018cm-')
, 32p-1nAs buffer layer (thickness 2500, p=
1×10”cm-3), 33 high-purity InAs layers (thickness: 1000 layers, no additives), 34 Be atomic layers (thickness ~l/l000 atomic layers, 5 X 10 l2cm)
-2), 35 o-GaAs layer (thickness: 500A
N n:lX10"cm-'). This wafer is
It was created using the molecular beam growth method.
成長条件は、基板温度＝４８０°Ｃにて、Ｇａフラック
ス： ４．２Ｘ １０−’Ｔｏｒｒ、 Ｉ ｎ７ラノク
ス： ６ 、 Ｉ Ｘ １０１０−’Ｔｏｒｒ１Ａ
ｓフラックスニア、 ６ Ｘ １０−６Ｔｏｒｒである
。なお、ｐ 形不純物トしてはＢｅをｎ形不純物として
はＳｉを用いており、３４ Ｂｅ原子層成膜時には、
ＢｅとＡｓ同時に照射し、厚さ約１／１０００原子層の
Ｂｅ層を形成した。なお無添加の高純度ＩｎＡｓ層１３
は、通常ｎ形を示し、電子濃度は、Ｉ Ｘ １０ ”ｃ
ｍ−３程度である。実際のデバイスは、ゲート長：２μ
ｍで作成した。プロセスは、燐酸系エッチャントを用い
たＧａＡｓ系デバイス用プロセスをＩｎＡｓにおいても
条件出しを行なった上で用いた。ゲート電極にはＡｌを
、ソース電極とドレイン電極にはＡｕＧｅ／Ａｕを蒸着
で形成し、熱処理せずに用いた。トランジスタ特性とし
ては、７７Ｋにおいて３００ｍ５が得うれた。Ｂｅ原子
層の厚さは１原子層から１／１０００００原子層の範囲
であれば発明の効果か得られた。またＢｅ以外のｐ形不
純物例えばＺ ｎ Ｎ Ｃｄなどでも良い。成長方法は
分子線成長に限らず原子層工ピタキンヤル成長や角゛機
金属気相成長など他の成長方法で良い。The growth conditions were: substrate temperature = 480°C, Ga flux: 4.2X 10-'Torr, In7 Lanox: 6, IX 1010-'Torr1A
s flux nia, 6 x 10-6 Torr. Note that Be is used as the p-type impurity and Si is used as the n-type impurity, and when forming a 34 Be atomic layer,
Be and As were irradiated simultaneously to form a Be layer with a thickness of about 1/1000 atomic layer. Note that the high purity InAs layer 13 without additives
usually indicates n-type, and the electron concentration is I x 10 ”c
It is about m-3. The actual device has a gate length of 2μ.
Created with m. As for the process, a process for GaAs-based devices using a phosphoric acid-based etchant was used after adjusting the conditions for InAs as well. Al was formed for the gate electrode, and AuGe/Au was formed for the source and drain electrodes by vapor deposition, and these were used without heat treatment. As for the transistor characteristics, 300 m5 was obtained at 77K. The effects of the invention were obtained when the thickness of the Be atomic layer was in the range of 1 atomic layer to 1/100,000 atomic layer. Further, p-type impurities other than Be, such as Z n N Cd, etc. may also be used. The growth method is not limited to molecular beam growth, but may be other growth methods such as atomic layer deposition, crystalline metal vapor phase growth, etc.
（発明の効果）
以上のよ・うに本発明の１５導体結晶によれば、ＡｌＧ
ａＡｓＳｂ／ １ｎＡｓへと口成長等の高度な成長技術
を必ｄとせず、容易にＩｎＡｓを動作層として用いる二
次ＪＣ’；Ｔ！子ガス重ガス電界効果トランジスタでき
る。(Effect of the invention) As described above, according to the 15-conductor crystal of the present invention, AlG
A secondary JC';T! that easily uses InAs as the active layer without requiring advanced growth techniques such as growth to aAsSb/1nAs; A child gas heavy gas field effect transistor can be created.
第１図は、特許請求の範囲１で示された構造を持つ半導
体結晶ウェハの断面図、第２図は、第１の実施例で作成
した二次元電子ガス電界効果トランジスタ用結晶のバン
ド図、第３図は、特許請求の範囲２で示された構造を持
つ半導体結晶ウェハの断面図であろうFIG. 1 is a cross-sectional view of a semiconductor crystal wafer having the structure shown in claim 1, and FIG. 2 is a band diagram of a crystal for a two-dimensional electron gas field effect transistor produced in the first embodiment. FIG. 3 is a cross-sectional view of a semiconductor crystal wafer having the structure shown in claim 2.
Claims (2)
ｐ形不純物を添加したＩｎＡｓ層、更にその上にＡｌの
組成比のＸが０．２２以下のｎ形Ａｌ＿ｘＧａ＿１＿−
＿ｘＡｓ層を配したことを特徴とする半導体基板。(1) A high-purity InAs layer on an InAs substrate, an InAs layer doped with p-type impurities on top of that, and an n-type Al_xGa_1_- with an Al composition ratio X of 0.22 or less
A semiconductor substrate characterized by disposing a _xAs layer.
ＩｎＡｓやＡｌＧａＡｓに対してｐ形不純物となる元素
を原子層状に添加した層、更にその上にＡｌの組成比の
Ｘが０．２２以下のｎ形Ａｌ＿ｘＧａ＿１＿−＿ｘＡｓ
層を配したことを特徴とする半導体基板。(2) A high-purity InAs layer on an InAs substrate, on top of that a layer doped with an atomic layer of elements that serve as p-type impurities for InAs and AlGaAs, and on top of that a layer with an Al composition ratio of 0.22 The following n-type Al_xGa_1_-_xAs
A semiconductor substrate characterized by having layers arranged thereon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15553988A JPH025439A (en) | 1988-06-22 | 1988-06-22 | Semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15553988A JPH025439A (en) | 1988-06-22 | 1988-06-22 | Semiconductor substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH025439A true JPH025439A (en) | 1990-01-10 |
Family
ID=15608272
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15553988A Pending JPH025439A (en) | 1988-06-22 | 1988-06-22 | Semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH025439A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5430310A (en) * | 1991-03-28 | 1995-07-04 | Asahi Kasei Kogyo Kabushiki Kaisha | Field effect transistor |
| US6291842B1 (en) | 1998-03-12 | 2001-09-18 | Nec Corporation | Field effect transistor |
| JP2005277358A (en) * | 2004-03-26 | 2005-10-06 | Ngk Insulators Ltd | Semiconductor multilayer structure, transistor element, and method of manufacturing the same |
-
1988
- 1988-06-22 JP JP15553988A patent/JPH025439A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5430310A (en) * | 1991-03-28 | 1995-07-04 | Asahi Kasei Kogyo Kabushiki Kaisha | Field effect transistor |
| US6291842B1 (en) | 1998-03-12 | 2001-09-18 | Nec Corporation | Field effect transistor |
| JP2005277358A (en) * | 2004-03-26 | 2005-10-06 | Ngk Insulators Ltd | Semiconductor multilayer structure, transistor element, and method of manufacturing the same |
| JP4642366B2 (en) * | 2004-03-26 | 2011-03-02 | 日本碍子株式会社 | Semiconductor stacked structure, transistor element, and method of manufacturing transistor element |
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