JPH025313B2 - - Google Patents
Info
- Publication number
- JPH025313B2 JPH025313B2 JP56091479A JP9147981A JPH025313B2 JP H025313 B2 JPH025313 B2 JP H025313B2 JP 56091479 A JP56091479 A JP 56091479A JP 9147981 A JP9147981 A JP 9147981A JP H025313 B2 JPH025313 B2 JP H025313B2
- Authority
- JP
- Japan
- Prior art keywords
- plating
- current density
- thickness
- resist
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000007747 plating Methods 0.000 claims description 44
- 238000000034 method Methods 0.000 claims description 25
- 229910052751 metal Inorganic materials 0.000 claims description 24
- 239000002184 metal Substances 0.000 claims description 24
- 239000004020 conductor Substances 0.000 claims description 19
- 238000004519 manufacturing process Methods 0.000 claims description 13
- PEVJCYPAFCUXEZ-UHFFFAOYSA-J dicopper;phosphonato phosphate Chemical compound [Cu+2].[Cu+2].[O-]P([O-])(=O)OP([O-])([O-])=O PEVJCYPAFCUXEZ-UHFFFAOYSA-J 0.000 claims description 11
- 229910052782 aluminium Inorganic materials 0.000 claims description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 8
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 7
- 229910052725 zinc Inorganic materials 0.000 claims description 7
- 239000011701 zinc Substances 0.000 claims description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- 229910052718 tin Inorganic materials 0.000 claims description 5
- 239000000243 solution Substances 0.000 description 17
- 238000005530 etching Methods 0.000 description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 14
- 229910052802 copper Inorganic materials 0.000 description 13
- 239000010949 copper Substances 0.000 description 13
- 238000009713 electroplating Methods 0.000 description 9
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000001035 drying Methods 0.000 description 3
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 3
- 229910052753 mercury Inorganic materials 0.000 description 3
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000007864 aqueous solution Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000005011 phenolic resin Substances 0.000 description 2
- 229920001568 phenolic resin Polymers 0.000 description 2
- 238000005507 spraying Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 238000004804 winding Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 235000010724 Wisteria floribunda Nutrition 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007865 diluting Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000007646 gravure printing Methods 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
- 239000005028 tinplate Substances 0.000 description 1
Landscapes
- Manufacturing Of Printed Wiring (AREA)
Description
【発明の詳細な説明】
本発明は高密度、高信頼性の微細厚膜印刷回路
基板の改良された製造方法に関するものである。
微細厚膜印刷回路基板は、電流値が必要とされる
小型コイル、高密度コネクター、高密度配線など
の分野で要求されている。コイルの製造法として
は、通常巻き線方式が用いられているが、この方
法では小型のコイルを製造する事は困難であり、
かつ巻き線の状態にバラツキが生じる。また銅箔
をエツチングしたいわゆるプリントコイルは、サ
イドエツチングの為、フアインパターンは得られ
ず、たかだか２〜３本／mmのパターンしか得られ
ず、この方法も小型のコイルを製造する事はむつ
かしい。しかしながら、近年モーターの小型化に
ともない、フアインパターンを有するフアインコ
イルの開発が要望されている。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improved method for manufacturing high density, high reliability micro thick film printed circuit boards.
Fine thick-film printed circuit boards are required in fields such as small coils, high-density connectors, and high-density wiring where current values are required. The wire winding method is normally used to manufacture coils, but it is difficult to manufacture small coils using this method.
Moreover, variations occur in the state of the winding wire. Also, so-called printed coils made by etching copper foil do not produce fine patterns because of side etching, and only a pattern of 2 to 3 wires/mm can be obtained at most, making it difficult to manufacture small coils using this method. . However, as motors have become smaller in recent years, there has been a demand for the development of fine coils having fine patterns.
本発明者らはすでに特願昭56−166614号、特願
昭56−55100〜55102号にある様に金属薄板上にレ
ジストを回路部以外の所に設け、電解メツキによ
り回路部に導電体を形成した該金属薄板の全面又
は回路部以外の所を除去し印刷回路基板を得る微
細厚膜印刷回路基板の製造方法を提案した。 As described in Japanese Patent Application No. 56-166614 and Japanese Patent Application No. 56-55100 to 55102, the inventors have already provided a resist on a thin metal plate in areas other than the circuit area, and electrolytically plated the conductor in the circuit area. We have proposed a method for manufacturing a fine thick film printed circuit board in which a printed circuit board is obtained by removing the entire surface of the formed metal thin plate or a portion other than the circuit portion.
しかし、これら提案の方法において、電解メツ
キ条件、特に電流密度条件により形成される導電
体ラインの端に突起が生じることがある。 However, in these proposed methods, protrusions may occur at the ends of conductor lines formed under electrolytic plating conditions, particularly under current density conditions.
また、金属薄板と電解メツキ層との密着力も電
解メツキ条件の影響を大きく受ける。導電体ライ
ンの端の突起や、メツキ層の基板への密着力は、
量産プロセスにおいて微細厚膜印刷回路の信頼性
の低下や収率の低下を招き易い。 Furthermore, the adhesion between the metal thin plate and the electrolytically plated layer is also greatly influenced by the electrolytically plated conditions. The protrusion at the end of the conductor line and the adhesion of the plating layer to the substrate are
In the mass production process, the reliability and yield of fine thick film printed circuits tend to decrease.
本発明者らは鋭意研究を重ね、かかる欠点を克
服し、簡易かつ収率の高い量産プロセスを持つ信
頼性の高い微細厚膜印刷回路基板の製造方法を確
立し本発明をなすに至つた。 The inventors of the present invention have conducted extensive research, overcome these drawbacks, and established a highly reliable manufacturing method for fine thick-film printed circuit boards that has a simple and high-yield mass production process, thereby achieving the present invention.
即ち、本発明は、厚さ10μmを超え200μm以下
の亜鉛、アルミニウムまたは錫の金属薄板上にレ
ジストを回路部以外の所に設け、電流密度0.05〜
2A／ｄm2で膜厚0.3〜10μmまでピロリン酸銅メ
ツキをした後、所定の膜厚まで３〜20A／ｄm2の
電流密度でピロリン酸銅メツキして回路部に導電
体を形成し、その後、該金属薄板の全面又は回路
部以外の所を除去することを特徴とする線密度３
本／mm以上の配線パターンを有する微細厚膜印刷
回路基板の製造方法を提供するものである。 That is, in the present invention, a resist is provided on a thin metal plate of zinc, aluminum, or tin with a thickness of more than 10 μm and less than 200 μm in a place other than the circuit part, and a current density of 0.05 to 0.05 is applied.
After copper pyrophosphate plating is applied to a film thickness of 0.3 to 10 μm at 2 A/dm 2 , copper pyrophosphate plating is performed at a current density of 3 to 20 A/dm 2 to a specified film thickness to form a conductor in the circuit area, and then , linear density 3, characterized in that the entire surface of the thin metal plate or a portion other than the circuit portion is removed.
The present invention provides a method for manufacturing a fine thick-film printed circuit board having a wiring pattern of more than 2 lines/mm.
本発明の方法によれば、回路部への電解メツキ
工程の初期において低電流密度によつて形成され
たメツキ層を介して導電体ラインを金属薄板上に
形成することによつて初めて導電体ラインの端の
突起が防止され、メツキ層の金属薄板への密着性
が改善された。その理由は良くわからないが、た
とえばメツキ初期の核発生とその成長が電流密度
に関係しているためであるとか、又はメツキ層の
残留応力が緩和されるためであるとかが考えられ
る。 According to the method of the present invention, a conductor line is formed on a thin metal plate through a plating layer formed with a low current density in the early stage of the electrolytic plating process for a circuit part. Protrusions at the edges of the plate were prevented, and the adhesion of the plating layer to the thin metal plate was improved. The reason for this is not well understood, but it is thought that, for example, nucleation and growth at the initial stage of plating are related to current density, or that residual stress in the plating layer is relaxed.
しかしながら、導電体ラインの端に突起が生じ
ないため導体ラインの加工精度があがり信頼性、
再現性が向上した。また密着力が向上したため工
程間の取り扱いにおいて生じるラインの乱れがな
くなり量産プロセスにおける収率も向上した。し
かも、他の組成の異なる浴も不要で工程数も増加
しない。 However, since there are no protrusions at the ends of the conductor line, the processing accuracy of the conductor line is improved and the reliability is improved.
Improved reproducibility. In addition, the improved adhesion eliminates line disturbances that occur during handling between processes, and improves yield in the mass production process. Furthermore, there is no need for other baths with different compositions, and the number of steps does not increase.
以上のことから本発明の製造方法は工業的に優
れたものである。 From the above, the manufacturing method of the present invention is industrially superior.
全工程を簡単に述べると、金属薄板上に回路部
以外の部分にレジストを形成し、次に回路部にピ
リン酸銅メツキにより導電体を形成し、次にレジ
ストを剥離後金属薄板の回路部以外をエツチング
除去するか、又は裏側から金属薄板を剥離又はエ
ツチングで全面除去するか、又は裏面に表の回路
部に対する所にレジストを形成した後、回路部以
外の金属薄板をエツチング除去して、印刷回路基
板を得る。 To briefly describe the entire process, a resist is formed on the parts other than the circuit part on a thin metal plate, then a conductor is formed on the circuit part by plating copper pyrate, and then after the resist is peeled off, the circuit part of the thin metal plate is removed. Either the thin metal plate is completely removed by peeling or etching from the back side, or a resist is formed on the back side in the area corresponding to the front circuit area, and then the thin metal plate other than the circuit area is removed by etching. Obtain a printed circuit board.
本発明に使用される金属薄板は、アルミニウ
ム、亜鉛またはスズ等が使用される。また、膜厚
としては、10〜200μmが好ましい範囲である。
10μm以下の膜厚では、取り扱い難く、かつメツ
キ膜厚に分布が生じ易い。また200μm以上の膜厚
では、エツチング除去に時間がかかり生産が低下
し、かつ金属薄板の回路部以外の所をエツチング
除去する場合はサイドエツチによりパターンに乱
れが生じる。 The thin metal plate used in the present invention is made of aluminum, zinc, tin, or the like. Moreover, the preferable range of film thickness is 10 to 200 μm.
If the film thickness is 10 μm or less, it is difficult to handle and the plating film thickness tends to be uneven. Further, if the film thickness is 200 μm or more, it takes time to remove the etching by etching, which reduces production, and when etching areas other than the circuit portion of the thin metal plate, the pattern is disturbed due to side etching.
本発明において行われる回路部以外の部分にレ
ジストを形成する方法としては、スクリーン印刷
或いはグラビア印刷などで形成しても良いが、フ
アインパターンが得易いフオトレジストを用い露
光、現像プロセスを経て得る事が出来る。フオト
レジストとしては、イーストマンコダツク社の
KPR、KOR、KPL、KTFR、東京応化社の
TPR、OMR81、富士薬品工業のFSRなどのネガ
型、およびイーストマンコダツク社のKADR、
シプレー社のAZ−1350などのポジ型などがある
が、耐メツキ性に優れたものが好ましく、特にネ
ガ型が好ましく使用される。また、ドライフイル
ムレジストも使用可能である。膜厚は厚い方がメ
ツキの太り防止として役立つが、余り厚過ぎると
フアインパターンが得られなくなつてしまい、
0.1〜50μm、特に１〜10μmが好ましい。0.1μm以
下ではピンホールが生じ易い。 In the present invention, the resist may be formed on parts other than the circuit part by screen printing or gravure printing, but it can be formed by using a photoresist that allows fine patterns to be easily obtained through an exposure and development process. I can do things. As a photoresist, Eastman Kodak's
KPR, KOR, KPL, KTFR, Tokyo Ohkasha
Negative types such as TPR, OMR81, Fuji Pharmaceutical's FSR, and Eastman Kodatsu's KADR,
There are positive types such as AZ-1350 manufactured by Shipley Co., Ltd., but those with excellent plating resistance are preferred, and negative types are particularly preferably used. A dry film resist can also be used. The thicker the film, the more effective it will be in preventing the plating from becoming thick, but if it is too thick, it will become impossible to obtain a fine pattern.
0.1-50 μm, particularly 1-10 μm is preferred. If the thickness is 0.1 μm or less, pinholes are likely to occur.
本発明において電解メツキを行なう方法として
は、線密度３本／mm以上のパターンを厚付けする
ために、ピロリン酸銅メツキ液を用い、初めに電
流密度0.05〜2A／ｄm2、好ましくは0.1〜1.5A／
ｄm2で膜厚0.3〜10μm、好ましくは0.5〜5μmに電
解メツキを行う。電流密度は2A／ｄm2以上では
メツキ層の金属薄板への十分な密着力が得られ
ず、また、0.05A／ｄm2以下ではメツキ時間がか
かりすぎ生産性が低下する。膜厚も0.3μm以下で
はやはり十分な密着性が得られず、10μm以上で
は時間がかかり生産性が低下する。 In the present invention, electrolytic plating is carried out using a copper pyrophosphate plating solution at a current density of 0.05 to 2 A/dm 2 , preferably 0.1 to 1.5A/
Electrolytic plating is performed at dm 2 to a film thickness of 0.3 to 10 μm, preferably 0.5 to 5 μm. If the current density is 2 A/dm 2 or higher, sufficient adhesion of the plating layer to the thin metal plate cannot be obtained, and if the current density is 0.05 A/dm 2 or lower, the plating time will be too long and productivity will decrease. If the film thickness is less than 0.3 μm, sufficient adhesion cannot be obtained, and if it is more than 10 μm, it will take time and productivity will decrease.
つぎに、所定の膜厚までさらに前記電解メツキ
より高い電流密度でメツキを行う。その陰極電流
密度としては5A／ｄm2以上、更には8A／ｄm2以
上が好ましく、陰極電流密度を大きくすると幅方
向への太りが抑制される。陰極電流密度は高い程
好ましく、パルスメツキなども好ましく用いられ
る。陰極電流密度の上限はやけにより決定され
る。 Next, plating is further performed at a higher current density than the electrolytic plating until a predetermined film thickness is reached. The cathode current density is preferably 5 A/dm 2 or more, more preferably 8 A/dm 2 or more, and increasing the cathode current density suppresses thickening in the width direction. The higher the cathode current density is, the more preferable it is, and pulse plating is also preferably used. The upper limit of cathode current density is determined by burnout.
第１図及び第２図は、ピロリン酸銅メツキ液を
用い陰極電流密度2A／ｄm2と5A／ｄm2で電解メ
ツキしたときの電解メツキ層の断面成長を示す図
で、金属薄板上にレジストを5μm厚形成し、レジ
スト幅40μm、間隔85μm（線密度８本／mm）のレ
ジストパターン上に電解メツキにより導電体層を
成長させた場合の例である。 Figures 1 and 2 show the cross-sectional growth of an electroplated layer when electrolytically plated using a copper pyrophosphate plating solution at cathode current densities of 2 A/dm 2 and 5 A/dm 2. This is an example in which a conductor layer is grown by electrolytic plating on a resist pattern with a resist width of 40 μm and an interval of 85 μm (line density of 8 lines/mm).
陰極電流密度が2A／ｄm2の電解メツキでは、
電解メツキ層の幅方向は厚み方向の約２倍の速さ
で成長し、厚さ方向で25μm成長したときに隣接
のメツキ層と衝突し短絡してしまう（第１図）の
に対し、陰極電流密度が5A／ｄm2の電解メツキ
では逆にメツキ層の厚さ方向の成長は、幅方向の
２倍に近い速さで成長する（第２図）。 In electrolytic plating with a cathode current density of 2A/ dm2 ,
The electroplated layer grows at about twice the speed in the width direction as in the thickness direction, and when it grows to 25 μm in the thickness direction, it collides with the adjacent plating layer and short-circuits (Figure 1). In electrolytic plating at a current density of 5 A/dm 2 , on the other hand, the plating layer grows at a rate nearly twice as fast in the thickness direction as in the width direction (Figure 2).
第３図は、第１図、第２図で説明した手法で得
た電解メツキ層の幅方向の成長長さに対して成長
厚さ方向の長さをプロツトして得た電解メツキ層
の成長曲線で、ピロリン酸銅メツキ液を用いる電
解メツキでは、厚さ方向のメツキ層成長速度が幅
方向のメツキ層成長速度よりも著しく大きいとい
う異方向性のメツキ層成長が陰極電流密度5A／
ｄm2以上で生じることを示している。 Figure 3 shows the growth of the electroplated layer obtained by plotting the length in the growth thickness direction against the growth length in the width direction of the electroplated layer obtained by the method explained in Figures 1 and 2. The curve shows that in electrolytic plating using a copper pyrophosphate plating solution, the plating layer grows in an anisotropic direction in which the plating layer growth rate in the thickness direction is significantly higher than the plating layer growth rate in the width direction at a cathode current density of 5A/
This shows that this occurs at dm 2 or higher.
本発明の方法は、配線密度の低い所で使うこと
も可能であるが、工業的には３本／mm以上特に５
本／mm以上の配線密度に対し好適である。 Although the method of the present invention can be used in places with low wiring density, it is industrially suitable for wiring of 3 wires/mm or more, especially 5 wires/mm.
Suitable for wiring density of lines/mm or more.
更に本発明は導電パターンの占積率が50％以上
特に70％以上の場合好適である。 Furthermore, the present invention is suitable when the space factor of the conductive pattern is 50% or more, particularly 70% or more.
本発明において、レジストの剥離を行なう方法
は、市販の剥離液を使えば良く、たとえばインダ
ストーリ−ケミーラボラトリ（Indust−Ri−
Chem−Laboratory）社製レジストストリツパー
Ｊ−100等を用いて、スプレー或いは浸漬などに
よれば良い。ただし、剥離液は、金属薄板、メツ
キ金属を侵さぬ物を選ぶ必要がある。 In the present invention, a commercially available stripping solution may be used to strip the resist.
It may be applied by spraying or dipping using a resist stripper J-100 manufactured by Chem-Laboratory. However, it is necessary to choose a stripping solution that does not attack the thin metal plate or plated metal.
本発明において金属薄板を除去する方法として
は、剥離又はエツチング等が考えられ、全面除去
する場合は剥離でもエツチングでもよい。又、金
属薄板の回路部以外のところを除去する場合には
エツチングが用いられる。金属薄板をエツチング
除去する方法としては、使用した金属薄板を溶解
する溶液を用いて、スプレー或いは浸漬などによ
るエツチング方法が用いられる。金属薄板として
アルミニウム、スズ、亜鉛を用いた場合は、電解
メツキ導電体をエツチングしない例えばアルカリ
水溶液でエツチングする事が好ましいが、希塩酸
等の酸性水溶液でエツチングする事も可能であ
る。 In the present invention, methods for removing the thin metal plate include peeling or etching, and in the case of removing the entire surface, either peeling or etching may be used. Etching is also used to remove parts of the thin metal plate other than the circuit portion. To remove the thin metal plate by etching, an etching method such as spraying or immersion using a solution that dissolves the used thin metal plate is used. When aluminum, tin, or zinc is used as the thin metal plate, it is preferable not to etch the electrolytically plated conductor, for example, to etch it with an alkaline aqueous solution, but it is also possible to etch it with an acidic aqueous solution such as dilute hydrochloric acid.
本発明により得られた微細厚膜印刷回路基板
は、工業的には抵抗値の小さい小型コイル、高密
度コネクター、高密度配線などにおいて特に好適
である。 The fine thick film printed circuit board obtained according to the present invention is particularly suitable for use in industrial applications such as small coils with low resistance, high-density connectors, and high-density wiring.
以下に本発明の態様を一層明確にする為に、実
施例を挙げて説明するが、本発明は以下の実施例
に限定されるものではなく、種々の変形が可能で
ある。 EXAMPLES In order to further clarify aspects of the present invention, examples will be described below, but the present invention is not limited to the following examples, and various modifications can be made.
実施例 １
膜厚40μmアルミニウム薄板上に、イーストマ
ンコダツク社製ネガ型レジスト「マイクロレジス
ト747−110cst」を乾燥後、膜厚が5μmになる様
に塗布、プレベークして、回路パターンマスクを
通して高圧水銀ランプで露光し、専用の現像液お
よびリンス液を用いて現像し、ポストベークし
て、回路部以外の部分にレジストを形成した。Example 1 After drying, a negative resist "Microresist 747-110cst" manufactured by Eastman Kodak Co., Ltd. was applied on a thin aluminum plate with a film thickness of 40 μm to a film thickness of 5 μm, prebaked, and exposed to high pressure through a circuit pattern mask. It was exposed to light using a mercury lamp, developed using a special developer and rinse solution, and post-baked to form a resist in areas other than the circuit area.
次いでハーシヨウ村田社製ピロリン酸銅メツキ
液を用いて、アルミニウム薄板を陰極とし、初め
電流密度0.5A／ｄm2で平均膜厚2μmの銅を電解
メツキした後、電流密度を8A／ｄm2に増加させ、
計100μm厚の銅を回路部に形成した。 Next, using a copper pyrophosphate plating solution manufactured by Hershiyo Murata Co., Ltd., and using a thin aluminum plate as a cathode, copper with an average thickness of 2 μm was electrolytically plated at an initial current density of 0.5 A/dm 2 , and then the current density was increased to 8 A/dm 2 . let me,
A total of 100 μm thick copper was formed in the circuit section.
その後、エポキシ系表面コート材（日本ペルノ
ツクス社製ME−264主剤とHV−106硬化剤を重
量比で100：27に混合した物）で導電パターン面
をオーバーコートした。次にアルミニウム薄板を
36重量％の塩酸を水で２：３に希釈した液でエツ
チング除去した。その結果配線密度８本／mm、導
体膜厚100μmの微細厚膜印刷回路基板を得た。メ
ツキ工程でのアルミニウム薄板と銅メツキ層との
剥離はみられず、導電体ラインの端に突起もな
く、メツキ工程とそれ以後の工程全体での収率は
85％であつた。 Thereafter, the conductive pattern surface was overcoated with an epoxy surface coating material (a mixture of ME-264 main agent and HV-106 curing agent manufactured by Nippon Pernox Co., Ltd. in a weight ratio of 100:27). Next, a thin aluminum plate
Etching was performed using a solution prepared by diluting 36% by weight of hydrochloric acid with water at a ratio of 2:3. As a result, a fine thick film printed circuit board with a wiring density of 8 lines/mm and a conductor film thickness of 100 μm was obtained. There was no peeling between the aluminum thin plate and the copper plating layer during the plating process, and there were no protrusions at the ends of the conductor lines, and the overall yield in the plating process and subsequent processes was low.
It was 85%.
実施例 ２
膜厚50μm亜鉛薄板上に、イーストマンコダツ
ク社製ネガ型レジスト「マイクロレジスト747−
110cst」を乾燥後、膜厚が2μmになる様に塗布、
プレベークして、回路パターンマスクを通して高
圧水銀ランプで露光し、専用の現像液およびリン
ス液を用いて現像し、ポストベークして、回路部
以外の部分にレジストを形成した。Example 2 A negative resist "Microresist 747-" manufactured by Eastman Kodak Co., Ltd.
110cst" after drying, apply it to a film thickness of 2μm,
It was prebaked, exposed to light using a high pressure mercury lamp through a circuit pattern mask, developed using a special developer and rinse solution, and postbaked to form a resist in areas other than the circuit portion.
次いでハーシヨウ村田社製ピロリン酸銅メツキ
液を用いて、亜鉛薄板を陰極とし、初め電流密度
1A／ｄm2で平均膜厚5μmの銅を電解メツキした
後、電流密度を5A／ｄm2に増加させ、計500μm
厚の銅を回路部に形成した。 Next, using a copper pyrophosphate plating solution manufactured by Harshiyo Murata Co., Ltd., a thin zinc plate was used as a cathode, and the current density was initially increased.
After electrolytically plating copper with an average film thickness of 5 μm at 1 A/dm 2 , the current density was increased to 5 A/dm 2 and a total of 500 μm
A thick copper layer was formed on the circuit section.
ボスチツク社製XA−564−４フエノール樹脂
系接着剤を導体パターンが形成されていない側に
塗布し、シエルケミカル社製トラドロンフイルム
（厚さ25μm）に貼りつけ、次に回路部以外の所に
あるレジストをインダストーリーケミーラボラト
リ社製レジストストリツプＪ−100液を用いてレ
ジストを除去した。レジストで覆われていた亜鉛
薄板を36重量％の塩酸を水で２：３に希釈した液
でエツチング除去し、配線密度12本／mm導体膜厚
50μmの微細厚膜印刷回路基板を得た。 Apply Bostik's XA-564-4 phenolic resin adhesive to the side where the conductor pattern is not formed, paste it on Ciel Chemical's Tradron film (thickness 25 μm), and then apply it to the area other than the circuit area. A certain resist was removed using a resist strip J-100 solution manufactured by Industrie Chemie Laboratory. The thin zinc plate covered with resist was removed by etching with a solution of 36% by weight hydrochloric acid diluted 2:3 with water, resulting in a wiring density of 12 lines/mm conductor film thickness.
A fine thick film printed circuit board of 50 μm was obtained.
メツキ工程での亜鉛薄板と銅メツキ層との剥離
や導電体ラインの端に突起は見られず、メツキ工
程とそれ以後の工程全体での収率は90％であつ
た。 There was no peeling between the zinc thin plate and the copper plating layer during the plating process, and no protrusions were observed at the ends of the conductor lines, and the overall yield in the plating process and subsequent processes was 90%.
比較例として実施例２において初期の電流密度
1A／ｄm2で5μm銅メツキする工程を省き、電流
密度5A／ｄm2のまま膜厚55μmの銅をメツキし、
後の工程を実施例２と同一にしたところ、一部銅
メツキ層と基板との剥離が見られ、メツキ工程と
それ以後の工程全体での収率は70％であつた。 As a comparative example, the initial current density in Example 2
By omitting the step of plating 5μm copper at 1A/ dm2 , we plated copper with a thickness of 55μm while keeping the current density at 5A/ dm2 .
When the subsequent steps were the same as in Example 2, some peeling between the copper plating layer and the substrate was observed, and the overall yield in the plating step and subsequent steps was 70%.
実施例 ３
膜厚20μmスズ薄板上に、イーストマンコダツ
ク社製ネガ型レジスト「マイクロレジスト747−
110cst」を乾燥後、膜厚が5μmになる様に塗布、
プレベークして、回路パターンマスクを通して高
圧水銀ランプで露光し、専用の現像液およびリン
ス液を用いて現像し、ポストベークして、回路部
以外の部分にレジストを形成した。Example 3 A negative resist “Microresist 747-” manufactured by Eastman Kodak Co., Ltd.
After drying, apply ``110cst'' to a film thickness of 5μm.
It was prebaked, exposed to light using a high pressure mercury lamp through a circuit pattern mask, developed using a special developer and rinse solution, and postbaked to form a resist in areas other than the circuit portion.
次いでハーシヨウ村田社製ピロリン酸銅メツキ
液を用いて、スズ薄板を陰極とし、初め電流密度
0.1A／ｄm2で平均膜厚0.5μmの銅を電解メツキし
た後、電流密度を5A／ｄm2に増加させ、50μm厚
の銅を回路部に形成した。導電パターンが形成さ
れた面にボスチツク社製XA−564−４フエノー
ル樹脂系接着剤を塗布しシエルケミカル社製トラ
ドロンフイルム（厚さ25μm）に貼り付け、スズ
薄板を36重量％の塩酸を水で２：３に希釈した液
でエツチング除去した。その結果配線密度12本／
mm、導体膜厚50μmの微細厚膜印刷回路基板が得
られ、メツキ工程でのスズ薄板と銅メツキ層との
剥離や導電体ラインの端の突起は見られず、メツ
キ工程とそれ以後の工程全体での収率は85％であ
つた。 Next, using a copper pyrophosphate plating solution manufactured by Harshio Murata Co., Ltd., a thin tin plate was used as a cathode, and the current density was initially increased.
After electrolytically plating copper with an average thickness of 0.5 μm at 0.1 A/dm 2 , the current density was increased to 5 A/dm 2 to form a 50 μm thick copper on the circuit portion. Apply XA-564-4 phenolic resin adhesive manufactured by Bostik Co., Ltd. to the surface on which the conductive pattern was formed, and attach it to Tradron film (thickness 25 μm) manufactured by Ciel Chemical Company. It was removed by etching with a 2:3 diluted solution. As a result, the wiring density is 12 lines/
A fine thick-film printed circuit board with a conductor film thickness of 50 μm was obtained, and no peeling between the tin thin plate and the copper plating layer or protrusions at the ends of the conductor lines were observed during the plating process, and the plating process and subsequent steps were not observed. The overall yield was 85%.
第１図は2A／ｄm2の陰極電流密度で電解メツ
キを行つた場合の電解メツキ層の成長状況を示す
図、第２図は5A／ｄm2の陰極電流密度で電解メ
ツキを行つた場合の電解メツキ層の生長状況を示
す図、第３図はピロリン酸銅メツキ液を用いた電
解メツキによる電解メツキ厚の成長曲線である。
図中、１は金属薄板、２はレジスト、３は導電
体層を示す。
Figure 1 shows the growth of the electrolytically plated layer when electrolytically plated at a cathode current density of 2A/ dm2 , and Figure 2 shows the growth of the electrolytically plated layer when electrolytically plated at a cathode current density of 5A/ dm2 . FIG. 3, which is a diagram showing the growth status of the electrolytically plated layer, is a growth curve of the electrolytically plated thickness by electrolytically plating using a copper pyrophosphate plating solution. In the figure, 1 is a metal thin plate, 2 is a resist, and 3 is a conductor layer.
Claims (1)
ニウム又は錫の金属薄板上にレジストを回路部以
外の所に設け、電流密度0.05〜2A／ｄm2で膜厚
0.3〜10μmまでピロリン酸銅メツキをした後、所
定の膜厚まで５〜20A／ｄm2の電流密度でピロリ
ン酸銅メツキして回路部に導電体を形成し、その
後、該金属薄板の全面又は回路部以外の所を除去
することを特徴とする線密度３本／mm以上の配線
パターンを有する微細厚膜印刷回路基板の製法。1. A resist is placed on a zinc, aluminum, or tin metal thin plate with a thickness of more than 10 μm and less than 200 μm in areas other than the circuit area, and the film thickness is increased at a current density of 0.05 to 2 A/dm 2.
After plating copper pyrophosphate to a thickness of 0.3 to 10 μm, copper pyrophosphate plating is performed at a current density of 5 to 20 A/dm 2 to a predetermined thickness to form a conductor in the circuit area, and then the entire surface of the thin metal plate or A method for manufacturing a fine thick-film printed circuit board having a wiring pattern with a line density of 3 lines/mm or more, characterized by removing areas other than circuit parts.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9147981A JPS57207392A (en) | 1981-06-16 | 1981-06-16 | Method of producing ultrafine thick film printed circuit board |
| US06/323,337 US4401521A (en) | 1980-11-28 | 1981-11-20 | Method for manufacturing a fine-patterned thick film conductor structure |
| EP81305603A EP0053490B1 (en) | 1980-11-28 | 1981-11-26 | Method for manufacturing a fine-patterned thick film conductor structure |
| DE8181305603T DE3170956D1 (en) | 1980-11-28 | 1981-11-26 | Method for manufacturing a fine-patterned thick film conductor structure |
| AT81305603T ATE13794T1 (en) | 1980-11-28 | 1981-11-26 | PROCESS FOR MAKING A FINE PATTERNED STRUCTURE WITH THICK FILM CONDUCTORS. |
| KR1019810004604A KR850001363B1 (en) | 1980-11-28 | 1981-11-27 | Method for manufacturing a fine patterned thick film conductor structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9147981A JPS57207392A (en) | 1981-06-16 | 1981-06-16 | Method of producing ultrafine thick film printed circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57207392A JPS57207392A (en) | 1982-12-20 |
| JPH025313B2 true JPH025313B2 (en) | 1990-02-01 |
Family
ID=14027534
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9147981A Granted JPS57207392A (en) | 1980-11-28 | 1981-06-16 | Method of producing ultrafine thick film printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57207392A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5250570A (en) * | 1975-10-20 | 1977-04-22 | Seiko Instr & Electronics | Method of producing circuit substrate |
| JPS52124172A (en) * | 1976-04-13 | 1977-10-18 | Fuji Photo Film Co Ltd | Method of producing printed circuit substrate |
| JPS5381966A (en) * | 1976-12-27 | 1978-07-19 | Hirotoshi Nomura | Method of producing electric circuit part |
-
1981
- 1981-06-16 JP JP9147981A patent/JPS57207392A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5250570A (en) * | 1975-10-20 | 1977-04-22 | Seiko Instr & Electronics | Method of producing circuit substrate |
| JPS52124172A (en) * | 1976-04-13 | 1977-10-18 | Fuji Photo Film Co Ltd | Method of producing printed circuit substrate |
| JPS5381966A (en) * | 1976-12-27 | 1978-07-19 | Hirotoshi Nomura | Method of producing electric circuit part |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57207392A (en) | 1982-12-20 |
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