JPH0252895B2 - - Google Patents
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- Publication number
- JPH0252895B2 JPH0252895B2 JP16704783A JP16704783A JPH0252895B2 JP H0252895 B2 JPH0252895 B2 JP H0252895B2 JP 16704783 A JP16704783 A JP 16704783A JP 16704783 A JP16704783 A JP 16704783A JP H0252895 B2 JPH0252895 B2 JP H0252895B2
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- Japan
- Prior art keywords
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- rectangular wave
- circuit
- output
- control signal
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- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 22
- 238000010586 diagram Methods 0.000 description 7
- 239000002131 composite material Substances 0.000 description 3
- 238000007493 shaping process Methods 0.000 description 3
- 238000001514 detection method Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Stereo-Broadcasting Methods (AREA)
- Noise Elimination (AREA)
Description
【発明の詳細な説明】
(イ) 産業上の利用分野
本発明は、矩形波信号中に含まれる奇数次高調
波信号を除去する為の高調波除去回路に関するも
ので、特にFMラジオ受信機の検波出力信号中に
含まれるステレオパイロツト信号のキヤンセル信
号中の高調波信号の除去やステレオマルチプレツ
クス回路で用いられる38KHzスイツチング信号中
の高調波を除去するのに適するものである。
(ロ) 従来技術
FMステレオ受信機のFM検波出力信号中に含
まれる19KHzステレオパイロツト信号をキヤンセ
ルする為のパイロツトキヤンセル回路が知られて
いる。その場合、前記ステレオパイロツト信号
は、サイン波であるから、通常は波形整形回路を
用いて19KHz矩形波信号をサイン波あるいはサイ
ン波に近い三角波に整形し、それをキヤンセル信
号として用いている。しかしながら波形整形回路
は、普通インダクタンスやキヤパシタンスを必要
とするので、前記波形整形回路の使用は、IC（集
積回路）化の妨げとなるという欠点を有してい
た。一方キヤンセル信号として19KHz矩形波信号
を直接用いると、前記矩形波信号中に含まれる高
調波信号が妨害を与え、Ｓ／Ｎが悪化するという
欠点が生じるので、前記矩形波信号をキヤンセル
信号として使用することが出来なかつた。
また、ステレオマルチプレツクス回路において
は、従来から38KHz矩形波スイツチング信号を用
いてステレオ復調を行つているが、ステレオコン
ポジツト信号中に含まれる隣接局の干渉に起因す
る114KHz近傍のビート信号と、前記38KHz矩形
波スイツチング信号中の第３高調波（114KHz）
とのビートが生じ、ビート妨害が発生するという
欠点を有していた。
(ハ) 発明の目的
本発明は、上述の如く様々な妨害を引き起す矩
形波信号中の奇数次高調波成分を、除去する為の
高調波除去回路を提供せんとするものである。
(ニ) 発明の構成
本発明に係る高調波除去回路は、正逆２つの矩
形波信号とそれらの奇数次高調波信号とを用いて
制御信号を発生する制御信号発生回路と、該制御
信号発生回路の一方の出力制御信号に応じてそれ
ぞれ第１及び第２矩形波信号のデユーテイ信号を
発生する第１及び第２信号発生回路と、前記制御
信号発生回路の出力信号に応じてそれぞれ第１及
び第２矩形波信号を分割する第１及び第２信号分
割回路によつて構成され、前記第１及び第２信号
発生回路の出力信号と前記第１及び第２信号分割
回路の出力信号とを適宜混合して高調波除去を行
うものである。
(ホ) 実施例
第１図は、本発明の一実施例を示すもので、１
は周波数1の第１矩形波信号が印加される第１入
力端子、２は前記第１矩形波信号と逆相の第２矩
形波信号が印加される第２入力端子、３は制御信
号発生回路、４及び５は第１及び第２信号発生回
路、６及び７は第１及び第２信号分割回路、８及
び９は高調波が除去された矩形波信号が得られる
第１及び第２出力端子である。前記制御信号発生
回路３は、第２図に示す如く、第１及び第２アン
ド回路１０及び１１と、オア回路１２と、インバ
ータ１３とによつて構成されている。しかして、
第１アンド回路１０の第１入力端子１４には、第
３図イに示す如き周波数1の第１矩形波信号が、
第２入力端子１５には、第３図ハに示す如き周波
数2（＝31）の第１高調波信号がそれぞれ印加さ
れ、第２アンド回路１１の第１入力端子１６に
は、第３図ロに示す如き周波数1の第２矩形波信
号が、第２入力端子１７には、第３図ニに示す如
き周波数2の第２高調波信号がそれぞれ印加され
る。その結果第１アンド回路１０の出力端には、
第３図ホの信号が、第２アンド回路１１の出力端
には第３図ヘの信号がそれぞれ得られ、オア回路
１２の出力端（第１出力端子１８）には第３図ト
の信号が、インバータ１３の出力端（第２出力端
子１９）には第３図チの信号がそれぞれ得られ
る。前記第１出力端子１８に得られる信号は、第
１制御信号として、前記第２出力端子１９に得ら
れる信号は、第２制御信号として第１図の第１及
び第２信号発生回路４及び５と第１及び第２信号
分圧回路６及び７に印加される。
再び第１図に戻つて、いま第１制御信号が
「Ｈ」のとき、第１及び第２信号発生回路４及び
５が作動し、出力を発生させるものとする。ま
た、第１及び第２信号分割回路６及び７の分割比
を、３：１（＝ｎ：１）とする。時刻t1に、第３
図イの「Ｈ」信号が第１入力端子１に、第３図ロ
の「Ｌ」信号が第２入力端子２に印加されている
とすれば、制御信号発生回路３から第１及び第２
信号発生回路４及び５に、第３図トの「Ｈ」信号
が印加され、第１及び第２信号分割回路６及び７
に、第３図チの「Ｌ」信号が印加されることによ
り、第１信号発生回路４の出力端４ａに「Ｈ」信
号が、第２信号発生回路５の出力端５ａに「Ｌ」
信号がそれぞれ発生し、その状態は時刻t2迄続
く。その時、第１及び第２信号分割回路６及び７
には、「Ｌ」の制御信号が印加されているので、
出力が発生しない。時刻t2となり、第１及び第２
信号発生回路４及び５に印加される制御信号が
「Ｌ」第１及び第２信号分割回路６及び７に印加
される制御信号が「Ｈ」となると、第１信号分割
回路６の第１出力端６ａに「3/4Ｈ」の出力信号
が、第２出力端６ｂに「1/4Ｈ」の出力信号がそ
れぞれ発生し、第２信号分割回路７の第１出力端
７ａに「3/4Ｌ」の出力信号が、第２出力端７ｂ
に「1/4Ｌ」の出力信号がそれぞれ発生する。そ
の為、第１出力端子８には「2/4Ｈ」の出力信号
が、第２出力端子９には「2/4Ｌ」の出力信号が
それぞれ得られる。この状態は、時刻t3迄続く。
時刻t3になると、第１入力端子１に印加される信
号が「Ｌ」に、第２入力端子２に印加される信号
が「Ｈ」に反転する。その為、第１信号分割回路
６の第１出力端６ａに「3/4Ｌ」の出力信号が、
第２出力端６ｂに「1/4Ｌ」の出力信号がそれぞ
れ発生し、第２信号分割回路７の第１出力端７ａ
に「3/4Ｈ」の出力信号が、第２出力端７ｂに
「1/4Ｈ」の出力信号がそれぞれ発生する。従つ
て、第１出力端子８には「2/4Ｌ」の出力信号が、
第２出力端子９には「2/4Ｈ」の出力信号がそれ
ぞれ得られる。この状態は、時刻t4迄続く。時刻
t4になると、再び第１及び第２信号発生回路４及
び５に印加される制御信号が「Ｈ」に、第１及び
第２信号分割回路６及び７に印加される制御信号
が「Ｌ」になる。その為、第１信号発生回路４の
出力端４ａに「Ｌ」信号が、第２信号発生回路５
の出力端５ａに「Ｈ」信号が発生し、その状態は
時刻t5迄続く。時刻t5になると、第１及び第２信
号分割回路６及び７に印加される制御信号が
「Ｈ」となり、前記第１信号分割回路６の第１出
力端６ａに「3/4Ｌ」の出力信号が、第２出力端
６ｂに「1/4Ｌ」の出力信号がそれぞれ発生し、
第２信号分割回路７の第１出力端７ａに「3/4Ｈ」
の出力信号が、第出力端７ｂに「1/4Ｈ」の出力
信号がそれぞれ発生する。その為、第１出力端子
８に「2/4Ｌ」の出力信号が、第２出力端子９に
「2/4Ｈ」の出力信号がそれぞれ発生する。この状
態は、時刻t6迄続く。時刻t6になると、第１入力
端子１に印加される信号が「Ｈ」に、第２入力端
子２に印加される信号が「Ｌ」に反転するので、
第１信号分割回路６の第１出力端６ａから「3/4
Ｈ」の出力信号が、第２出力端６ｂから「1/4Ｈ」
の出力信号が発生し、第２信号分割回路７の第１
出力端７ａから「3/4Ｌ」の出力信号が、第２出
力端７ｂから「1/4Ｌ」の出力信号がそれぞれ発
生する。その為、第１出力端子８に「2/4Ｈ」の
出力信号が、第２出力端子９に「2/4Ｌ」の出力
信号がそれぞれ発生し、その状態が時刻t7迄続
く。時刻t1からt7迄で１サイクルの動作が完了
し、その後は前記動作を繰り返す。その結果、第
１出力端子８には、第３図リの信号が、第２出力
端子９には、第３図ヌの信号が得られる。第３図
リ及びヌの信号は、第３図イ及びロの信号から、
第３高調波成分が除去されたものであり、結果と
して高調波の除去が達成される。尚、実施例にお
いては、矩形波信号から第３高調波信号を除去す
る場合を説明したが、第３図イ及びロの信号と正
負の第５高調波信号とを用いて第１及び第２制御
信号を作成するとともに、第１及び第２信号分割
回路の分割比を５：１にすれば、矩形波信号から
第５高調波成分を除去することが出来る。これを
一般形式で表わせば、矩形波信号とその第ｎ次
（ｎは奇数）高調波信号とを用いて第１及び第２
制御信号を作成し、第１及び第２信号分割回路６
及び７の分割比をｎ：１とすれば、第ｎ次高調波
成分の除去が達成されるということになる。ま
た、先に述べた各高調波成分を除去する回路を直
列接続すれば、矩形波信号の奇数次高調波成分を
すべて除去することが出来る。
第４図は、FMステレオ信号中の19KHzステレ
オパイロツト信号をキヤンセルする為のキヤンセ
ル信号発生回路に本発明を応用した例を示すもの
で、初段差動増幅部２０を構成する一対のトラン
ジスタ２１及び２２のベースには、互いに逆相の
19KHz矩形波信号が印加される。しかして、前記
19KHz矩形波信号は、前記初段差動増幅部２０で
増幅された後、前記トランジスタ２１及び２２の
コレクタからレベル制御回路２３に印加される。
前記レベル制御回路２３は、トランジスタ２４及
び２５から成る第１差動部２６と、トランジスタ
２７及び２８から成る第２差動部２９から成り、
前記第１差動部２６を構成するトランジスタ２４
及び２５の共通エミツタに、前記初段増幅部２０
の第１出力信号が、前記第２差動部２９を構成す
るトランジスタ２７及び２８の共通エミツタに、
前記初段増幅部２０の第２出力信号がそれぞれ印
加される。前記レベル制御回路２３の制御入力端
子３０及び３１に、FMステレオ信号中の19KHz
ステレオパイロツト信号のレベルに応じた直流制
御信号が印加されると、該制御信号に応じて、ト
ランジスタ２４，２５，２７及び２８の導通度が
決まり、トランジスタ２４及び２７の共通コレク
タに、前記パイロツト信号レベルに応じた19KHz
矩形波信号が発生し、それと逆相の19KHz矩形波
信号がトランジスタ２５及び２８の共通コレクタ
に発生する。レベル制御回路２３の両出力信号
は、57KHz高調波信号（第３高調波信号）を除去
する為の第１高調波除去回路３２に印加される。
前記第１高調波除去回路３２は、第１図の第１信
号発生回路４に対応するトランジスタ３３と、第
２信号発生回路５に対応するトランジスタ３４
と、第１信号分割回路６に対応するトランジスタ
３５及び３６と、第２信号分割回路７に対応する
トランジスタ３７及び３８とによつて構成されて
おり、第１及び第２制御入力端子３９及び４０に
印加される制御信号に応じて、出力端に57KHz高
調波成分が除去された19KHz矩形波信号を発生さ
せるものである。その際前記制御信号は、正負の
19KHz矩形波信号と、正負の57KHz矩形波信号と
を用いて作成される。前記第１高調波除去回路３
２の動作については、第１図の場合と略同一に付
省略する。
前記第１高調波除去回路３２の第３図リ及びヌ
の如き形状を有する２つの出力信号は、95KHzの
第５高調波を除去する為の第２高調波除去回路４
１に印加される。そして、前記第２高調波除去回
路４１の出力端に接続された第１及び第２出力端
子４２及び４３に、第３及び第５高調波信号が除
去された19KHz矩形波信号が得られる。前記第２
高調波除去回路４１は、第１及び第２制御信号入
力端子４４及び４５に正負の19KHz矩形波信号と
正負の95KHz矩形波信号とを用いて作成される制
御信号が印加される点を除き第１高調波除去回路
３２と同一の構成である。前記第１もしくは第２
出力端子４２もしくは４３に得られる19KHz矩形
波信号を、FMステレオ信号と混合することによ
り、19KHzステレオパイロツト信号のキヤンセル
が行なわれる。
第５図は、ステレオマルチプレツクス回路に本
発明に係る高調波信号除去回路を適用した例を示
す回路図である。第１入力端子４６に印加される
ステレオコンポジツト信号と、第２及び第３入力
端子４７及び４８に印加される互いに逆相の38K
Hzスイツチング信号とを乗算し、トランジスタ４
９及び５０の共通コレクタに左ステレオ信号Ｌ
を、トランジスタ５１及び５２の共通コレクタに
右ステレオ信号Ｒをそれぞれ得るステレオマルチ
プレツクス回路５３が知られている。しかして、
ステレオコンポジツト信号中には、114KHz近傍
のビート成分が含まれており、このビート成分と
38KHzスイツチング信号の114KHzの第３高調波
とによつてビートが生じ、このビートが雑音の原
因になる。しかして、前記ステレオマルチプレツ
クス回路５３の左右出力端５４及び５５に得られ
る信号（38KHz矩形波信号）を入力信号とする高
調波除去回路５６を設け、38KHz矩形波信号と
114KHz矩形波信号とから作成される信号を制御
信号として第１及び第２制御入力端子５７及び５
８に印加すれば、前記38KHz矩形波信号中の
114KHzの第３高調波成分が除去され、ビート妨
害を防止することが出来る。第５図の詳細な動作
説明は、重複するので省略する。
(ヘ) 発明の効果
以上述べた如く、本発明に依れば、矩形波信号
中の高調波成分を確実に除去し得る高調波除去回
路を提供出来る。特に、本発明に依れば、外付回
路を必要とせず、簡単な構成で前記高調波除去回
路を作成出来るので、IC化に適するという利点
が生じる。 [Detailed Description of the Invention] (a) Field of Industrial Application The present invention relates to a harmonic removal circuit for removing odd harmonic signals contained in a rectangular wave signal, and is particularly applicable to FM radio receivers. It is suitable for removing harmonic signals in the cancellation signal of the stereo pilot signal contained in the detection output signal and for removing harmonics in the 38KHz switching signal used in the stereo multiplex circuit. (b) Prior Art A pilot cancel circuit for canceling a 19KHz stereo pilot signal included in an FM detection output signal of an FM stereo receiver is known. In that case, since the stereo pilot signal is a sine wave, a waveform shaping circuit is usually used to shape the 19KHz rectangular wave signal into a sine wave or a triangular wave close to a sine wave, and this is used as a cancel signal. However, since waveform shaping circuits usually require inductance and capacitance, the use of the waveform shaping circuits has the drawback of hindering integration into ICs (integrated circuits). On the other hand, if a 19KHz square wave signal is directly used as a cancel signal, the harmonic signal contained in the square wave signal causes interference and the S/N ratio deteriorates, so the square wave signal is used as a cancel signal. I couldn't do it. Furthermore, in stereo multiplex circuits, stereo demodulation has conventionally been performed using a 38KHz square wave switching signal, but the beat signal around 114KHz caused by interference from adjacent stations contained in the stereo composite signal and the above-mentioned 3rd harmonic (114KHz) in 38KHz square wave switching signal
This has the drawback that a beat occurs, causing beat disturbance. (C) Object of the Invention The present invention provides a harmonic removal circuit for removing odd harmonic components in a rectangular wave signal that cause various disturbances as described above. (D) Structure of the Invention The harmonic removal circuit according to the present invention includes a control signal generation circuit that generates a control signal using two forward and reverse rectangular wave signals and their odd-order harmonic signals, and a control signal generation circuit that generates a control signal using first and second signal generation circuits that generate duty signals of first and second rectangular wave signals, respectively, in response to an output control signal of one of the circuits; It is configured by first and second signal dividing circuits that divide a second rectangular wave signal, and appropriately divides the output signals of the first and second signal generating circuits and the output signals of the first and second signal dividing circuits. It mixes and removes harmonics. (E) Embodiment FIG. 1 shows an embodiment of the present invention.
1 is a first input terminal to which a first rectangular wave signal of frequency 1 is applied; 2 is a second input terminal to which a second rectangular wave signal having an opposite phase to the first rectangular wave signal is applied; 3 is a control signal generation circuit , 4 and 5 are first and second signal generation circuits, 6 and 7 are first and second signal division circuits, and 8 and 9 are first and second output terminals from which rectangular wave signals with harmonics removed are obtained. It is. The control signal generation circuit 3 is composed of first and second AND circuits 10 and 11, an OR circuit 12, and an inverter 13, as shown in FIG. However,
The first input terminal 14 of the first AND circuit 10 receives a first rectangular wave signal of frequency 1 as shown in FIG.
The first harmonic signal of frequency 2 (=3 1 ) as shown in FIG. 3C is applied to the second input terminal 15, and the first harmonic signal of frequency 2 (=3 1 ) as shown in FIG. A second rectangular wave signal of frequency 1 as shown in FIG. 3B is applied to the second input terminal 17, and a second harmonic signal of frequency 2 as shown in FIG. As a result, at the output terminal of the first AND circuit 10,
The signal E in FIG. 3 is obtained at the output terminal of the second AND circuit 11, the signal shown in FIG. However, the signals shown in FIG. 3H are obtained at the output terminal (second output terminal 19) of the inverter 13. The signal obtained at the first output terminal 18 is used as a first control signal, and the signal obtained at the second output terminal 19 is used as a second control signal in the first and second signal generation circuits 4 and 5 of FIG. is applied to the first and second signal voltage divider circuits 6 and 7. Returning to FIG. 1 again, it is assumed that when the first control signal is "H", the first and second signal generating circuits 4 and 5 operate and generate outputs. Further, the division ratio of the first and second signal division circuits 6 and 7 is set to 3:1 (=n:1). At time t 1 , the third
If the "H" signal in Figure A is applied to the first input terminal 1 and the "L" signal in Figure 3B is applied to the second input terminal 2, then
The "H" signal shown in FIG. 3 is applied to the signal generating circuits 4 and 5, and the first and second signal dividing circuits 6 and 7
By applying the "L" signal shown in FIG.
Each signal is generated and the state continues until time t2 . At that time, the first and second signal dividing circuits 6 and 7
Since the "L" control signal is applied to
No output occurs. At time t 2 , the first and second
When the control signals applied to the signal generation circuits 4 and 5 become "L" and the control signals applied to the first and second signal division circuits 6 and 7 become "H", the first output of the first signal division circuit 6 An output signal of "3/4H" is generated at the terminal 6a, an output signal of "1/4H" is generated at the second output terminal 6b, and "3/4L" is generated at the first output terminal 7a of the second signal dividing circuit 7. The output signal from the second output terminal 7b
An output signal of "1/4L" is generated respectively. Therefore, an output signal of "2/4H" is obtained at the first output terminal 8, and an output signal of "2/4L" is obtained at the second output terminal 9. This state continues until time t3 .
At time t3 , the signal applied to the first input terminal 1 is inverted to "L" and the signal applied to the second input terminal 2 is inverted to "H". Therefore, an output signal of "3/4L" is output to the first output terminal 6a of the first signal dividing circuit 6.
An output signal of "1/4L" is generated at the second output terminal 6b, and the first output terminal 7a of the second signal dividing circuit 7
An output signal of "3/4H" is generated at the second output terminal 7b, and an output signal of "1/4H" is generated at the second output terminal 7b. Therefore, the output signal of "2/4L" is output to the first output terminal 8.
A "2/4H" output signal is obtained at the second output terminal 9, respectively. This state continues until time t4 . time
At t 4 , the control signals applied to the first and second signal generation circuits 4 and 5 become "H" again, and the control signals applied to the first and second signal division circuits 6 and 7 become "L". become. Therefore, the "L" signal is output to the output terminal 4a of the first signal generation circuit 4, and the "L" signal is output to the output terminal 4a of the first signal generation circuit 4.
An "H" signal is generated at the output terminal 5a of the circuit, and this state continues until time t5 . At time t5 , the control signals applied to the first and second signal dividing circuits 6 and 7 become "H", and the first output terminal 6a of the first signal dividing circuit 6 outputs "3/4L". An output signal of "1/4L" is generated at the second output terminal 6b, respectively.
“3/4H” is applied to the first output terminal 7a of the second signal dividing circuit 7.
An output signal of "1/4H" is generated at the output terminal 7b, respectively. Therefore, an output signal of "2/4L" is generated at the first output terminal 8, and an output signal of "2/4H" is generated at the second output terminal 9. This state continues until time t6 . At time t6 , the signal applied to the first input terminal 1 is inverted to "H" and the signal applied to the second input terminal 2 is inverted to "L".
From the first output terminal 6a of the first signal dividing circuit 6 to "3/4
The output signal of "H" is "1/4H" from the second output terminal 6b.
The output signal of the second signal dividing circuit 7 is generated.
An output signal of "3/4L" is generated from the output terminal 7a, and an output signal of "1/4L" is generated from the second output terminal 7b. Therefore, an output signal of "2/4H" is generated at the first output terminal 8, and an output signal of "2/4L" is generated at the second output terminal 9, and this state continues until time t7 . One cycle of operation is completed from time t 1 to t 7 , and thereafter the above operation is repeated. As a result, the signal shown in FIG. 3 is obtained at the first output terminal 8, and the signal shown in FIG. 3 is obtained at the second output terminal 9. The signals shown in Fig. 3 are as follows from the signals shown in Fig. 3,
The third harmonic component is removed, and as a result, harmonic removal is achieved. In the embodiment, the case where the third harmonic signal is removed from the rectangular wave signal has been explained, but the first and second harmonic signals are removed using the signals in A and B of FIG. By creating a control signal and setting the division ratio of the first and second signal division circuits to 5:1, it is possible to remove the fifth harmonic component from the rectangular wave signal. Expressing this in general form, using a rectangular wave signal and its nth (n is an odd number) harmonic signal,
A control signal is created and the first and second signal dividing circuit 6
If the division ratio of . Further, by connecting the circuits for removing each harmonic component described above in series, it is possible to remove all odd harmonic components of the rectangular wave signal. FIG . 4 shows an example in which the present invention is applied to a cancel signal generation circuit for canceling a 19KHz stereo pilot signal in an FM stereo signal. The bases of
A 19KHz square wave signal is applied. However, the above
The 19 KHz rectangular wave signal is amplified by the first stage differential amplification section 20 and then applied to the level control circuit 23 from the collectors of the transistors 21 and 22.
The level control circuit 23 consists of a first differential section 26 consisting of transistors 24 and 25, and a second differential section 29 consisting of transistors 27 and 28,
Transistor 24 constituting the first differential section 26
and 25 common emitters, the first stage amplifier section 20
The first output signal is applied to the common emitter of the transistors 27 and 28 forming the second differential section 29 ,
The second output signals of the first stage amplifying section 20 are respectively applied. 19KHz in the FM stereo signal is connected to the control input terminals 30 and 31 of the level control circuit 23 .
When a DC control signal corresponding to the level of the stereo pilot signal is applied, the conductivity of the transistors 24, 25, 27 and 28 is determined according to the control signal, and the pilot signal is applied to the common collector of the transistors 24 and 27. 19KHz according to level
A square wave signal is generated, and a 19KHz square wave signal having the opposite phase thereto is generated at the common collector of transistors 25 and 28. Both output signals of the level control circuit 23 are applied to a first harmonic removal circuit 32 for removing the 57KHz harmonic signal (third harmonic signal).
The first harmonic removal circuit 32 includes a transistor 33 corresponding to the first signal generation circuit 4 in FIG. 1 and a transistor 34 corresponding to the second signal generation circuit 5.
, transistors 35 and 36 corresponding to the first signal dividing circuit 6, and transistors 37 and 38 corresponding to the second signal dividing circuit 7, and first and second control input terminals 39 and 40. In response to the control signal applied to the output terminal, a 19KHz rectangular wave signal from which 57KHz harmonic components have been removed is generated. At that time, the control signal is positive or negative.
It is created using a 19KHz square wave signal and positive and negative 57KHz square wave signals. The first harmonic removal circuit 3
Regarding the operation 2, it is substantially the same as in the case of FIG. 1, and the description thereof will be omitted. The two output signals of the first harmonic removal circuit 32 having shapes as shown in FIG .
1. Then, a 19KHz rectangular wave signal from which the third and fifth harmonic signals have been removed is obtained at first and second output terminals 42 and 43 connected to the output terminal of the second harmonic removal circuit 41 . Said second
The harmonic removal circuit 41 is the same except that a control signal created using a positive/negative 19KHz rectangular wave signal and a positive/negative 95KHz rectangular wave signal is applied to the first and second control signal input terminals 44 and 45. It has the same configuration as the first harmonic removal circuit 32. Said first or second
By mixing the 19KHz rectangular wave signal obtained at the output terminal 42 or 43 with the FM stereo signal, the 19KHz stereo pilot signal is canceled. FIG. 5 is a circuit diagram showing an example in which the harmonic signal removal circuit according to the present invention is applied to a stereo multiplex circuit. A stereo composite signal applied to the first input terminal 46 and a 38K signal of mutually opposite phase applied to the second and third input terminals 47 and 48.
Hz switching signal and transistor 4
Left stereo signal L to the common collector of 9 and 50
A stereo multiplex circuit 53 is known which obtains a right stereo signal R to the common collector of transistors 51 and 52, respectively. However,
The stereo composite signal contains a beat component around 114KHz, and this beat component and
The 114KHz third harmonic of the 38KHz switching signal causes a beat, which causes noise. Therefore, a harmonic removal circuit 56 is provided which receives as an input signal the signal (38KHz rectangular wave signal) obtained at the left and right output terminals 54 and 55 of the stereo multiplex circuit 53 .
The first and second control input terminals 57 and 5 use a signal created from the 114KHz rectangular wave signal as a control signal.
8, the 38KHz square wave signal
The third harmonic component of 114KHz is removed, making it possible to prevent beat interference. A detailed explanation of the operation in FIG. 5 will be omitted since it is redundant. (F) Effects of the Invention As described above, according to the present invention, it is possible to provide a harmonic removal circuit that can reliably remove harmonic components in a rectangular wave signal. In particular, according to the present invention, the harmonic removal circuit can be created with a simple configuration without the need for an external circuit, so there is an advantage that it is suitable for IC implementation.
第１図は本発明の一実施例を示す回路図、第２
図はその制御信号発生回路の具体例を示す回路
図、第３図は第１図の説明に使用される波形図、
第４図は本発明の応用例を示す回路図、及び第５
図は本発明の別の応用例を示す回路図である。
主な図番の説明、３……制御信号発生回路、
４，５……信号発生回路、６，７……信号分割回
路。
Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing an embodiment of the present invention.
The figure is a circuit diagram showing a specific example of the control signal generation circuit, and Figure 3 is a waveform diagram used to explain Figure 1.
FIG. 4 is a circuit diagram showing an application example of the present invention, and FIG.
The figure is a circuit diagram showing another example of application of the present invention. Explanation of main drawing numbers, 3...Control signal generation circuit,
4, 5... Signal generation circuit, 6, 7... Signal division circuit.
Claims (1)
波信号と逆相の第２矩形波信号と、前記第１及び
第２矩形波信号の第ｎ次（ただし、ｎは奇数）高
調波信号と等しい周波数の矩形波信号とを用い
て、周波数が前記第１矩形波信号の1/2になり、
所定のデユーテイを有する第１制御信号及び該第
１制御信号と逆相の第２制御信号とを発生する制
御信号発生回路、前記第１制御信号によりオンオ
フ制御され、前記第１制御信号のデユーテイに応
じて、前記第１矩形波信号のデユーテイ信号を発
生する第１信号発生回路、前記第１制御信号によ
りオンオフ制御され、前記第１制御信号のデユー
テイに応じて、前記第２矩形波信号のデユーテイ
信号を発生する第２信号発生回路、前記第２制御
信号に応じて前記第１矩形波信号をレベル分割
し、第１及び第２出力信号を発生する第１信号分
割回路、及び前記第２制御信号に応じて前記第２
矩形波信号をレベル分割し、第３及び第４出力信
号を発生する第２信号分割回路から成り、前記第
１及び第２分割回路の分割比をｎ：１に設定し、
前記第１信号発生回路の出力デユーテイ信号と前
記第１及び第４出力信号とを混合して前記第１矩
形波信号の高調波を除去するとともに、前記第２
信号発生回路の出力デユーテイ信号と前記第２及
び第３出力信号とを混合して前記第２矩形波信号
の高調波を除去する様にした高調波除去回路。1. A first rectangular wave signal of a predetermined frequency, a second rectangular wave signal having an opposite phase to the first rectangular wave signal, and an n-th (however, n is an odd number) harmonic of the first and second rectangular wave signals. using a rectangular wave signal of the same frequency as the signal, the frequency is 1/2 of the first rectangular wave signal,
a control signal generation circuit that generates a first control signal having a predetermined duty and a second control signal having a phase opposite to that of the first control signal; the control signal generating circuit is controlled on and off by the first control signal, and the duty of the first control signal is controlled; Accordingly, a first signal generation circuit generates a duty signal of the first rectangular wave signal, and is controlled on/off by the first control signal, and generates a duty signal of the second rectangular wave signal according to a duty of the first control signal. a second signal generation circuit that generates a signal, a first signal division circuit that divides the first rectangular wave signal into levels according to the second control signal and generates first and second output signals, and the second control signal. Said second according to the signal
comprising a second signal dividing circuit that divides the levels of a rectangular wave signal and generates third and fourth output signals, and a dividing ratio of the first and second dividing circuits is set to n:1;
The output duty signal of the first signal generation circuit and the first and fourth output signals are mixed to remove harmonics of the first rectangular wave signal, and
A harmonic removal circuit configured to remove harmonics of the second rectangular wave signal by mixing the output duty signal of the signal generation circuit and the second and third output signals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16704783A JPS6058725A (en) | 1983-09-09 | 1983-09-09 | Harmonic eliminating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16704783A JPS6058725A (en) | 1983-09-09 | 1983-09-09 | Harmonic eliminating circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6058725A JPS6058725A (en) | 1985-04-04 |
| JPH0252895B2 true JPH0252895B2 (en) | 1990-11-15 |
Family
ID=15842403
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16704783A Granted JPS6058725A (en) | 1983-09-09 | 1983-09-09 | Harmonic eliminating circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6058725A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2711343B2 (en) * | 1988-04-25 | 1998-02-10 | 日本電気アイシーマイコンシステム株式会社 | Pilot signal removal circuit |
-
1983
- 1983-09-09 JP JP16704783A patent/JPS6058725A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6058725A (en) | 1985-04-04 |
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