JPH0249140U - - Google Patents
Info
- Publication number
- JPH0249140U JPH0249140U JP12774388U JP12774388U JPH0249140U JP H0249140 U JPH0249140 U JP H0249140U JP 12774388 U JP12774388 U JP 12774388U JP 12774388 U JP12774388 U JP 12774388U JP H0249140 U JPH0249140 U JP H0249140U
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- printed circuit
- lead
- semiconductor device
- external lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 8
- 239000008188 pellet Substances 0.000 claims description 2
- 239000011347 resin Substances 0.000 claims description 2
- 229920005989 resin Polymers 0.000 claims description 2
- 238000004806 packaging method and process Methods 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第1図は本考案の一実施例にかかる半導体装置
の一部破断斜視図、第2図は第1図の半導体装置
の−断面図、第3図は同実施例に使用される
アイランド部と外部導出リードの斜視図、第4図
は本考案の他の実施例の半導体装置に使用される
アイランド部と外部導出リードの斜視図、第5図
は従来の半導体装置の一部破断斜視図である。
1……半導体ペレツト、2……プリント基板、
5……導電パターン、8……樹脂モールドパツケ
ージ、31,33……アイランド部、31a,3
3a……凹部、71……外部導出リード、72,
73……一端を延設した外部導出リード、72a
,73a……一端。
FIG. 1 is a partially cutaway perspective view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a sectional view of the semiconductor device of FIG. 1, and FIG. 3 is an island portion used in the embodiment. FIG. 4 is a perspective view of an island portion and external leads used in a semiconductor device according to another embodiment of the present invention, and FIG. 5 is a partially cutaway perspective view of a conventional semiconductor device. be. 1... Semiconductor pellet, 2... Printed circuit board,
5... Conductive pattern, 8... Resin mold package, 31, 33... Island portion, 31a, 3
3a... recess, 71... external lead-out lead, 72,
73...External lead-out lead with one end extended, 72a
, 73a... one end.
Claims (1)
ト基板をアイランド部に貼り合わせ、外部導出リ
ードと上記プリント基板の導電パターンとをワイ
ヤボンデイングした後樹脂モールドパツケージン
グしてなる半導体装置において、 上記アイランド部に外部導出リードに対応する
凹部を形成し、該凹部に上記外部導出リードの延
設された一端を進入させてアイランド部およびプ
リント基板の少なくとも一方と近接かつ絶縁して
接着したことを特徴とする半導体装置。[Scope of Claim for Utility Model Registration] A semiconductor device obtained by bonding a printed circuit board on which a plurality of semiconductor pellets are mounted to an island portion, wire bonding the external lead and the conductive pattern of the printed circuit board, and then resin mold packaging. A recess corresponding to the external lead-out lead is formed in the island part, and one extended end of the external lead-out lead is inserted into the recess and adhered in close proximity to and insulated from at least one of the island part and the printed circuit board. A semiconductor device characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12774388U JPH0249140U (en) | 1988-09-29 | 1988-09-29 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12774388U JPH0249140U (en) | 1988-09-29 | 1988-09-29 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0249140U true JPH0249140U (en) | 1990-04-05 |
Family
ID=31380445
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12774388U Pending JPH0249140U (en) | 1988-09-29 | 1988-09-29 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0249140U (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04136484A (en) * | 1990-09-28 | 1992-05-11 | Matsushita Electric Ind Co Ltd | Electronic ignitor |
JP2006253681A (en) * | 2005-03-07 | 2006-09-21 | Agere Systems Inc | Integrated circuit package |
US7230320B2 (en) | 2003-02-18 | 2007-06-12 | Hitachi, Ltd. | Electronic circuit device with reduced breaking and cracking |
JP2008066457A (en) * | 2006-09-06 | 2008-03-21 | Asmo Co Ltd | Connector integrated semiconductor module for controlling motor for motorcar |
-
1988
- 1988-09-29 JP JP12774388U patent/JPH0249140U/ja active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04136484A (en) * | 1990-09-28 | 1992-05-11 | Matsushita Electric Ind Co Ltd | Electronic ignitor |
US7230320B2 (en) | 2003-02-18 | 2007-06-12 | Hitachi, Ltd. | Electronic circuit device with reduced breaking and cracking |
JP2006253681A (en) * | 2005-03-07 | 2006-09-21 | Agere Systems Inc | Integrated circuit package |
JP2008066457A (en) * | 2006-09-06 | 2008-03-21 | Asmo Co Ltd | Connector integrated semiconductor module for controlling motor for motorcar |
JP4745925B2 (en) * | 2006-09-06 | 2011-08-10 | アスモ株式会社 | Connector integrated semiconductor module for automotive motor control |
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